CN220357446U - Enabling circuit for negative voltage output, power supply device and automatic test equipment - Google Patents
Enabling circuit for negative voltage output, power supply device and automatic test equipment Download PDFInfo
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- CN220357446U CN220357446U CN202320983377.8U CN202320983377U CN220357446U CN 220357446 U CN220357446 U CN 220357446U CN 202320983377 U CN202320983377 U CN 202320983377U CN 220357446 U CN220357446 U CN 220357446U
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- 238000012360 testing method Methods 0.000 title claims abstract description 23
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Abstract
The application relates to the field of semiconductor automation testing, in particular to a negative voltage output enabling circuit, a power supply device and automatic testing equipment, wherein the circuit comprises: the enabling control circuit is provided with a power supply end, an enabling end, a reference end and a control end, wherein the power supply end is connected with the positive power supply, the enabling end is connected with an enabling pin of the negative power supply chip, the reference end is connected with a reference ground of the negative power supply chip, and the enabling control circuit outputs an enabling signal based on a positive voltage output by the positive power supply and a negative voltage of the reference ground; and the controller is connected with the control end and used for controlling the output of the enabling signal of the enabling control circuit. The enabling circuit of the technical scheme can output a negative-level enabling signal without other negative-pressure power supplies; and meanwhile, the controller controls the output of the enabling signal of the enabling control circuit so as to realize the power-on time sequence control of the negative power chip.
Description
Technical Field
The present disclosure relates to the field of semiconductor automated testing, and in particular, to a negative voltage output enabling circuit, a power supply device, and an automatic testing apparatus.
Background
The automatic semiconductor test refers to that various parameter indexes of a tested device (Device Under Test, DUT) are detected by automatic test equipment (Automatic Test Equipment, ATE) and defective products are removed to control the factory quality of the semiconductor device. The hardware circuitry of semiconductor automated test equipment is often complex and involves multiple chips, and therefore in powering an analog IC, power supply designs for multiple negative voltage power supplies are often involved.
In the prior art, the specifications of chips capable of being used as negative-pressure power supplies are usually different, so that the level requirements of enabling pins are also different, and corresponding circuits are usually designed according to different power supply chip characteristics. The level calculation of the negative voltage power supply enabling pin is based on the internal ground of the chip, so that the level of the enabling signal is not a conventional level any more, but needs to be designed according to an actual scene, even negative values can occur, and the voltage of other negative voltage power supplies is generally used for dividing to obtain the enabling signal of the negative voltage.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a negative voltage output enabling circuit, a negative voltage power supply, a power supply device, and an automatic test equipment.
In a first aspect, an embodiment of the present utility model provides an enabling circuit for negative voltage output, connected to a negative power supply chip, where a voltage input pin of the negative power supply chip is connected to a positive power supply, the circuit includes:
the enabling control circuit is provided with a power supply end, an enabling end, a reference end and a control end, wherein the power supply end is connected with the positive power supply, the enabling end is connected with an enabling pin of the negative power supply chip, the reference end is connected with a reference ground of the negative power supply chip, and the enabling control circuit outputs an enabling signal based on a positive voltage output by the positive power supply and a negative voltage of the reference ground;
and the controller is connected with the control end and used for controlling the output of the enabling signal of the enabling control circuit.
In one embodiment, the enable control circuit includes: the switching circuit is further connected with the controller.
In one embodiment, the voltage divider circuit includes: a first resistor and a second resistor;
one end of the first resistor is used as a first power end to be connected with the positive power supply, and the other end of the first resistor is connected with the switching circuit;
one end of the second resistor is used as a reference end to be connected with the reference ground of the negative power supply chip, and the other end of the second resistor is connected with the switch circuit;
an intermediate node of the switching circuit and the second resistor serves as an enabling terminal.
In an embodiment, the switching circuit includes a third resistor, a first control switch, and a second control switch connected in series;
one end of the third resistor is used as a second power end to be connected with a positive power supply,
one end of the first control switch is used as a control end and connected with the controller and used for controlling the on-off of the second control switch;
the second control switch is connected with the third resistor, the first control switch and the voltage dividing circuit and used for controlling the on-off of the voltage dividing circuit.
In an embodiment, the first control switch includes a MOS transistor, a G pole of the MOS transistor is connected to the controller as a control end, an S pole is connected to a common ground, and a D pole is connected to the second control switch.
In an embodiment, the second control switch includes an optocoupler relay, a light emitting side of the optocoupler relay is connected between the third resistor and the second control switch, and a light sensing side of the optocoupler relay is connected in the voltage dividing circuit.
In an embodiment, the enabling control circuit further comprises: and the voltage stabilizing circuit is connected with the second resistor in parallel.
In an embodiment, the voltage stabilizing circuit includes a voltage stabilizing diode, wherein an anode of the voltage stabilizing diode is connected with a reference ground of the negative power supply chip, and a cathode of the voltage stabilizing diode is connected with an enabling pin of the negative power supply chip.
In a second aspect, an embodiment of the present utility model proposes a power supply device, including at least one positive power chip, at least one negative power chip, and a negative voltage output enabling circuit according to the first aspect.
In a third aspect, an embodiment of the present utility model proposes an automatic test equipment comprising a power supply device as described in the second aspect.
Compared with the prior art, the technical scheme has the following technical effects:
1. the enabling control circuit comprises a power end, an enabling end, a reference end and a control end, wherein the power end is connected with the positive power supply, the enabling end is connected with an enabling pin of the negative power supply chip, the reference end is connected with a reference ground of the negative power supply chip, and the enabling control circuit outputs an enabling signal based on a positive voltage output by the positive power supply and a negative voltage of the reference ground, so that the enabling circuit can output a negative-level enabling signal without other negative-voltage power supplies; meanwhile, the controller controls the output of the enabling signal of the enabling control circuit so as to realize the power-on time sequence control of the negative power chip;
2. the voltage of the enabling signal is effectively controlled through the voltage stabilizing circuit, and the negative power supply chip is effectively protected.
Drawings
FIG. 1 is a schematic diagram of an enable circuit in the prior art;
FIG. 2 is a schematic diagram illustrating connection of an enable circuit according to an embodiment of the present utility model;
FIG. 3 is a schematic diagram of an enabling circuit according to an embodiment of the present utility model;
fig. 4 is a schematic structural diagram of an automatic test equipment according to an embodiment of the present utility model.
Wherein, 10, enable the control circuit; 20. a controller; 101. a voltage dividing circuit; 102. a switching circuit; 103. and a voltage stabilizing circuit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
It is apparent that the drawings in the following description are only some examples or embodiments of the present application, and it is possible for those of ordinary skill in the art to apply the present application to other similar situations according to these drawings without inventive effort. Moreover, it should be appreciated that while such a development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as having the benefit of this disclosure.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by those of ordinary skill in the art that the embodiments described herein can be combined with other embodiments without conflict.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this application belongs. Reference to "a," "an," "the," and similar terms herein do not denote a limitation of quantity, but rather denote the singular or plural. The terms "comprising," "including," "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to only those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein refers to two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The terms "first," "second," "third," and the like, as used herein, are merely distinguishing between similar objects and not representing a particular ordering of objects.
FIG. 1 is a schematic diagram of an enable control circuit connection in the prior art. As shown in fig. 1, the enable control circuit includes resistors R1 and R2 connected in series, the resistor R1 is further connected to a negative power supply, the resistor R2 is further connected to a common ground, an intermediate node of the resistors R1 and R2 is connected to an enable pin En of a negative power supply chip, a voltage input pin Vin of the negative power supply chip is connected to a positive power supply (+12v), a voltage output pin Vout is connected to the common ground, and a reference terminal GND is used as an output.
As can be seen from fig. 1, the enable circuit needs other negative voltage power sources (-10V) to output the enable signal of negative level (-8V), and the power-on timing of the negative power chip is controlled by the other negative voltage power sources. However, these may result in an unnecessary addition of negative power to the automatic test equipment, increasing the design difficulty of the power-up timing of the entire system, and relying on other negative power supplies to power up is obviously not a highly reliable design. In particular, for automatic test equipment, high parallelism and test efficiency are the final demands of the market, so the internal space of the automatic test equipment is very precious, and the high-density channel design requirement is that unnecessary circuit design is simplified as much as possible on the premise of ensuring reliability, and the space cost brought by the design is not acceptable for the automatic test equipment.
Based on the above technical problems, as shown in fig. 2, the present embodiment provides an enabling circuit for negative voltage output, which is connected to a negative power supply chip, wherein a voltage input pin of the negative power supply chip is connected to a positive power supply, and the circuit includes: an enable control circuit 10 having a power supply terminal connected to the positive power supply, an enable terminal connected to an enable pin of the negative power supply chip, a reference terminal connected to a reference ground of the negative power supply chip, and a control terminal, the enable control circuit 10 outputting an enable signal based on a positive voltage output from the positive power supply and a negative voltage from the reference ground; and a controller 20 connected to the control terminal for controlling the output of the enable signal of the enable control circuit 10.
The controller 20 has a plurality of IO ports (IO 1, … …, IOn) through which control signals are output to control the output of the enable signal of the enable control circuit 10.
In this embodiment, the enable circuit and the negative power supply chip are both connected to the positive power supply, so that the enable signal of the negative level can be output without the need for another negative power supply. Next, power-on timing control of the negative power supply chip is achieved by the controller 20.
The structure of the enabling circuit is described in detail below with reference to fig. 3.
In one embodiment, the enable control circuit 10 includes: the voltage division circuit 101 and the switch circuit 102 connected in the voltage division circuit 101, the switch circuit 102 is also connected with the controller 20.
The controller 20 controls the on-off of the switch circuit 102 to control the on-off of the voltage dividing circuit 101, thereby realizing the power-on time sequence control of the negative power chip. The voltage dividing circuit 101 divides the voltage according to the difference between the voltage of the positive power supply and the voltage of the reference ground of the negative power supply chip, and outputs an enable signal after dividing the voltage.
In one embodiment, the voltage dividing circuit 101 includes: a first resistor R1 and a second resistor R2; one end of the first resistor R1 is used as a first power supply end and connected with the positive power supply, and the other end of the first resistor R1 is connected with the switch circuit 102; one end of the second resistor R2 is used as a reference end and connected with the reference ground of the negative power supply chip, and the other end of the second resistor R2 is connected with the switch circuit 102; the intermediate node of the switching circuit 102 and the second resistor R2 serves as an enable terminal.
In one embodiment, the switching circuit 102 includes a third resistor R3, a first control switch, and a second control switch connected in series. One end of the third resistor R3 is connected to a positive power supply as a second power supply end, and one end of the first control switch is connected to the controller 20 as a control end for controlling the on-off state of the second control switch; the second control switch is connected to the third resistor R3, the first control switch, and the voltage dividing circuit 101, and is configured to control on/off of the voltage dividing circuit 101.
In an embodiment, the first control switch includes a MOS transistor Q1, a G pole of the MOS transistor Q1 is connected to the controller 20 as a control end, an s pole is connected to a common ground, and a D pole is connected to the second control switch.
In an embodiment, the second control switch includes an optocoupler relay Q2, the light emitting side of the optocoupler relay Q2 is connected between the third resistor R3 and the second control switch, and the light sensing side of the optocoupler relay Q2 is connected in the voltage divider circuit 101, specifically between the resistors R1 and R2.
The light emitting side of the optocoupler relay Q2 is a light emitting diode, and the photosensitive side of the optocoupler relay Q2 is a relay.
In an embodiment, the enabling control circuit 10 further comprises: and a voltage stabilizing circuit 103 connected in parallel with the second resistor R2. The voltage of the enabling signal is effectively controlled through the voltage stabilizing circuit, and the negative power supply chip is effectively protected.
In an embodiment, the voltage stabilizing circuit 103 includes a voltage stabilizing diode D1, where an anode of the voltage stabilizing diode D1 is connected to the reference ground GND of the negative power supply chip, and a cathode of the voltage stabilizing diode D1 is connected to the enable pin En of the negative power supply chip.
The operation principle of the enable circuit will be specifically described below by taking the negative power chip output-6V voltage as an example. Wherein, positive power supply output voltage is +12V, and resistance R1 is 15KΩ, and resistance R2 is 3KΩ, and resistance R3 is 2KΩ, and controller 20 output control signal is 3.3V.
When the controller 20 does not work or does not output a 3.3V control signal, the MOS transistor Q1 is disconnected, and the light emitting diode cathode of the light emitting side of the optocoupler relay Q2 is positionedIn a suspended state, the relay on the photosensitive side is disconnected; only when the IO pin of the controller 20 outputs a control signal of 3.3V, the MOS tube Q1 is conducted, at the moment, the negative electrode of the light emitting diode is communicated with the public ground, and the relay is conducted. For the enable pin En of the negative power supply chip, when the optocoupler relay is disconnected, the enable pin En is pulled down to the internal ground through the resistor R2, at the moment, the enable pin En does not do suspension processing, so that the enable pin En can be prevented from being turned on when the enable pin En is suspended, and at the moment, the negative power supply chip is in a turned-off state; when the optocoupler relay Q2 is turned on, the enable pin En is pulled up to +12V for conduction, and the voltage difference between the enable pin En and the internal pin GND (-6V output) is obtained according to the resistor voltage division calculation According to the calculation of negative power chip with SGM61163, when the output is-6V, the high level range of the corresponding enabling signal is between-4.8V and 0V, at this time V en = -3V may meet chip pin requirements.
In addition, for reliability and design simplicity, a 3.3V zener diode D1 is connected in parallel across the second resistor R2 to ensureThe value of (2) is always less than 3.3V, and even if the resistance of the designed voltage division circuit 101 is not strict enough, the zener diode D1 can ensure +.>The value of (2) is always clamped between 0V and 3.3V, which can ensure that even if there is a design defect resulting in +.>When the voltage born by the chip pins exceeds the voltage born by the chip pins, the voltage stabilizing circuit can effectively protect the chip so that the chip is not burnt, therefore, the design can be realized by only ensuring that the level value of the enable pin EN is enough to turn on the negative power supply chip after voltage divisionNow functional requirements. By the design of the enabling circuit, the controller 20 is equivalent to controlling the power-on of the negative power supply chip, and the related device delay time of the enabling control circuit 10 is low (< 3 ms), so that the power-on time sequence can be directly designed at the end of the controller 20.
In this embodiment, the device including the N-channel MOSFET Q1, the optocoupler relay Q2, and the zener diode D1 is used as the enable control circuit 10 of the negative power chip, so as to complete the adapting process of the control signal from the controller 20, increase the cost less, and select the components with smaller occupation area, so that the circuit area of the automatic test equipment is not wasted.
In an embodiment, as shown in fig. 4, a power supply device is also provided, which includes at least one positive power chip, at least one negative power chip, and an enable circuit for outputting negative voltage, where the enable circuit includes an enable control circuit and a controller.
It should be noted that, the enabling circuit is already described in detail in the above embodiments, and thus, the details are not repeated in this embodiment. Since the power supply device includes the enable circuit in the above-described embodiment, the same technical effects are achieved.
In an embodiment, an automatic test equipment is also provided, including the above power supply device.
It should be noted that, the enabling circuit is already described in detail in the above embodiments, and thus, the details are not repeated in this embodiment. Since the automatic test equipment includes the enabling circuit in the above-described embodiment, the same technical effects are achieved.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the utility model. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
Claims (10)
1. An enabling circuit for negative voltage output, connected to a negative power supply chip, wherein a voltage input pin of the negative power supply chip is connected to a positive power supply, the circuit comprising:
the enabling control circuit is provided with a power supply end, an enabling end, a reference end and a control end, wherein the power supply end is connected with the positive power supply, the enabling end is connected with an enabling pin of the negative power supply chip, the reference end is connected with a reference ground of the negative power supply chip, and the enabling control circuit outputs an enabling signal based on a positive voltage output by the positive power supply and a negative voltage of the reference ground;
and the controller is connected with the control end and used for controlling the output of the enabling signal of the enabling control circuit.
2. The negative voltage output enabling circuit according to claim 1, wherein the enabling control circuit includes: the switching circuit is further connected with the controller.
3. The negative voltage output enabling circuit according to claim 2, wherein the voltage dividing circuit includes: a first resistor and a second resistor;
one end of the first resistor is used as a first power end to be connected with the positive power supply, and the other end of the first resistor is connected with the switching circuit;
one end of the second resistor is used as a reference end to be connected with the reference ground of the negative power supply chip, and the other end of the second resistor is connected with the switch circuit;
an intermediate node of the switching circuit and the second resistor serves as an enabling terminal.
4. The negative voltage output enabling circuit according to claim 2, wherein the switching circuit includes a third resistor, a first control switch, and a second control switch connected in series;
one end of the third resistor is used as a second power end to be connected with a positive power supply,
one end of the first control switch is used as a control end and connected with the controller and used for controlling the on-off of the second control switch;
the second control switch is connected with the third resistor, the first control switch and the voltage dividing circuit and used for controlling the on-off of the voltage dividing circuit.
5. The negative voltage output enabling circuit according to claim 4, wherein the first control switch comprises a MOS transistor, a G pole of the MOS transistor is connected to the controller as a control terminal, the S pole is connected to a common ground, and a D pole is connected to the second control switch.
6. The negative voltage output enabling circuit according to claim 4, wherein the second control switch includes an optocoupler relay, a light emitting side of the optocoupler relay is connected between the third resistor and the second control switch, and a light sensing side of the optocoupler relay is connected in the voltage dividing circuit.
7. The negative voltage output enabling circuit according to claim 3, wherein the enabling control circuit further comprises: and the voltage stabilizing circuit is connected with the second resistor in parallel.
8. The negative voltage output enabling circuit according to claim 7, wherein the voltage stabilizing circuit comprises a voltage stabilizing diode, the positive electrode of the voltage stabilizing diode is connected with the reference ground of the negative power supply chip, and the negative electrode of the voltage stabilizing diode is connected with the enabling pin of the negative power supply chip.
9. A power supply device comprising at least one positive power supply chip, at least one negative power supply chip, and an enabling circuit for negative voltage output according to any one of claims 1-8.
10. An automatic test equipment comprising the power supply device according to claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320983377.8U CN220357446U (en) | 2023-04-26 | 2023-04-26 | Enabling circuit for negative voltage output, power supply device and automatic test equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320983377.8U CN220357446U (en) | 2023-04-26 | 2023-04-26 | Enabling circuit for negative voltage output, power supply device and automatic test equipment |
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| Publication Number | Publication Date |
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| CN220357446U true CN220357446U (en) | 2024-01-16 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202320983377.8U Active CN220357446U (en) | 2023-04-26 | 2023-04-26 | Enabling circuit for negative voltage output, power supply device and automatic test equipment |
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- 2023-04-26 CN CN202320983377.8U patent/CN220357446U/en active Active
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