CN220342749U

CN220342749U - Display substrate and display device

Info

Publication number: CN220342749U
Application number: CN202321557083.5U
Authority: CN
Inventors: 方飞; 黎倩; 王铸; 闫政龙; 石领; 尚延阳; 张玉欣
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2023-06-16
Filing date: 2023-06-16
Publication date: 2024-01-12
Anticipated expiration: 2033-06-16

Abstract

The utility model relates to the technical field of display, and provides a display substrate aiming at the problem that the light transmittance and the size of an under-screen camera area are to be improved, which comprises the following components: the display device includes a substrate, a plurality of first light emitting units and a plurality of second light emitting units located in a first display area, a plurality of first pixel circuits located in the first display area, and a plurality of second pixel circuits located in a second display area. The first light emitting unit includes at least one first light emitting element, and the second light emitting unit includes at least one second light emitting element. The at least one first light emitting unit is adjacent to the at least one second light emitting unit. The at least one first pixel circuit is electrically connected to the at least one first light emitting element and configured to drive the at least one first light emitting element to emit light. The at least one second pixel circuit is electrically connected to the at least one second light emitting element and configured to drive the at least one second light emitting element to emit light. The light transmittance of the first display area can be ensured, and an increase in the size of the first display area is supported.

Description

Display substrate and display device

Technical Field

The present utility model relates to the field of display technologies, and in particular, to a display substrate and a display device.

Background

An organic light emitting diode (OLED, organic Light Emitting Diode) and a Quantum-dot light emitting diode (QLED, quantum-dot Light Emitting Diode) are active light emitting display devices, and have advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high reaction speed, thinness, flexibility, low cost, and the like.

Disclosure of Invention

The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

The embodiment of the utility model provides a display substrate and a display device.

In one aspect, the present embodiment provides a display substrate, including: the light emitting diode includes a substrate, a plurality of first light emitting units, a plurality of second light emitting units, a plurality of first pixel circuits, and a plurality of second pixel circuits. The substrate comprises a first display area and a second display area positioned on at least one side of the first display area. The first light-emitting units and the second light-emitting units are positioned in the first display area; the first light emitting unit comprises at least one first light emitting element, and the second light emitting unit comprises at least one second light emitting element; the first light emitting unit is adjacent to at least one second light emitting unit. A plurality of first pixel circuits are positioned in the first display area; at least one first pixel circuit of the plurality of first pixel circuits is electrically connected to the at least one first light emitting element and configured to drive the at least one first light emitting element to emit light. A plurality of second pixel circuits are positioned in the second display area; at least one second pixel circuit of the plurality of second pixel circuits is electrically connected to the at least one second light emitting element and configured to drive the at least one second light emitting element to emit light.

In some exemplary embodiments, the plurality of first light emitting units and the plurality of second light emitting units are disposed at intervals along at least one of the first direction and the second direction; the first direction intersects the second direction.

In some exemplary embodiments, one first light emitting unit and one second light emitting unit are disposed at intervals in the first direction; in the second direction, a first light emitting unit and a second light emitting unit are disposed at intervals.

In some exemplary embodiments, the plurality of first light emitting units includes: a plurality of columns of first light emitting units; each column of first light emitting units comprises a plurality of first light emitting units which are sequentially arranged along the second direction. The plurality of second light emitting units includes: and a plurality of columns of second light emitting units, each column of second light emitting units comprising a plurality of second light emitting units sequentially arranged along the second direction. In the first direction, a column of first light emitting units and a column of second light emitting units are arranged at intervals.

In some exemplary embodiments, the plurality of first light emitting units includes a plurality of rows of first light emitting units, each row of first light emitting units including a plurality of first light emitting units disposed sequentially along the first direction. The plurality of second light emitting units includes a plurality of rows of second light emitting units, each row of second light emitting units including a plurality of second light emitting units disposed in sequence along the first direction. In the second direction, a row of first light emitting units and a row of second light emitting units are arranged at intervals.

In some exemplary embodiments, the first light emitting unit and the second light emitting unit adjacent in the first direction are disposed in alignment, and the first light emitting unit and the second light emitting unit adjacent in the second direction are disposed in alignment; alternatively, there is a misalignment of the first light emitting unit and the second light emitting unit adjacent in the second direction.

In some exemplary embodiments, a ratio of light emitting areas of the second light emitting element and the first light emitting element emitting the same color light is less than 1.

In some exemplary embodiments, the at least one first light emitting unit includes the same number of first light emitting elements as the at least one second light emitting unit includes the same number of second light emitting elements.

In some exemplary embodiments, the at least one first light emitting unit includes four first light emitting elements: a first light emitting element emitting light of a first color, a first light emitting element emitting light of a second color, and two first light emitting elements emitting light of a third color. The at least one second light emitting unit includes the following four second light emitting elements: a second light emitting element emitting light of the first color, a second light emitting element emitting light of the second color, and two second light emitting elements emitting light of the third color.

In some exemplary embodiments, the plurality of first light emitting elements and the plurality of second light emitting elements of the first display region are arranged in a plurality of rows and a plurality of columns. In the at least one first light emitting unit, the two first light emitting elements emitting the third color light are arranged in the same column, the first light emitting element emitting the first color light and the first light emitting element emitting the second color light are arranged in the same column, and the four first light emitting elements of the first light emitting unit are arranged in different rows. In the at least one second light emitting unit, the two second light emitting elements emitting the third color light are arranged in the same column, the second light emitting element emitting the first color light and the second light emitting element emitting the second color light are arranged in the same column, and the four first light emitting elements of the second light emitting unit are arranged in different rows.

In some exemplary embodiments, the plurality of first light emitting elements and the plurality of second light emitting elements of the first display region are arranged in a plurality of rows and a plurality of columns. In the at least one first light emitting unit, the two first light emitting elements emitting the third color light are arranged in the same row, the first light emitting element emitting the first color light and the first light emitting element emitting the second color light are arranged in the same row, and the four first light emitting elements of the first light emitting unit are arranged in different columns. In the at least one second light emitting unit, the two second light emitting elements emitting the third color light are arranged in the same row, the first light emitting element emitting the first color light and the second light emitting element emitting the second color light are arranged in the same row, and the four second light emitting elements of the second light emitting unit are arranged in different columns.

In some exemplary embodiments, four first light emitting elements in the first light emitting unit are electrically connected in one-to-one correspondence with four first pixel circuits, the four first pixel circuits being sequentially arranged along a first direction, and an orthographic projection of each first pixel circuit on the substrate at least partially overlaps an orthographic projection of the connected first light emitting element on the substrate.

In some exemplary embodiments, the four first pixel circuits are symmetrically disposed about a first center line of the four first pixel circuits along the first direction, a first one of the four first pixel circuits and a second one of the four first pixel circuits are symmetrically disposed about a second center line of the two first pixel circuits along the first direction, and a third one of the four first pixel circuits and a fourth one of the four first pixel circuits are symmetrically disposed about a third center line of the two first pixel circuits along the first direction.

In some exemplary embodiments, the four first pixel circuits are electrically connected to a first power line, and the first power line is in a grid shape in the first display area.

In some exemplary embodiments, in a direction perpendicular to a display substrate, the display substrate includes: a circuit structure layer on the substrate; the circuit structure layer includes the plurality of first pixel circuits and the plurality of second pixel circuits; each of the plurality of first pixel circuits and the plurality of second pixel circuits includes: at least one first type transistor, at least one second type transistor, and a storage capacitor. The circuit structure layer includes: the semiconductor device includes a first semiconductor layer, a first conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on the substrate. The first semiconductor layer includes at least: an active layer of a first type transistor of the pixel circuit; the first conductive layer includes at least: a gate electrode of a first type transistor of the pixel circuit, a first electrode of a storage capacitor; the second conductive layer includes at least: a second electrode of the storage capacitor of the pixel circuit; the second semiconductor layer includes at least: an active layer of a second type transistor of the pixel circuit; the third conductive layer includes at least: a gate of a second type transistor of the pixel circuit; the fourth conductive layer includes at least: a plurality of connection electrodes; the fifth conductive layer includes at least: a plurality of data lines; the sixth conductive layer includes at least: a first power line.

In some exemplary embodiments, the first display area includes: a plurality of first sub-regions and a plurality of second sub-regions; at least one first sub-area of the plurality of first sub-areas is provided with at least one first light emitting unit and at least one second sub-area of the plurality of second sub-areas is provided with at least one second light emitting unit. The second conductive layer further includes: a first scan line, a light emission control line, a first reset control line, and a second reset control line electrically connected to the first pixel circuit; the first scan line, the light emission control line, the first reset control line, and the second reset control line extend in a first direction. In a second direction, the first scan line and the first reset control line bypass from one side of the second sub-region, and the light emission control line and the second reset control line bypass from the other side of the second sub-region; the second direction intersects the first direction.

In some exemplary embodiments, the first display area includes: a plurality of first sub-regions and a plurality of second sub-regions; at least one first sub-area of the plurality of first sub-areas is provided with at least one first light emitting unit and at least one second sub-area of the plurality of second sub-areas is provided with at least one second light emitting unit. The third conductive layer further includes: a first initial signal line, a second initial signal line, a third initial signal line, and a second scan line electrically connected to the first pixel circuit; the first initial signal line, the second initial signal line, the third initial signal line, and the second scan line extend in a first direction. In a second direction, the first initial signal line and the second scan line bypass from one side of the second sub-region, and the second initial signal line and the third initial signal line bypass from the other side of the second sub-region; the second direction intersects the first direction.

In some exemplary embodiments, the first and second light emitting units of the first display area have a number ratio of 0.8 to 1.2.

In some exemplary embodiments, the first display region has a light transmittance that is greater than a light transmittance of the second display region. The display substrate further includes: a plurality of third light emitting elements and a plurality of third pixel circuits in the second display area, at least one third pixel circuit in the plurality of third pixel circuits is electrically connected with at least one third light emitting element in the plurality of third light emitting elements, and is configured to drive the at least one third light emitting element to emit light. The plurality of second pixel circuits are arranged between the plurality of third pixel circuits at intervals.

In some exemplary embodiments, the orthographic projection of the at least one first pixel circuit at the substrate overlaps with the orthographic projection of the at least one first light emitting element at the substrate. The at least one second pixel circuit is electrically connected with the at least one second light emitting element through at least one conductive connection line; the orthographic projection of the at least one second pixel circuit on the substrate and the orthographic projection of the at least one second light emitting element on the substrate are not overlapped.

In some exemplary embodiments, the orthographic projection of the at least one electrically conductive connection line on the substrate overlaps with the orthographic projection of the at least one first pixel circuit on the substrate.

In another aspect, the present embodiment provides a display device including the display substrate as described above, and a sensor located on a non-display surface side of the display substrate, where a front projection of the sensor on the display substrate at least partially overlaps with a first display area of the display substrate.

The display substrate provided by the embodiment adopts a mode of combining the external arrangement and the internal arrangement of the pixel circuit, so that the light transmittance of the first display area can be ensured, and the size of the first display area can be increased.

Other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

Drawings

The accompanying drawings are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate and do not limit the utility model.

FIG. 1 is a schematic diagram of a display substrate according to at least one embodiment of the utility model;

FIG. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the present utility model;

FIG. 3 is a timing diagram illustrating operation of the pixel circuit of FIG. 2;

FIGS. 4A and 4B are partial schematic views of a first display area according to at least one embodiment of the utility model;

FIG. 5 is a schematic diagram illustrating a connection relationship between a light emitting device and a pixel circuit according to at least one embodiment of the present utility model;

FIG. 6 is a partial top view of a first display area according to at least one embodiment of the utility model;

FIG. 7A is a schematic view of the first display region of FIG. 6 after forming the first semiconductor layer;

FIG. 7B is a schematic view of a first sub-region of FIG. 7A;

FIG. 8A is a schematic view of the first display region of FIG. 6 after forming a first conductive layer;

FIG. 8B is a schematic diagram of the first conductive layer of FIG. 8A;

FIG. 8C is a schematic view of a first sub-region of FIG. 8A;

FIG. 9A is a schematic view of the first display region of FIG. 6 after forming a second conductive layer;

FIG. 9B is a schematic diagram of the second conductive layer of FIG. 9A;

FIG. 9C is a schematic view of a first sub-region of FIG. 9A;

FIG. 10A is a schematic view of the first display region of FIG. 6 after forming a second semiconductor layer;

FIG. 10B is a schematic view of the second semiconductor layer of FIG. 10A;

FIG. 10C is a schematic view of a first sub-region of FIG. 10A;

FIG. 11A is a schematic view of the first display region of FIG. 6 after forming a third conductive layer;

FIG. 11B is a schematic diagram of the third conductive layer of FIG. 11A;

FIG. 11C is a schematic view of a first sub-region of FIG. 11A;

FIG. 12 is a schematic view of a first sub-region of the fifth insulating layer of FIG. 6;

FIG. 13A is a schematic view of the first display region of FIG. 6 after forming a fourth conductive layer;

FIG. 13B is a schematic view of the fourth conductive layer of FIG. 13A;

FIG. 13C is a schematic view of a first sub-region of FIG. 13A;

FIG. 14 is a schematic view of a first sub-region of the seventh insulating layer of FIG. 6;

FIG. 15A is a schematic view of the first display region of FIG. 6 after forming a fifth conductive layer;

FIG. 15B is a schematic view of the fifth conductive layer of FIG. 15A;

FIG. 15C is a schematic view of a first sub-region of FIG. 15A;

FIG. 16 is a schematic view of a first sub-region of the eighth insulating layer of FIG. 6;

FIG. 17A is a schematic view of the first display region of FIG. 6 after forming a sixth conductive layer;

FIG. 17B is a schematic diagram of the sixth conductive layer of FIG. 17A;

FIG. 17C is a schematic view of a first sub-region of FIG. 17A;

FIG. 18 is a schematic view of the first display region of FIG. 6 after forming a ninth insulating layer;

FIG. 19A is a schematic view of the first display region of FIG. 6 after the conductive connection layer is formed;

FIG. 19B is a schematic view of the conductive connection layer of FIG. 19A;

FIG. 20 is a schematic view of the first display region of FIG. 6 after forming an anode layer;

FIG. 21 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 22 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 23 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 24 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 25 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 26 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 27 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 28 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 29 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 30 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 31 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 32 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 33 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 34 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

FIG. 35 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model;

fig. 36 is a schematic view of a display device according to at least one embodiment of the utility model.

Detailed Description

Embodiments of the present utility model will be described in detail below with reference to the accompanying drawings. Embodiments may be implemented in a number of different forms. One of ordinary skill in the art will readily recognize the fact that the manner and content may be changed into other forms without departing from the spirit and scope of the present utility model. Therefore, the present utility model should not be construed as being limited to the following embodiments. Embodiments of the utility model and features of the embodiments may be combined with one another arbitrarily without conflict.

In the drawings, the size of one or more constituent elements, thicknesses of layers or regions may be exaggerated for clarity. Accordingly, one aspect of the utility model is not necessarily limited to this dimension, and the shape and size of one or more of the components in the drawings do not reflect true proportions. Further, the drawings schematically show ideal examples, and one embodiment of the present utility model is not limited to the shapes, numerical values, and the like shown in the drawings.

The ordinal numbers of "first", "second", "third", etc. in the present specification are provided to avoid mixing of constituent elements, and are not intended to be limited in number. The term "plurality" in the present utility model means two or more.

In the present specification, for convenience, words such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like, which indicate an azimuth or a positional relationship, are used to describe the positional relationship of the constituent elements with reference to the drawings, only for convenience of description of the present specification and simplification of the description, and do not indicate or imply that the apparatus or elements referred to must have a specific azimuth, be constructed and operated in a specific azimuth, and thus should not be construed as limiting the present utility model. The positional relationship of the constituent elements is appropriately changed according to the direction of the described constituent elements. Therefore, the present utility model is not limited to the words described in the specification, and may be appropriately replaced according to circumstances.

In this specification, the terms "mounted," "connected," and "connected" are to be construed broadly, unless explicitly stated or limited otherwise. For example, it may be a fixed connection, a removable connection, or an integral connection; may be a mechanical connection, or a connection; may be directly connected, or indirectly connected through intermediate members, or may be in communication with the interior of two elements. The meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to circumstances.

In this specification, "electrically connected" includes a case where constituent elements are connected together by an element having some electric action. The "element having a certain electric action" is not particularly limited as long as it can transmit an electric signal between the connected constituent elements. Examples of the "element having some electric action" include not only an electrode and a wiring but also a switching element such as a transistor, a resistor, an inductor, a capacitor, other elements having various functions, and the like.

In this specification, a transistor means an element including at least three terminals of a gate, a drain, and a source. The transistor has a channel region between a drain (drain electrode terminal, drain region, or drain electrode) and a source (source electrode terminal, source region, or source electrode), and a current can flow through the drain, the channel region, and the source. In this specification, a channel region refers to a region through which current mainly flows.

In this specification, the first pole may be a drain electrode, the second pole may be a source electrode, or the first pole may be a source electrode, and the second pole may be a drain electrode. In the case of using transistors having opposite polarities, or in the case of a change in current direction during circuit operation, the functions of the "source" and the "drain" may be exchanged with each other. Thus, in this specification, "source" and "drain" may be interchanged. In addition, the gate may also be referred to as a control electrode.

In the present specification, "parallel" means a state in which two straight lines form an angle of-10 ° or more and 10 ° or less, and therefore, a state in which the angle is-5 ° or more and 5 ° or less is also included. The term "perpendicular" refers to a state in which the angle formed by two straight lines is 80 ° or more and 100 ° or less, and thus includes a state in which the angle is 85 ° or more and 95 ° or less.

In the present specification, a circle, an ellipse, a triangle, a rectangle, a trapezoid, a pentagon, a hexagon, or the like is not strictly defined, and may be an approximate circle, an approximate ellipse, an approximate triangle, an approximate rectangle, an approximate trapezoid, an approximate pentagon, an approximate hexagon, or the like, and some small deformation due to a tolerance may exist, for example, a lead angle, an arc edge, deformation, or the like may exist.

The term "light transmittance" as used herein refers to the ability of light to pass through a medium, and refers to the percentage of the light flux transmitted through a transparent or translucent body to the light flux incident thereto.

The terms "about" and "approximately" in the present utility model refer to a situation in which the limits are not strictly defined, and the process and measurement errors are allowed. In the present utility model, "substantially the same" means a case where the values differ by 10% or less.

In the present utility model, a extending in the B direction means that a may include a main body portion and a sub portion connected to the main body portion, the main body portion being a line, a line segment or a bar-shaped body, the main body portion extending in the B direction, and the main body portion extending in the B direction for a length greater than that of the sub portion extending in other directions. The term "a extends in the B direction" as used herein means that the main body portion of a extends in the B direction.

With the continuous development of display technology, a camera is usually installed on a display device to meet shooting or face recognition requirements. In order to maximize the screen duty ratio, liu Haibing, water drop screen, in-screen hollowing and other technologies appear successively. The technology is that the area occupied by the camera is reduced by digging holes in the part of the display area and placing the camera below the digging hole area, so that the screen occupation ratio is improved. However, the above technique requires digging out a part of the display area, which may cause that the part of the display area cannot be displayed, and the screen ratio cannot be further improved. In order to avoid punching holes in the display area and to enable a true full screen on the premise of ensuring the practicability of the display substrate, an external pixel circuit method or an internal pixel circuit method is generally adopted in the under-screen camera area.

The pixel circuit external method is to set the pixel circuit connected with the light emitting element in the under-screen camera area in the normal display area, and to improve the light transmittance of the under-screen camera area by separately arranging the light emitting element and the pixel circuit. Because the under-screen camera area is not provided with a pixel circuit, the area is not provided with other shading layers except the anode of the light-emitting element, and higher light transmittance can be realized. However, in this method, the pixel circuit and the light emitting element need to be electrically connected by the conductive connection line, which is limited by the arrangement space of the conductive connection line, and the size (for example, aperture) of the under-screen camera region of the display substrate adopting the pixel circuit external method is limited. Increasing the aperture of the under-screen camera area typically requires a masking process that adds conductive connections, resulting in increased costs. Moreover, the material of the conductive connection line is usually a transparent conductive material, such as Indium Tin Oxide (ITO), and due to the large sheet resistance of the ITO, the load of the conductive connection line is large, which easily affects the brightness of the light emitting element of the under-screen camera area, so that the brightness of the under-screen camera area is reduced, thereby causing poor display of the under-screen camera area, such as causing vertical poor display (Mura).

The pixel circuit built-in method is to provide a light emitting element and a pixel circuit to which the light emitting element is connected in an under-screen camera region. Compared with an external pixel circuit method, the electric connection between the pixel circuit of the under-screen camera area adopting the internal method and the light-emitting element does not need to adopt a longer conductive connecting wire, so that poor display condition of the under-screen camera area caused by the conductive connecting wire can be avoided, the size of the under-screen camera area is not limited by the internal method, and the under-screen camera area with a large aperture can be supported. However, in the display substrate adopting the pixel circuit built-in method, since the anode of the light emitting element of the under-screen camera region cannot completely block the pixel circuit, the light transmittance of the under-screen camera region may be affected.

The embodiment provides a display substrate and a display device, which can support increasing the size of an under-screen camera region on the basis of ensuring the light transmittance of the under-screen camera region.

The present embodiment provides a display substrate, including: the light emitting diode includes a substrate, a plurality of first light emitting units, a plurality of second light emitting units, a plurality of first pixel circuits, and a plurality of second pixel circuits. The substrate includes a first display region and a second display region located on at least one side of the first display region. The plurality of first light-emitting units and the plurality of second light-emitting units are positioned in the first display area; the first light emitting unit includes at least one first light emitting element, and the second light emitting unit includes at least one second light emitting element. The first light emitting unit is adjacent to the at least one second light emitting unit. The plurality of first pixel circuits are positioned in the first display area; at least one first pixel circuit of the plurality of first pixel circuits is electrically connected to the at least one first light emitting element and configured to drive the at least one first light emitting element to emit light. The plurality of second pixel circuits are positioned in the second display area; at least one second pixel circuit of the plurality of second pixel circuits is electrically connected to at least one second light emitting element and configured to drive the at least one second light emitting element to emit light.

In some exemplary embodiments, the plurality of first light emitting units and the plurality of second light emitting units may be disposed at intervals in at least one of the first direction and the second direction. Wherein the first direction intersects the second direction. For example, the first direction may be perpendicular to the second direction. In some examples, the plurality of first light emitting units and the plurality of second light emitting units may be disposed at intervals in both the first direction and the second direction. For example, in the first direction, one first light emitting unit and one second light emitting unit are arranged at intervals; in the second direction, a first light emitting unit and a second light emitting unit are disposed at intervals. In other examples, the plurality of first light emitting units and the plurality of second light emitting units may be disposed at intervals only in the first direction or the second direction. According to the display substrate, the first light-emitting units and the second light-emitting units are arranged at intervals, so that the light-emitting elements outside the pixel circuits and the light-emitting elements inside the pixel circuits can be reasonably distributed, the optimal combination of the light transmittance and the size of the first display area is realized, and the performance and the user experience of the display substrate are improved. Moreover, the first light-emitting unit and the second light-emitting unit are arranged at intervals, so that brightness compensation between the first light-emitting element and the second light-emitting element is facilitated, and brightness uniformity of the first display area is improved.

In some exemplary embodiments, a ratio of light emitting areas of the second light emitting element and the first light emitting element emitting the same color light may be less than 1. In some examples, the ratio of the light emitting areas of the second light emitting element and the first light emitting element emitting the same color light may be 0.4 to 0.8, for example, may be about 0.5. The example can improve the condition of dark brightness caused by the external pixel circuit of the second light-emitting element by reducing the light-emitting area of the second light-emitting element.

In some exemplary embodiments, the number of first light emitting elements included in the at least one first light emitting unit may be the same as the number of second light emitting elements included in the at least one second light emitting unit. In some examples, the at least one first light emitting unit may include four first light emitting elements: a first light emitting element emitting light of a first color, a first light emitting element emitting light of a second color, and two first light emitting elements emitting light of a third color. The at least one second light emitting unit may include the following four second light emitting elements: a second light emitting element emitting light of the first color, a second light emitting element emitting light of the second color, and two second light emitting elements emitting light of the third color. However, the present embodiment is not limited thereto. For example, the first light emitting unit and the second light emitting unit may each include three light emitting elements. The first light emitting unit and the second light emitting unit are arranged to have the same number of light emitting elements, so that adjacent light emitting elements emitting light with the same color can be favorably compensated for brightness, and brightness uniformity of the first display area is facilitated.

In some exemplary embodiments, the number ratio of the first light emitting unit and the second light emitting unit of the first display area may be 0.8 to 1.2, for example, may be about 1. The number ratio of the first light emitting units and the second light emitting units of the present example can effectively alleviate the number and the wiring space of the conductive connection lines connected to the external pixel circuit, and can support the increase in the size of the first display area.

In some exemplary embodiments, the light transmittance of the first display region may be greater than the light transmittance of the second display region. The display substrate may further include: a plurality of third light emitting elements and a plurality of third pixel circuits in the second display region. The at least one third pixel circuit is electrically connected to the at least one third light emitting element and configured to drive the at least one third light emitting element to emit light. The plurality of second pixel circuits may be disposed at intervals between the plurality of third pixel circuits. The display effect of the display substrate can be ensured by setting the second display region having the light transmittance smaller than that of the first display region.

In some examples, the sum of the number of first and second light emitting elements per unit area may be less than or equal to the number of third light emitting elements per unit area. Alternatively, the density of the first light emitting element and the second light emitting element in the first display region may be less than or equal to the density of the third light emitting element in the second display region. Alternatively, the pixel density (PPI, pixels Per Inch) of the first display region may be less than or equal to the pixel density of the second display region.

The scheme of the present embodiment is illustrated by some examples below.

Fig. 1 is a schematic view of a display substrate according to at least one embodiment of the utility model. In some examples, as shown in fig. 1, the display substrate may include: a display area AA and a peripheral area BB located at the periphery of the display area AA. The display area AA of the display substrate may include at least: a first display area A1 and a second display area A2. The second display area A2 may at least partially surround the first display area A1. For example, the second display area A2 may surround the first display area A1. The peripheral area BB may surround the second display area A2. However, the present embodiment is not limited thereto.

In some examples, as shown in fig. 1, the first display area A1 may be a light transmissive display area, which may also be referred to as an under-screen camera (FDC, full Display With Camera) area. The second display area A2 may be referred to as a normal display area. For example, an orthographic projection of a sensor (e.g., hardware such as a camera) on a display substrate may be located within a first display area A1 of the display substrate. In some examples, as shown in fig. 1, the first display area A1 may be circular, and the size of the orthographic projection of the sensor on the display substrate may be smaller than or equal to the size of the first display area A1. However, the present embodiment is not limited thereto. In other examples, the first display area A1 may be rectangular, and the size of the orthographic projection of the sensor on the display substrate may be smaller than or equal to the size of the inscribed circle of the first display area A1.

In some examples, as shown in fig. 1, the first display area A1 may be located at a top middle position of the display area AA. The second display area A2 may surround the first display area A1. However, the present embodiment is not limited thereto. For example, the first display area A1 may be located at the upper left corner, the lower right corner, or the upper right corner of the display area AA. For example, the second display area A2 may surround at least one side of the first display area A1.

In some examples, as shown in fig. 1, the display area AA may be rectangular, such as rounded rectangle. The first display area A1 may be circular or elliptical. However, the present embodiment is not limited thereto. For example, the first display area A1 may have other shapes such as a rectangle, a semicircle, a pentagon, and the like.

In some examples, the display area AA may be provided with a plurality of sub-pixels. The at least one sub-pixel may include a pixel circuit and a light emitting element. The pixel circuit may be configured to drive the connected light emitting element. For example, the pixel circuit may be configured to supply a driving current to drive the light emitting element to emit light. The pixel circuit may include a plurality of transistors and at least one capacitor. For example, the pixel circuit may be a 3T1C, 4T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. Wherein, T in the circuit structure refers to a thin film transistor, C refers to a capacitor, the number in front of T represents the number of the thin film transistors in the circuit, and the number in front of C represents the number of the capacitors in the circuit.

In some examples, the light emitting element may be any of a light emitting diode (LED, light Emitting Diode), an organic light emitting diode (OLED, organic Light Emitting Diode), a quantum dot light emitting diode (QLED, quantum Dot Light Emitting Diode), a micro LED (including: mini-LED or micro-LED), or the like. For example, the light emitting element may be an OLED, and the light emitting element may emit red light, green light, blue light, white light, or the like under the driving of its corresponding pixel circuit. The light emitting color of the light emitting element may be determined as needed. In some examples, the light emitting element may include: an anode, a cathode, and an organic light emitting layer between the anode and the cathode. The anode of the light emitting element may be electrically connected to a corresponding pixel circuit. However, the present embodiment is not limited thereto.

Fig. 2 is an equivalent circuit diagram of a pixel circuit according to at least one embodiment of the utility model. The pixel circuit of the present example is described by taking an 8T1C structure as an example. In some examples, as shown in fig. 2, the pixel circuit of the present example may include eight transistors (i.e., first to eighth transistors T1 to T8) and one storage capacitor Cst. The first transistor T1 may also be referred to as a first reset transistor, the second transistor T2 may also be referred to as a threshold compensation transistor, the third transistor T3 may also be referred to as a driving transistor, the fourth transistor T4 may also be referred to as a data writing transistor, the fifth transistor T5 may also be referred to as a first light emission control transistor, the sixth transistor T6 may also be referred to as a second light emission control transistor, the seventh transistor T7 may also be referred to as a second reset transistor, and the eighth transistor T8 may also be referred to as a third reset transistor. The light emitting element EL may include an anode, a cathode, and an organic light emitting layer disposed between the anode and the cathode.

In some examples, the first transistor T1, the third transistor T3 to the eighth transistor T8 may be a first type transistor, for example, may be a P type transistor, and the second transistor T2 may be a second type transistor, for example, may be an N type transistor. However, the present embodiment is not limited thereto. For example, the plurality of transistors of the pixel circuit may be P-type transistors each, or may be N-type transistors each.

In some examples, the first type of transistor (e.g., including the first transistor T1, the third transistor T3 to the eighth transistor T8) of the pixel circuit may employ a low temperature polysilicon thin film transistor, and the second type of transistor (e.g., including the second transistor T2) of the pixel circuit may employ an oxide thin film transistor. The active layer of the low temperature polysilicon thin film transistor adopts low temperature polysilicon (LTPS, low Temperature Poly-Silicon), and the active layer of the Oxide thin film transistor adopts Oxide semiconductor (Oxide). The low-temperature polycrystalline silicon thin film transistor has the advantages of high mobility, quick charge and the like, the Oxide thin film transistor has the advantages of low leakage current and the like, the low-temperature polycrystalline silicon thin film transistor and the Oxide thin film transistor are integrated on one display substrate to form a low-temperature polycrystalline Oxide (LTPS+oxide) display substrate, the advantages of the low-temperature polycrystalline silicon thin film transistor and the Oxide thin film transistor can be utilized, low-frequency driving can be realized, power consumption can be reduced, and display quality can be improved.

In some examples, as shown in fig. 2, the pixel circuit may be electrically connected to the first scan line GL1, the second scan line GL2, the data line DL, the first power line PL1, the second power line PL2, the light emission control line EML, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the first reset control line RST1, and the second reset control line RST 2. The first power line PL1 may be configured to supply a constant first voltage signal VDD to the pixel circuit, the second power line PL2 may be configured to supply a constant second voltage signal VSS to the pixel circuit, and the first voltage signal VDD is greater than the second voltage signal VSS. The first SCAN line GL1 may be configured to supply a first SCAN signal SCAN1 to the pixel circuit. The second SCAN line GL2 may be configured to supply the second SCAN signal SCAN2 to the pixel circuit. The data line DL may be configured to supply a data signal to the pixel circuit. The emission control line EML may be configured to supply the emission control signal EM to the pixel circuit. The first RESET control line RST1 may be configured to supply a first RESET control signal RESET1 to the pixel circuit. The second RESET control line may be configured to supply a second RESET control signal RESET2 to the pixel circuit.

In some examples, as shown in fig. 2, the gate of the third transistor T3 is electrically connected to the first node N1, the first pole of the third transistor T3 is electrically connected to the second node N2, and the second pole of the third transistor T3 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the first scan line GL1, the first pole of the fourth transistor T4 is electrically connected to the data line DL, and the second pole of the fourth transistor T4 is electrically connected to the second node N2. The gate of the second transistor T2 is electrically connected to the second scan line GL2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. The gate of the fifth transistor T5 is electrically connected to the emission control line EML, the first pole of the fifth transistor T5 is electrically connected to the first power line PL1, and the second pole of the fifth transistor T5 is electrically connected to the second node N2. The gate of the sixth transistor T6 is electrically connected to the emission control line EML, the first pole of the sixth transistor T6 is electrically connected to the third node N3, and the second pole of the sixth transistor T6 is electrically connected to the fourth node N4. The gate of the first transistor T1 is electrically connected to the first reset control line RST1, the first pole of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second pole of the first transistor T1 is electrically connected to the third node N3. The gate of the seventh transistor T7 is electrically connected to the second reset control line RST2, the first pole of the seventh transistor T7 is electrically connected to the second initial signal line INIT2, and the second pole of the seventh transistor T7 is electrically connected to the fourth node N4. The gate of the eighth transistor T8 is electrically connected to the second reset control line RST2, the first pole of the eighth transistor T8 is electrically connected to the third initial signal line INIT3, and the second pole of the eighth transistor T8 is electrically connected to the second node N2. The first electrode of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode of the storage capacitor Cst is electrically connected to the first power line PL 1.

In this example, the first node N1 is a connection point of the storage capacitor Cst, the second transistor T2, and the third transistor T3, the second node N2 is a connection point of the fifth transistor T5, the fourth transistor T4, the eighth transistor T8, and the third transistor T3, the third node N3 is a connection point of the first transistor T1, the third transistor T3, the second transistor T2, and the sixth transistor T6, and the fourth node N4 is a connection point of the sixth transistor T6, the seventh transistor T7, and the light emitting element EL.

Fig. 3 is a timing diagram illustrating operation of the pixel circuit provided in fig. 2. The operation of the pixel circuit shown in fig. 2 will be described with reference to fig. 3. The first transistor T1, the third transistor T3, the eighth transistor T8, and the second transistor T2 of the pixel circuit are P-type transistors.

In some examples, as shown in fig. 2 and 3, during a frame display period, the operation of the pixel circuit may include at least: a first stage S1, a second stage S2, a third stage S3 and a fourth stage S4.

The first stage S1 is referred to as a first reset stage. The second RESET control signal RESET2 provided by the second RESET control line RST2 is a low level signal, so that the seventh transistor T7 and the eighth transistor T8 are turned on; the second SCAN signal SCAN2 provided by the second SCAN line GL2 is a high level signal, so that the second transistor T2 is turned on. The eighth transistor T8 is turned on such that the third initial signal supplied from the third initial signal line INIT3 is supplied to the second node N2. The seventh transistor T7 is turned on such that the second initialization signal supplied from the second initialization signal line INIT2 is supplied to the fourth node N4, and initializes the fourth node N4. The first SCAN signal SCAN1 provided by the first SCAN line GL1 is a high level signal, the first RESET control signal RESET1 provided by the first RESET control line RST1 is a high level signal, and the light emission control signal EM provided by the light emission control line EML is a high level signal, so that the fourth transistor T4, the first transistor T1, the fifth transistor T5, and the sixth transistor T6 are turned off. The light emitting element EL does not emit light at this stage.

The second stage S2 is referred to as a second reset stage. The first RESET control signal RESET1 provided by the first RESET control line RST1 is a low level signal, and the first transistor T1 is turned on; the second SCAN signal SCAN2 provided by the second SCAN line GL2 is a high level signal, and the second transistor T2 is turned on. The first transistor T1 and the second transistor T2 are turned on such that the first initial signal line provided by the first initial signal line INIT1 is provided to the first node N1, and the first node N1 is initialized. The second RESET control signal RESET2 provided by the second RESET control line RST2 is a high level signal, the first SCAN signal SCAN1 provided by the first SCAN line GL1 is a high level signal, and the light emission control signal EM provided by the light emission control line EML is a high level signal, so that the seventh transistor T7, the eighth transistor T8, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are turned off. The light emitting element EL does not emit light at this stage.

The third stage S3 is called a data writing stage or a threshold compensation stage. The first SCAN signal SCAN1 provided by the first SCAN line GL1 is a low level signal, and the fourth transistor T4 is turned on; the second SCAN signal SCAN2 provided by the second SCAN line GL2 is a high level signal, and the second transistor T2 is turned on. The first electrode of the storage capacitor Cst is at a low level, and the third transistor T3 is turned on. The second transistor T2, the fourth transistor T4 and the third transistor T3 are turned on, so that the data voltage Vdata output by the data line DL is provided to the first node N1 through the second node N2, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and a difference between the data voltage Vdata output by the data line DL and the threshold voltage of the third transistor T3 is charged into the storage capacitor Cst, wherein the voltage of the first electrode (i.e., the first node N1) of the storage capacitor Cst is Vdata-vth|, wherein Vdata is the data voltage output by the data line DL, and Vth is the threshold voltage of the third transistor T3. The first RESET control signal RESET1 supplied from the first RESET control line RST1 is a high level signal, the second RESET control signal RESET2 supplied from the second RESET control line RST2 is a high level signal, and the light emission control signal EM supplied from the light emission control line EML is a high level signal, so that the first transistor T1, the seventh transistor T7, the eighth transistor T8, the fifth transistor T5, and the sixth transistor T6 are turned off.

In the fourth stage S4, the emission control signal EM supplied from the emission control line EML may be switched from a high level signal to a low level signal, so that the fifth transistor T5 and the sixth transistor T6 are turned on. The second SCAN signal SCAN2 provided by the second SCAN line GL2 is a low level signal, turning off the second transistor T2. The first SCAN signal SCAN1 supplied from the first SCAN line GL1, the first RESET control signal RESET1 supplied from the first RESET control line RST1, and the second RESET control signal RESET2 supplied from the second RESET control line RST2 are high signals, and turn off the fourth transistor T4, the first transistor T1, the seventh transistor T7, and the eighth transistor T8. The first voltage signal VDD output from the first power line PL1 may supply a driving voltage to the anode of the light emitting element EL through the turned-on fifth transistor T5, third transistor T3, and sixth transistor T6, thereby driving the light emitting element EL to emit light.

In the driving process of the pixel circuit, the driving current flowing through the third transistor T3 is determined by the voltage difference between the gate and the first electrode thereof. Since the voltage of the first node N1 is Vdata- |vth|, the driving current of the third transistor T3 is:

I＝K×(Vgs-Vth) ² ＝K×[(VDD-Vdata+|Vth|)-Vth] ² ＝K×[VDD-Vdata] ² ；

where I is a driving current flowing through the third transistor T3, that is, a driving current for driving the light emitting element, K is a constant, vgs is a voltage difference between the gate and the first electrode of the third transistor T3, vth is a threshold voltage of the third transistor T3, vdata is a data voltage outputted from the data line DL, and VDD is a first voltage signal outputted from the first power supply line PL 1.

As can be seen from the above equation, the current flowing through the light emitting element is independent of the threshold voltage of the third transistor T3. Therefore, the pixel circuit of the present embodiment can better compensate the threshold voltage of the third transistor T3. Moreover, the pixel circuit provided by the embodiment can improve the display defect caused by low frequency and improve the display effect of the light-emitting element.

In some examples, as shown in fig. 1, the first display area A1 of the display substrate may be provided with a plurality of first light emitting elements 21, a plurality of second light emitting elements 22, and a plurality of first pixel circuits 11. The at least one first pixel circuit 11 is electrically connected to the at least one first light emitting element 21 and configured to drive the at least one first light emitting element 21 to emit light. The second display area A2 may be provided with a plurality of second pixel circuits 12, a plurality of third pixel circuits 13, and a plurality of third light emitting elements 23. The circuit structures of the first pixel circuit 11, the second pixel circuit 12, and the third pixel circuit 13 of the present example may be the same, for example, the 8T1C structure as described above. The at least one second pixel circuit 12 may be electrically connected to the at least one second light emitting element 22 via at least one electrically conductive connection line 15, configured to drive the at least one second light emitting element 22 to emit light. The conductive connection line 15 may extend from the first display area A1 to the second display area A2. The at least one third pixel circuit 13 is electrically connected to the at least one third light emitting element 23 and configured to drive the at least one third light emitting element 23 to emit light.

For example, the plurality of first pixel circuits 11 and the plurality of first light emitting elements 21 are electrically connected in one-to-one correspondence, and one first pixel circuit 11 may be configured to drive one first light emitting element 21. The front projection of the first light emitting element 21 on the substrate at least partially overlaps the front projection of the connected first pixel circuit 11 on the substrate. The plurality of second pixel circuits 12 and the plurality of second light emitting elements 22 are electrically connected in one-to-one correspondence, and one second pixel circuit 12 may be configured to drive one second light emitting element 22. The front projection of the second light emitting element 22 on the substrate and the front projection of the connected second pixel circuit 12 on the substrate may not overlap. The plurality of third pixel circuits 13 and the plurality of third light emitting elements 23 are electrically connected in one-to-one correspondence, and one third pixel circuit 13 may be configured to drive one third light emitting element 23. The orthographic projection of the third light emitting element 23 on the substrate at least partially overlaps the orthographic projection of the connected third pixel circuit 13 on the substrate. However, the present embodiment is not limited thereto. In other examples, the plurality of first pixel circuits may be configured to drive one first light emitting element; alternatively, one first pixel circuit may be configured to drive a plurality of first light emitting elements. As another example, the plurality of second pixel circuits may be configured to drive one second light emitting element; alternatively, one second pixel circuit may be configured to drive a plurality of second light emitting elements. As another example, the plurality of third pixel circuits may be configured to drive one third light emitting element; alternatively, one third pixel circuit may be configured to drive a plurality of third light emitting elements.

Fig. 4A and fig. 4B are partial schematic views of a first display area according to at least one embodiment of the utility model. In some examples, as shown in fig. 4A, the first display area may include: a plurality of first sub-areas a11 and a plurality of second sub-areas a12. At least one first sub-area a11 is adjacent to at least one second sub-area a12, e.g. a first sub-area a11 is adjacent to two second sub-areas a12 in the first direction X and is located in the middle of the two second sub-areas a 12; the first sub-area a11 is adjacent to two second sub-areas a12 in the second direction Y, being located in the middle of the two second sub-areas a12. The first direction X intersects the second direction Y, for example, the first direction X may be perpendicular to the second direction Y.

In some examples, as shown in fig. 4A, the first sub-area a11 may be provided with one first light emitting unit 2a, and the second sub-area a12 may be provided with one second light emitting unit 2b. The plurality of first light emitting units 2a and the plurality of second light emitting units 2b of the first display area may be arranged in an array in a plurality of rows and a plurality of columns. The one row of light emitting units may include a plurality of first light emitting units 2a and a plurality of second light emitting units 2b arranged at intervals in the first direction X, and the one column of light emitting units may include a plurality of first light emitting units 2a and a plurality of second light emitting units 2b arranged at intervals in the second direction Y. The first light emitting units 2a and the second light emitting units 2b are arranged at an interval one by one in the first direction X; in the second direction Y, the first light emitting units 2a and the second light emitting units 2b are arranged at an interval one by one. For example, one first light emitting unit 2a may be adjacent to four second light emitting units 2b. In this example, "A and B are adjacent" means that A and B are close together, and that there are no other types of objects between A and B. This example is through setting up first light emitting unit and the equal interval setting of second light emitting unit in first direction and second direction, not only can guarantee the light transmissivity of first display area, is favorable to realizing the first display area of great size moreover, still is favorable to carrying out the luminance compensation and promotes the luminance homogeneity of first display area.

In some examples, as shown in fig. 4A and 4B, adjacent first and second light emitting units 2a and 2B are disposed in alignment in the first direction X, and adjacent first and second light emitting units 2a and 2B are disposed in alignment in the second direction Y. In this example, "in the C direction, the a and B alignment arrangement" means that the line connecting the center positions of a and B in the C direction is substantially parallel to the C direction.

In some examples, as shown in fig. 4A, the first light emitting unit 2a may include at least one first light emitting element, for example, four first light emitting elements; the second light emitting unit 2b may include at least one second light emitting element, for example, four second light emitting elements. The number of first light emitting elements included in the first light emitting unit 2a and the number of second light emitting elements included in the second light emitting unit 2b may be the same. However, the present embodiment is not limited thereto. In other examples, the number of first light emitting elements included in the first light emitting unit may be greater than the number of second light emitting elements included in the second light emitting unit, or the number of first light emitting elements included in the first light emitting unit may be less than the number of second light emitting elements included in the second light emitting unit. The present example can facilitate controlling the ratio of the first light emitting element and the second light emitting element by setting the number of the first light emitting elements included in the first light emitting unit and the number of the second light emitting elements included in the second light emitting unit to be the same, thereby facilitating designing the luminance compensation between the first light emitting element and the second light emitting element.

In some examples, as shown in fig. 4A and 4B, the plurality of light emitting elements (including the plurality of first light emitting elements and the plurality of second light emitting elements) of the first display region may be arranged in an array in a plurality of rows and a plurality of columns. The one row of light emitting elements may include a plurality of first light emitting elements and a plurality of second light emitting elements arranged in the first direction X, and the one column of light emitting elements may include a plurality of first light emitting elements and a plurality of second light emitting elements arranged in the second direction Y. A column of light emitting units may include four columns of light emitting elements, and a row of light emitting units may include two rows of light emitting elements. For example, the a-th column light emitting unit may include a d-th column, a d+1th column, a d+2th column, and a d+3rd column light emitting element, and the b-th row light emitting unit may include a c-th row and a c+1th row light emitting element, wherein a, b, c, and d are integers greater than 0.

In some examples, as shown in fig. 4A and 4B, one first light emitting unit 2a may include the following four first light emitting elements: a first light emitting element 21a emitting light of a first color, a first light emitting element 21b emitting light of a second color, and two first light emitting elements 21c and 21d emitting light of a third color. The four first light emitting elements included in the first light emitting unit 2a may be disposed in two rows of light emitting elements, the first light emitting element 21a emitting the first color light and the first light emitting element 21b emitting the second color light may be disposed in the same row of light emitting elements, the two first light emitting elements 21c and 21d emitting the third color light may be disposed in the same row of light emitting elements, and the four first light emitting elements may be disposed in different columns of light emitting elements.

In some examples, as shown in fig. 4A and 4B, one second light emitting unit 2B may include the following four second light emitting elements: a second light emitting element 22a emitting light of the first color, a second light emitting element 22b emitting light of the second color, and two second light emitting elements 22c and 22d emitting light of the third color. Wherein four second light emitting elements included in one second light emitting unit 2b may be disposed in two rows of light emitting elements, the second light emitting element 22a emitting the first color light and the second light emitting element 22b emitting the second color light may be disposed in the same row of light emitting elements, two second light emitting elements 22c and 22d emitting the third color light may be disposed in the same row of light emitting elements, and four second light emitting elements may be disposed in different columns of light emitting elements. The four second light emitting elements in the second light emitting unit and the four first light emitting elements in the first light emitting unit of this example are arranged in substantially the same manner. The arrangement of the light emitting elements of the present example may be advantageous in designing the brightness compensation between the first light emitting element and the second light emitting element.

In some examples, as shown in fig. 4B, in the light emitting elements of the c-th row, two second light emitting elements 22c and 22d emitting light of the third color and two first light emitting elements 21c and 21d emitting light of the third color may be periodically arranged along the first direction X; in the c+1th row light emitting elements, the second light emitting element 22a emitting the first color light, the second light emitting element 22b emitting the second color light, the first light emitting element 21a emitting the first color light, and the first light emitting element 21b emitting the second color light may be periodically arranged along the first direction X. In the d-th row of light emitting elements, the second light emitting element 22a emitting the first color light and the first light emitting element 21b emitting the second color light may be arranged at intervals in the second direction X; in the (d+1) -th column light emitting element, the second light emitting element 22c (or 22 d) emitting the second color light and the first light emitting element 21c (or 21 d) emitting the third color light may be arranged at intervals along the second direction Y; in the (d+2) -th row of light-emitting elements, the second light-emitting element 22b emitting the second color light and the first light-emitting element 21a emitting the first color light may be arranged at intervals along the second direction Y; in the (d+3) -th column light emitting elements, the second light emitting element 22d emitting the second color light and the first light emitting element 21d emitting the third color light may be arranged at intervals along the second direction Y.

In some examples, as shown in fig. 4A, in different first light emitting units located in adjacent light emitting unit rows, the arrangement order of the first light emitting element 21a emitting the first color light and the first light emitting element 21b emitting the second color light is reversed. For example, in the first light emitting unit located in the b-th row, the first light emitting element 21a emitting the first color light and the first light emitting element 21b emitting the second color light may be sequentially arranged along the first direction X. Of the first light emitting elements located in the b+1th row, the first light emitting element 21b emitting the second color light and the first light emitting element 21a emitting the first color light may be sequentially disposed along the first direction X.

In some examples, as shown in fig. 4A, in different first light emitting units located in adjacent light emitting unit columns, the arrangement order of the first light emitting element 21a emitting the first color light and the first light emitting element 21b emitting the second color light is reversed. For example, in the first light emitting unit located in the a-th column, the first light emitting element 21b emitting the second color light and the first light emitting element 21a emitting the first color light may be sequentially arranged along the first direction X. In the first light emitting unit located in the a+1th column, the first light emitting element 21a emitting the first color light and the first light emitting element 21b emitting the second color light may be sequentially disposed along the first direction X.

In some examples, as shown in fig. 4A, in the different second light emitting units located in the adjacent light emitting unit rows, the arrangement order of the second light emitting element 22a emitting the first color light and the second light emitting element 22b emitting the second color light is reversed; the second light emitting element 22a emitting the first color light and the second light emitting element 22b emitting the second color light are arranged in reverse order in different second light emitting units located in the adjacent light emitting unit columns. The arrangement of the second light emitting element in the second light emitting unit is similar to that of the first light emitting element in the first light emitting unit, and thus, the description thereof will not be repeated.

In some examples, the first color light may be red (R), the second color light may be blue (B), and the third color light may be green (G). However, the present embodiment is not limited thereto.

In some examples, the first light emitting elements of the first light emitting units 2a of the first display area may be configured to perform brightness compensation for the second light emitting elements emitting the same color light in the adjacent second light emitting units 2 b. For example, the first light emitting element 21b emitting blue light in the first light emitting unit 2a of the b+1th row of the a-th column and the b+3th row of the a-th column may perform brightness compensation for the second light emitting element 22b emitting blue light in the second light emitting unit 2b of the b+2th row of the a-th column. The first light emitting element 21a emitting red light in the first light emitting unit 2a of the b+1th row of the a-th column and the b+3th row of the a-th column may perform brightness compensation for the second light emitting element 22a emitting red light in the second light emitting unit 2b of the b+2th row of the a-th column. The first light emitting element 21c emitting green light in the first light emitting unit 2a of the (a+1) th row, the first light emitting element 21d emitting green light in the first light emitting unit 2a of the (a+1) th row, and the first light emitting element 21c emitting green light in the first light emitting unit 2a of the (a+1) th row, the second light emitting element 22c emitting green light in the second light emitting unit 2b of the (b+1) th row may be subjected to brightness compensation. The first light-emitting element in the first light-emitting unit is utilized to carry out brightness compensation on the second light-emitting element emitting the same color light in the adjacent second light-emitting unit, so that the condition that the brightness of the second light-emitting element is dark can be effectively improved.

Fig. 5 is a schematic diagram illustrating a connection relationship between a light emitting device and a pixel circuit according to at least one embodiment of the utility model. In some examples, as shown in fig. 5, the first display area A1 may include: the second display area A2 may include a plurality of first pixel circuits (e.g., including the first pixel circuits 11a, 11b, 11c, and 11 d), a plurality of first light emitting elements, and a plurality of second light emitting elements, and the second display area A2 may include a plurality of second pixel circuits 12, a plurality of third pixel circuits 13, and a plurality of third light emitting elements (not shown). The first pixel circuit and the first light emitting element may be located in the first sub-area a11, and the second light emitting element may be located in the second sub-area a12. The light transmittance of the second sub-region a12 may be greater than that of the first sub-region a 11. For example, the first sub-region a11 may be a light-non-transmitting region, and the second sub-region a12 may include a light-non-transmitting region and a light-transmitting region. The positions of the anode and the wire of the second light emitting element in the second sub-area a12 may be non-light-transmitting areas, and the area between the anodes of the adjacent second light emitting elements where the metal wire is not disposed may be a light-transmitting area.

In some examples, as shown in fig. 5, four first pixel circuits of each first sub-region a11 may be sequentially arranged along the first direction X. For example, the first pixel circuits 11a, 11b, 11c, and 11d may be sequentially disposed along the first direction X. The four first light emitting elements of the first light emitting unit and the four first pixel circuits may be electrically connected in a one-to-one correspondence. For example, a first light emitting element (e.g., a red first light emitting element) emitting light of a first color may be electrically connected to the first pixel circuit 11a, a first light emitting element (e.g., a green first light emitting element) emitting light of a third color may be electrically connected to the first pixel circuit 11b, a first light emitting element (e.g., a blue first light emitting element) emitting light of a second color may be electrically connected to the first pixel circuit 11c, and another first light emitting element (e.g., a green first light emitting element) emitting light of a third color may be electrically connected to the first pixel circuit 11 d.

In some examples, as shown in fig. 5, the second sub-area a12 is not provided with a pixel circuit, and four second light emitting elements within the second sub-area a12 may be electrically connected to the second pixel circuit 12 within the second display area A2 through conductive connection lines 15. In the second sub-area a12, the light transmitting areas between the adjacent second light emitting elements may be connected to each other to form a continuous light transmitting area, thereby improving the light transmittance of the first display area.

In some examples, as shown in fig. 5, the plurality of second pixel circuits 12 may be spaced apart between the plurality of third pixel circuits 13 within the second display area A2. In the second display area A2, a region where the second pixel circuit 12 is disposed can be obtained by reducing the size of the third pixel circuit 13 in the first direction X. For example, the size of the third pixel circuit 13 in the first direction X may be smaller than the size of the third light emitting element in the first direction X.

In some examples, the original third pixel circuits of every f columns may be compressed along the first direction X, so that the arrangement space of one or two columns of second pixel circuits is newly increased, and the space occupied by the pixel circuits of f columns before compression and the pixel circuits of f+1 columns or f+2 columns after compression may be the same. Where f may be an integer greater than 1. In this example, f may be 4, and the arrangement space of the two columns of second pixel circuits is newly increased by compressing the four columns of third pixel circuits. However, the present embodiment is not limited thereto.

In some examples, as shown in fig. 5, the second pixel circuits 12 may be disposed in the second display area A2 on both sides (e.g., left and right sides) of the first display area A1 in the first direction X, the second pixel circuits may not be disposed in the second display area on both sides (e.g., upper and lower sides) of the first display area A1 in the second direction Y, or the inactive pixel circuits may be disposed to maintain uniformity of the components of the plurality of film layers in the second display area during the etching process. The inactive pixel circuits may be substantially identical in structure to the second pixel circuits in the row or column, except that they are not electrically connected to any light emitting element. The present embodiment is not limited thereto.

In some examples, as shown in fig. 5, the second light emitting element near the center of the first display area A1 in the first display area A1 may be electrically connected to the second pixel circuit 12 near the first display area A1 in the second display area A2, and the second light emitting element near the edge of the first display area A1 may be electrically connected to the second pixel circuit far from the first display area A1. The present embodiment is not limited to the connection relationship between the second pixel circuit and the second light emitting element.

Fig. 6 is a partial top view of a first display area according to at least one embodiment of the utility model. The first and second light emitting units of the a-th to a+2-th columns and the b-th to b+3-th rows are illustrated in fig. 6. In some examples, as shown in fig. 6, the first display region of the display substrate includes a plurality of first sub-regions and a plurality of second sub-regions spaced apart in the first direction X and the second direction Y on a plane parallel to the display substrate. The first sub-region may include one first light emitting unit (including four first light emitting elements 21a, 21b, 21c, and 21 d) and four first pixel circuits, and the second sub-region may include one second light emitting unit (including four second light emitting elements 22a, 22b, 22c, and 22 d). The second sub-area where the (a+1) th b+1 th row of the second light emitting units is located may be surrounded by the first sub-area where the (a+1) th b th row of the first light emitting units is located, the first sub-area where the (a+1) th b+1 th row of the first light emitting units is located, the first sub-area where the (a+2) th b+1 th row of the first light emitting units is located, and the first sub-area where the (a+1) th b+2 th row of the first light emitting units is located. The first sub-area where the first light emitting unit of the b-th row of the a+1 th column, the first sub-area where the first light emitting unit of the b+1-th row of the a-th column, the first sub-area where the first light emitting unit of the b+1-th row of the a+2-th column and the first sub-area where the first light emitting unit of the b+2-th row of the a+1-th column are located may be mutually communicated.

In some examples, in a direction perpendicular to the display substrate, the display substrate may include: the light-emitting device comprises a substrate, a circuit structure layer, a conductive connection layer and a light-emitting structure layer, wherein the circuit structure layer, the conductive connection layer and the light-emitting structure layer are arranged on the substrate. The light emitting structure layer may be located at a side of the circuit structure layer remote from the substrate, and the conductive connection layer may be located between the circuit structure layer and the light emitting structure layer. The circuit structure layer of the first display region may include: the plurality of first pixel circuits, the light emitting structure layer of the first display region may include: a plurality of first light emitting elements and a plurality of second light emitting elements.

In some examples, the circuit structure layer may include: a first semiconductor layer, a first conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer disposed on a substrate. A first insulating layer may be disposed between the first semiconductor layer and the first conductive layer, a second insulating layer may be disposed between the first conductive layer and the second conductive layer, a third insulating layer may be disposed between the second conductive layer and the second semiconductor layer, a fourth insulating layer may be disposed between the second semiconductor layer and the third conductive layer, a fifth insulating layer may be disposed between the third conductive layer and the fourth conductive layer, a sixth insulating layer and a seventh insulating layer may be disposed between the fourth conductive layer and the fifth conductive layer, an eighth insulating layer may be disposed between the fifth conductive layer and the sixth conductive layer, and a ninth insulating layer may be disposed on a side of the sixth conductive layer away from the substrate. In some examples, the first to sixth insulating layers may be inorganic insulating layers, and the seventh to ninth insulating layers may be organic insulating layers. The present embodiment is not limited thereto.

In some examples, the conductive connection layer may include a plurality of conductive connection lines, which may extend from the first display region to the second display region, to electrically connect the second light emitting element and the second pixel circuit.

In some examples, the light emitting structure layer may include: the organic light-emitting device comprises an anode layer, a pixel definition layer, an organic light-emitting layer and a cathode layer which are sequentially arranged on a circuit structure layer. The anode layer can be electrically connected with the pixel circuit of the circuit structure layer, the organic light-emitting layer can be connected with the anode layer, the cathode layer can be connected with the organic light-emitting layer, and the organic light-emitting layer can emit light rays with corresponding colors under the driving of the anode layer and the cathode layer.

In some examples, the packaging structure layer may include a first packaging layer, a second packaging layer and a third packaging layer stacked together, where the first packaging layer and the third packaging layer may be made of an inorganic material, the second packaging layer may be made of an organic material, and the second packaging layer may be disposed between the first packaging layer and the third packaging layer to form an inorganic material/organic material/inorganic material stacked structure, so that external moisture may be prevented from entering the light emitting structure layer. In some possible implementations, the display substrate may further include other film layers, such as a touch structure layer, a color filter layer, and the like, which are not limited herein.

The structure of the display substrate is described below by way of an example of a process of preparing the display substrate. The patterning process disclosed by the utility model comprises the steps of coating photoresist, mask exposure, development, etching, stripping photoresist and the like for metal materials, inorganic materials or transparent conductive materials, and the like for organic materials, comprising the steps of coating organic materials, mask exposure, development and the like. The deposition can be any one or more of sputtering, vapor deposition and chemical vapor deposition, the coating can be any one or more of spraying, spin coating and ink jet printing, and the etching can be any one or more of dry etching and wet etching, so that the utility model is not limited. "film" refers to a layer of film formed by depositing, coating, or other process a material on a substrate. The "film" may also be referred to as a "layer" if the "film" does not require a patterning process throughout the fabrication process. If the "thin film" requires a patterning process throughout the fabrication process, it is referred to as a "thin film" prior to the patterning process, and as a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern".

The utility model refers to the fact that A and B are arranged in the same layer, wherein A and B are formed simultaneously through the same patterning process, or the distance between the surface of one side of A and B, which is close to the substrate, and the substrate is basically the same, or the surface of one side of A and B, which is close to the substrate, is in direct contact with the same film layer. The "thickness" of a film layer is the dimension of the film layer in a direction perpendicular to the display substrate. In an exemplary embodiment of the present utility model, "the front projection of B is within the range of the front projection of a" or "the front projection of a includes the front projection of B" means that the boundary of the front projection of B falls within the boundary range of the front projection of a or the boundary of the front projection of a overlaps with the boundary of the front projection of B. The "shape of a" as used herein refers to the shape of an orthographic projection of a on a substrate.

In some examples, the preparation process of the display substrate may include the following operations. The circuit configuration layer will be described below taking two first pixel circuits in the first sub-region of the first display region as an example. The present example is described taking the first pixel circuit as an example of the aforementioned 8T1C structure. Wherein the first pixel circuit (i.e., the first pixel circuit 11 a) may include: a first transistor 31a, a second transistor 32a, a third transistor 33a, a fourth transistor 34a, a fifth transistor 35a, a sixth transistor 36a, a seventh transistor 37a, an eighth transistor 38a, and a storage capacitor; the second first pixel circuit (i.e., the first pixel circuit 11 b) may include: the first transistor 31b, the second transistor 32b, the third transistor 33b, the fourth transistor 34b, the fifth transistor 35b, the sixth transistor 36b, the seventh transistor 37b, the eighth transistor 38b, and the storage capacitor. The connection relation of the eight transistors and the storage capacitance in each first pixel circuit can be referred to an equivalent circuit diagram shown in fig. 2.

(1) A substrate is provided. In some examples, the substrate may be a rigid base or a flexible base. For example, the rigid substrate may be, but is not limited to, one or more of glass, quartz; the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, textile fibers. In some examples, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a second flexible material layer, and a second inorganic material layer stacked, the materials of the first flexible material layer and the second flexible material layer may be Polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, and the materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx, x > 0), silicon oxide (SiOy, y > 0), or the like, for improving the water-oxygen resistance of the substrate.

(2) And forming a first semiconductor layer. In some examples, a first semiconductor film is deposited on a substrate, the first semiconductor film is patterned by a patterning process, and a first semiconductor layer disposed on the substrate is formed. In some examples, the material of the first semiconductor layer may be amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, or polythiophene, etc.

Fig. 7A is a schematic view of the first display region of fig. 6 after the first semiconductor layer is formed. Fig. 7B is a schematic view of a first sub-region in fig. 7A.

In some examples, as shown in fig. 7A and 7B, the first semiconductor layer of the first display region may include at least: the active layers of the plurality of first type transistors of the plurality of first pixel circuits (e.g., including the first active layer 310a of the first transistor, the third active layer 330a of the third transistor, the fourth active layer 340a of the fourth transistor, the fifth active layer 350a of the fifth transistor, the sixth active layer 360a of the sixth transistor, the seventh active layer 370a of the seventh transistor, and the eighth active layer 380a of the eighth transistor of the first transistor, and the first active layer 310b of the first transistor, the third active layer 330b of the third transistor, the fourth active layer 340b of the fourth transistor, the fifth active layer 350b of the fifth transistor, the sixth active layer 360b of the sixth transistor, the seventh active layer 370b of the seventh transistor, and the eighth active layer 380b of the eighth transistor of the first pixel circuit 11 b).

In some examples, within the first sub-region, the first semiconductor layer patterns of the four first pixel circuits may be substantially symmetrical about the first center line O1, the first semiconductor layer patterns of the first pixel circuits 11a and 11b may be substantially symmetrical about the second center line O2, and the first semiconductor layer patterns of the first pixel circuits 11c and 11d may be substantially symmetrical about the third center line O3. The first semiconductor layer patterns in the different first sub-regions may be independent of each other.

In some examples, within the first sub-region, the first active layer, the third active layer, the fourth active layer, the fifth active layer, the sixth active layer, and the seventh active layer of the four first pixel circuits may be an integrally connected structure. The seventh active layer 370a of the first pixel circuit 11a and the seventh active layer 370b of the first pixel circuit 11b may be connected to each other. The fifth active layer 350b of the first pixel circuit 11b and the fifth active layer of the first pixel circuit 11c may be connected to each other. The seventh active layer of the first pixel circuit 11c and the seventh active layer of the first pixel circuit 11d may be connected to each other. The first active layer of each first pixel circuit may be located at one side of the third active layer in the second direction Y, and the eighth active layer may be located at one side of the third active layer in the opposite direction of the second direction Y.

In some examples, the third active layers 330a and 330b may have a substantially u-shape, the fourth active layers 340a and 340b and the fifth active layers 350a and 350b may have a substantially I-shape, and the first active layers 310a and 310b, the sixth active layers 360a and 360b, the seventh active layers 370a and 370b and the eighth active layers 380a and 380b may have a substantially L-shape. However, the present embodiment is not limited thereto.

In some examples, the active layer of each transistor may include: a first region, a second region, and a channel region between the first region and the second region. The material of the first semiconductor layer may include polysilicon, for example. The channel region may be undoped with impurities and have semiconductor characteristics. The first region and the second region may be doped regions on both sides of the channel region, and are doped with impurities, and thus have conductivity. The impurities may vary depending on the type of transistor. In some examples, the doped region of the active layer may be interpreted as a source electrode or a drain electrode of the transistor. The portion of the active layer between the transistors can be interpreted as a wiring doped with impurities, which can be used to electrically connect the transistors. The present embodiment is not limited thereto.

(2) And forming a first conductive layer. In some examples, a first insulating film and a first conductive film are sequentially deposited on a substrate forming the foregoing structure, and the first conductive film is patterned by a patterning process to form a first insulating layer and a first conductive layer disposed on the first insulating layer. In some examples, the first conductive layer may also be referred to as a first gate metal layer.

Fig. 8A is a schematic view of the first display region of fig. 6 after the first conductive layer is formed. Fig. 8B is a schematic diagram of the first conductive layer in fig. 8A. Fig. 8C is a schematic view of a first sub-region of fig. 8A.

In some examples, as shown in fig. 8A to 8C, the first conductive layer of the first display region may include at least: a plurality of first scan lines (e.g., first scan lines GL1 (i), GL1 (i+1), GL1 (i+2), GL1 (i+3)), a plurality of light emission control lines (e.g., light emission control lines EML (i), EML (i+1), EML (i+2), EML (i+3)), a plurality of first reset control lines (e.g., first reset control lines RST1 (i), RST1 (i+1), RST1 (i+2), RST1 (i+3)), a plurality of second reset control lines (e.g., second reset control lines RST2 (i), RST2 (i+1), RST2 (i+2), RST2 (i+3)), and a plurality of first electrodes (e.g., first electrodes 391a, 391 b) of storage capacitors of the first pixel circuits.

In some examples, in the first sub-region, the first scan line GL1 (i) may be located at one side of the first electrode (e.g., 391a and 391 b) of the storage capacitor of the first pixel circuit in the second direction Y, and the first reset control line RST1 (i) may be located at one side of the first scan line GL1 (i) in the second direction Y. The light emission control line EML (i) may be located at one side of the storage capacitor of the first pixel circuit in the opposite direction of the second direction Y, for example, 391a and 391b, and the second reset control line RST2 (i) may be located at one side of the light emission control line EML (i) in the opposite direction of the second direction Y.

In some examples, the first reset control line RST1 (i), the first scan line GL1 (i), the second reset control line RST2 (i), and the light emission control line EML (i) may bypass the second sub-region adjacent to the first sub-region in the first direction X by bending. For example, the first reset control line RST1 (i) and the first scan line GL1 (i) may bypass from one side of the second sub-region in the second direction Y, and the second reset control line RST2 (i) and the light emission control line EML (i) may bypass from one side of the second sub-region in the opposite direction of the second direction Y. The wiring bending of the first conductive layer is arranged to bypass the second subarea, so that the light transmittance of the second subarea is improved.

In some examples, the first reset control line RST1 (i) may be substantially shaped as a meander line extending along the first direction X. Within the first sub-region, an overlapping region of the first reset control line RST1 (i) and the first active layers of the four first pixel circuits may serve as gates of the first transistors of the four first pixel circuits (e.g., including the gates of the first transistors 31a, 31 b).

In some examples, the shape of the first scan line GL1 (i) may be substantially a folded line extending along the first direction X. Within the first sub-region, an overlapping region of the first scan line GL1 (i) and the fourth active layer of the four first pixel circuits may serve as a gate of the fourth transistor of the four first pixel circuits (e.g., including a gate of the fourth transistor 34a, a gate of the fourth transistor 34 b).

In some examples, the light emission control line EML (i) may have a substantially folded line shape extending in the first direction X. In the first sub-region, an overlapping region of the emission control line EML (i) and the fifth active layer of the four first pixel circuits may serve as a gate electrode of the fifth transistor of the four first pixel circuits (e.g., a gate electrode including the fifth transistors 35a and 35 b), and an overlapping region of the emission control line EML (i) and the sixth active layer of the four first pixel circuits may serve as a gate electrode of the sixth transistor of the four first pixel circuits (e.g., a gate electrode including the sixth transistors 36a and 36 b).

In some examples, the second reset control line RST2 (i) may be substantially shaped as a meander line extending along the first direction X. Within the first sub-region, an overlapping region of the second reset control line RST2 (i) and the seventh active layer of the four first pixel circuits may serve as a gate of the seventh transistor of the four first pixel circuits (e.g., including gates of the seventh transistors 37a and 37 b), and an overlapping region of the second reset control line RST2 (i) and the eighth active layer of the four first pixel circuits may serve as a gate of the eighth transistor of the four first pixel circuits (e.g., including gates of the eighth transistors 38a and 38 b).

In some examples, the first electrode 391a of the storage capacitance of the first pixel circuit 11a may simultaneously serve as the gate of the third transistor 33a, and the first electrode 391b of the storage capacitance of the first pixel circuit 11b may simultaneously serve as the gate of the third transistor 33 b. The front projection of the first electrodes 391a and 391b on the substrate may be substantially rectangular. The present embodiment is not limited thereto.

(3) And forming a second conductive layer. In some examples, a second insulating film and a second conductive film are sequentially deposited on a substrate on which the foregoing structure is formed, and the second conductive film is patterned by a patterning process to form a second insulating layer and a second conductive layer disposed on the second insulating layer. In some examples, the second conductive layer may also be referred to as a second gate metal layer.

Fig. 9A is a schematic view of the first display region of fig. 6 after the second conductive layer is formed. Fig. 9B is a schematic diagram of the second conductive layer in fig. 9A. Fig. 9C is a schematic view of a first sub-region in fig. 9A.

In some examples, as shown in fig. 9A to 9C, the second conductive layer of the first display region may include at least: a plurality of second scanning auxiliary lines (e.g., second scanning auxiliary lines GL2b (i), GL2b (i+1), GL2b (i+2), GL2b (i+3)), and second electrodes (e.g., second electrodes 392a, 392 b) of storage capacitors of the plurality of first pixel circuits.

In some examples, the second scanning auxiliary line GL2b (i) may have a substantially folded line shape extending in the first direction X. In the first sub-region, the second scanning auxiliary line GL2b (i) may be positioned at one side of the second electrode (e.g., 392a and 392 b) of the storage capacitor of the first pixel circuit in the second direction Y. The second scan auxiliary line GL2b (i) may bypass the second sub-region from one side of the second direction Y, and be located at one side of the first scan line GL1 (i) in the opposite direction of the second direction Y.

In some examples, in the first sub-region, the front projection of the second electrode of the storage capacitor of each first pixel circuit on the substrate may be substantially a rectangular structure having a hollowed-out area, the front projection of the hollowed-out area on the substrate may be substantially a rectangle, and the rectangle may have rounded corners or chamfers. The second electrode 392a of the storage capacitor of the first pixel circuit 11a and the second electrode 392b of the storage capacitor of the first pixel circuit 11b may be electrically connected through the first plate connecting block 392-1, the second electrode 392b of the storage capacitor of the first pixel circuit 11b and the second electrode of the storage capacitor of the first pixel circuit 11c may be electrically connected through the second plate connecting block 392-2, and the second electrode of the storage capacitor of the first pixel circuit 11c and the second electrode of the storage capacitor of the first pixel circuit 11d may be electrically connected through the other first plate connecting block 392-1. The second electrodes of the storage capacitors of the first pixel circuits 11a and 11d may be electrically connected to one second plate connecting block 392-2 on a side away from the remaining first pixel circuits. The length L1 of the first plate connecting block 392-1 in the second direction Y may be smaller than the length L2 of the second plate connecting block 392-2 in the second direction Y. The second electrode of the storage capacitor may then be electrically connected to the first power line through a second plate connection block. In this example, the second electrodes of the storage capacitors of the four first pixel circuits of the first sub-region may be integrally connected to each other, which is advantageous in ensuring uniform transmission of the first voltage signal in the first direction X.

(4) And forming a second semiconductor layer. In some examples, a third insulating film and a second semiconductor film are sequentially deposited on a substrate on which the foregoing pattern is formed, and the second semiconductor film is patterned by a patterning process to form a third insulating layer and a second semiconductor layer disposed on the third insulating layer. In some examples, the material of the second semiconductor layer may include indium gallium zinc oxide (IGZO, indium Gallium Zinc Oxide).

Fig. 10A is a schematic view of the first display region of fig. 6 after the second semiconductor layer is formed. Fig. 10B is a schematic view of the second semiconductor layer in fig. 10A. Fig. 10C is a schematic view of a first sub-region of fig. 10A.

In some examples, as shown in fig. 10A to 10C, the second semiconductor layer of the first display region may include at least: the active layers of the second type transistors of the plurality of first pixel circuits (e.g., the second active layer 320a including the second transistor 32a of the first pixel circuit 11a, the second active layer 320b of the second transistor 32b of the first pixel circuit 11b within the first sub-region).

In some examples, within the first sub-region, the second semiconductor layer patterns of the four first pixel circuits may be substantially symmetrical about the first center line O1, the second semiconductor layer patterns of the first pixel circuits 11a and 11b may be substantially symmetrical about the second center line O2, and the second semiconductor layer patterns of the first pixel circuits 11c and 11d may be substantially symmetrical about the third center line O3.

In some examples, the second active layers 320a and 320b may have a substantially L-shape. The overlapping region of the second scan auxiliary line GL2b (i) and the second active layer 320a may serve as a bottom gate of the second transistor 32a, and the overlapping region of the second scan auxiliary line GL2b (i) and the second active layer 320b may serve as a bottom gate of the second transistor 32 b.

(5) And forming a third conductive layer. In some examples, a fourth insulating film and a third conductive film are sequentially deposited on the substrate on which the foregoing pattern is formed, and the third conductive film is patterned by a patterning process to form a fourth insulating layer and a third conductive layer disposed on the fourth insulating layer. In some examples, the third conductive layer may also be referred to as a third gate metal layer.

Fig. 11A is a schematic view of the first display region of fig. 6 after the third conductive layer is formed. Fig. 11B is a schematic view of the third conductive layer in fig. 11A. Fig. 11C is a schematic view of a first sub-region in fig. 11A.

In some examples, as shown in fig. 11A to 11C, the third conductive layer of the first display region may include at least: the second scan lines (e.g., second scan lines GL2 (i), GL2 (i+1), GL2 (i+2), GL2 (i+3)), a plurality of first initial signal lines (e.g., first initial signal lines INIT1 (i), INIT1 (i+1), INIT1 (i+2), INIT1 (i+3)), a plurality of second initial signal lines (e.g., second initial signal lines INIT2 (i), INIT2 (i+1), INIT2 (i+2), INIT2 (i+3)), and a plurality of third initial signal lines (e.g., third initial signal lines INIT3 (i), INIT3 (i+1), INIT3 (i+2), INIT3 (i+3)). The shapes of the first initial signal line, the second scan line, the second initial signal line, and the third initial signal line may each be substantially a folded line extending in the first direction X.

In some examples, within the first sub-region, the first initial signal line INIT1 (i) and the second scan line GL2 (i) may be located at one side of the storage capacitor in the second direction Y, and the second initial signal line INIT2 (i) and the third initial signal line INIT3 (i) may be located at one side of the storage capacitor in the opposite direction of the second direction Y. The first initial signal line INIT1 (i) may be located at one side of the second scan line GL2 (i) along the second direction Y. The second initial signal line INIT2 (i) may be located at one side of the third initial signal line INIT3 (i) in the opposite direction of the second direction Y.

In some examples, the first initial signal line INIT1 (i), the second scan line GL2 (i), the second initial signal line INIT2 (i), and the third initial signal line INIT3 (i) may bypass a second sub-region adjacent to the first sub-region in the first direction X by bending. For example, the first and third initial signal lines INIT1 (i) and GL2 (i) may bypass from one side of the second sub-region in the second direction Y, and the second and third initial signal lines INIT2 (i) and INIT3 (i) may bypass from one side of the second sub-region in the opposite direction of the second direction Y. The wiring bending of the third conductive layer is arranged to bypass the second subarea, so that the light transmittance of the second subarea is improved.

In some examples, the front projection of the first initial signal line INIT1 (i) on the substrate may at least partially overlap with the front projection of the first reset control line RST1 (i) on the substrate, the front projection of the second scan line GL2 (i) on the substrate may at least partially overlap with the front projection of the second scan auxiliary line GL2b (i) on the substrate, the front projection of the third initial signal line INIT3 (i) on the substrate may at least partially overlap with the front projection of the light emission control line EML (i) on the substrate, and the front projection of the second initial signal line INIT2 (i) on the substrate may at least partially overlap with the front projection of the second reset control line RST2 (i) on the substrate. According to the display device, through the laminated design of the wiring of different conductive layers, excessive wiring space can be prevented from being occupied, wiring space is saved, and therefore the light transmittance of the first display area is improved.

(6) And forming a fifth insulating layer. In some examples, a fifth insulating film is deposited on the substrate on which the foregoing pattern is formed, and the fifth insulating film is patterned by a patterning process to form a fifth insulating layer.

Fig. 12 is a schematic view of a first sub-region of fig. 6 after forming a fifth insulating layer. In some examples, as shown in fig. 12, the fifth insulating layer of the first display region may be opened with a plurality of vias, for example, may include first to nineteenth vias V1 to V19, twenty-first to twenty-second vias V21 to V22, twenty-third to twenty-fourth vias V23 to V24, twenty-fifth to twenty-ninth vias V25 to V29, and thirty-first to thirty-fourth vias V31 to V34.

In some examples, the fifth insulating layer, the fourth insulating layer, the third insulating layer, the second insulating layer, and the first insulating layer within the first through nineteenth vias V1 through V19 may be removed, exposing a portion of the surface of the first semiconductor layer. The fifth insulating layer, the fourth insulating layer, the third insulating layer, and the second insulating layer in the twenty-first via V21 and the twenty-second via V22 may be removed to expose a portion of the surface of the first conductive layer. The fifth, fourth and third insulating layers within the twenty-third and twenty-fourth vias V23 and V24 may be removed to expose a portion of the surface of the second conductive layer. The fifth insulating layer in the twenty-fifth through twenty-ninth vias V25 through V29 may be removed to expose a portion of the surface of the third conductive layer. The fifth insulating layer and the fourth insulating layer in the thirty-first through thirty-fourth vias V31 through V34 may be removed to expose the surface of the second semiconductor layer.

(7) And forming a fourth conductive layer. In some examples, a fourth conductive film is deposited on the substrate on which the foregoing pattern is formed, the fourth conductive film is patterned by a patterning process, and a fourth conductive layer is formed on the fifth insulating layer. In some examples, the fourth conductive layer may also be referred to as a first source drain metal layer.

Fig. 13A is a schematic view of the first display region of fig. 6 after forming the fourth conductive layer. Fig. 13B is a schematic view of the fourth conductive layer in fig. 13A. Fig. 13C is a schematic view of a first sub-region of fig. 13A.

In some examples, as shown in fig. 13A to 13C, the fourth conductive layer of the first display region may include at least: a plurality of connection electrodes (including, for example, first to ninth connection electrodes 401 to 409, and eleventh to seventeenth connection electrodes 411 to 417).

In some examples, the first connection electrode 401 may be substantially rectangular in shape. The first connection electrode 401 may be electrically connected to the fourth active layer of the fourth transistor 34a of the first pixel circuit 11a through the third via hole V3.

In some examples, the shape of the second connection electrode 402 may be substantially a bar extending in the second direction Y. One end of the second connection electrode 402 may be electrically connected to the second active layer of the second transistor 32a of the first pixel circuit 11a through the thirty-first via hole V31, and the other end may be electrically connected to the first electrode 391a of the storage capacitor through the twenty-first via hole V21. The second connection electrode 402 is electrically connected to the gate electrode of the third transistor 33a, the first electrode 391a of the storage capacitor, and the first electrode of the second transistor 32a, and the second connection electrode 402 may serve as a first node of the first pixel circuit 11 a.

In some examples, the third connection electrode 403 may have a shape substantially in a bar shape extending in the second direction Y. One end of the third connection electrode 403 may be electrically connected to the first active layer of the first transistor 31a of the first pixel circuit 11a through the second via hole V2, and the other end may be electrically connected to the second active layer of the second transistor 32a through the thirty-second via hole V32, and may be electrically connected to the third active layer of the third transistor 33a through the sixth via hole V6.

In some examples, the fourth connection electrode 404 may have a substantially folded shape extending in the second direction Y. The fourth connection electrode 404 may be electrically connected to the fourth active layer of the fourth transistor 34a of the first pixel circuit 11a through the fourth via hole V4, and may be electrically connected to the eighth active layer of the eighth transistor 38a through the eighth via hole V8.

In some examples, the fifth connection electrode 405 may have a shape substantially in a bar shape extending in the second direction Y. The fifth connection electrode 405 may be electrically connected to the fifth active layer of the fifth transistor 35a of the first pixel circuit 11a through the fifth via hole V5, and may be electrically connected to the second electrode 392a of the storage capacitor through the twenty-third via hole V23.

In some examples, the sixth connection electrode 406 may be generally rectangular in shape. The sixth connection electrode 406 may be electrically connected to the sixth active layer of the sixth transistor 36a of the first pixel circuit 11a through the seventh via hole V7.

In some examples, the seventh connection electrode 407 may be generally L-shaped. The seventh connection electrode 407 may be electrically connected to the eighth active layer of the eighth transistor 38a of the first pixel circuit 11a through the ninth via hole V9, and may be electrically connected to the third initial signal line INIT3 (i) through the twenty-sixth via hole V26.

In some examples, the eighth connection electrode 408 may have a shape substantially in a bar shape extending in the second direction Y. The eighth connection electrode 408 may be electrically connected to the seventh active layer of the seventh transistor 37a of the first pixel circuit 11a through the tenth via hole V10, and may also be electrically connected to the second initial signal line INIT2 (i) through the twenty-seventh via hole V27.

In some examples, the shape of the ninth connection electrode 409 may be generally arcuate extending in the second direction Y. One end of the ninth connection electrode 409 may be electrically connected to the first active layer of the first transistor 31a of the first pixel circuit 11a through the first via hole V1, may be electrically connected to the first initial signal line INIT1 (i) through the twenty-fifth via hole V25, and the other end may be electrically connected to the first active layer of the first transistor 31b of the first pixel circuit 11b through the eleventh via hole V11, and may be electrically connected to the first initial signal line INIT1 (i) through the twenty-eighth via hole V28.

In some examples, the eleventh connection electrode 411 may be generally rectangular in shape. The eleventh connection electrode 411 may be electrically connected to the fourth active layer of the fourth transistor 34b of the first pixel circuit 11b through a thirteenth via hole V13.

In some examples, the twelfth connection electrode 412 may have a shape substantially in a bar shape extending in the second direction Y. One end of the twelfth connection electrode 412 may be electrically connected to the second active layer of the second transistor 32b of the first pixel circuit 11b through the thirty-third via hole V31, and the other end may be electrically connected to the first electrode 391b of the storage capacitor through the twenty-second via hole V22. The twelfth connection electrode 412 is electrically connected to the gate electrode of the third transistor 33b, the first electrode 391b of the storage capacitor, and the first electrode of the second transistor 32b, and the twelfth connection electrode 412 may serve as a first node of the first pixel circuit 11 b.

In some examples, the thirteenth connection electrode 413 may have a shape substantially in a bar shape extending in the second direction Y. One end of the thirteenth connection electrode 413 may be electrically connected to the first active layer of the first transistor 31b of the first pixel circuit 11b through the twelfth via hole V12, and the other end may be electrically connected to the second active layer of the second transistor 32b through the thirty-fourth via hole V34, and may be electrically connected to the third active layer of the third transistor 33b through the sixteenth via hole V16.

In some examples, the fourteenth connection electrode 414 may have a substantially folded shape extending in the second direction Y. The fourteenth connection electrode 414 may be electrically connected to the fourth active layer of the fourth transistor 34b of the first pixel circuit 11b through the fourteenth via hole V14, and may be electrically connected to the eighth active layer of the eighth transistor 38b through the eighteenth via hole V18.

In some examples, the fifteenth connection electrode 415 may have a shape substantially in a bar shape extending in the second direction Y. The fifteenth connection electrode 415 may be electrically connected to the fifth active layer of the fifth transistor 35b of the first pixel circuit 11b through a fifteenth via hole V15, and may be electrically connected to the second electrode 392b of the storage capacitor through a twenty-fourth via hole V24.

In some examples, the sixteenth connection electrode 416 may be generally rectangular in shape. The sixteenth connection electrode 416 may be electrically connected to the sixth active layer of the sixth transistor 36b of the first pixel circuit 11b through a seventeenth via hole V17.

In some examples, seventeenth connection electrode 417 may be generally L-shaped in shape. The seventeenth connection electrode 417 may be electrically connected to the eighth active layer of the eighth transistor 38b of the first pixel circuit 11b through a nineteenth via V19, and may also be electrically connected to the third initial signal line INIT3 (i) through a twenty ninth via V29.

In some examples, within the first sub-region, the first pixel circuits 11a and 11b may be substantially symmetrical about the second center line O2, the first pixel circuits 11c and 11d may be substantially symmetrical about the third center line O3, and the first pixel circuits 11a and 11b, and the first pixel circuits 11c and 11d may be substantially symmetrical about the first center line O1.

In some examples, the first pixel circuits within the plurality of first sub-regions arranged along the first direction X may be disposed in alignment in the first direction X, and the first pixel circuits within the plurality of first sub-regions arranged along the second direction Y may be disposed in alignment in the second direction Y. For example, four columns of first pixel circuits may be arranged in a column of first sub-regions.

(8) And forming a sixth insulating layer and a seventh insulating layer. In some examples, a sixth insulating film is deposited on the substrate on which the foregoing pattern is formed, and then a seventh insulating film is coated, and the seventh insulating film and the sixth insulating film are patterned through a patterning process, forming a sixth insulating layer and a seventh insulating layer. In some examples, the sixth insulating layer may also be referred to as a passivation layer, and the seventh insulating layer may also be referred to as a first planarization layer.

Fig. 14 is a schematic view of a first sub-region of the seventh insulating layer of fig. 6 after formation. In some examples, as shown in fig. 14, the seventh insulating layer of the first display region may be opened with a plurality of vias, for example, may include forty-first to forty-sixth vias V41 to V46. The seventh insulating layer and the sixth insulating layer in the forty-eleven via V41 to the forty-six via V46 may be removed to expose a portion of the surface of the fourth conductive layer.

(9) And forming a fifth conductive layer. In some examples, a fifth conductive film is deposited on the substrate on which the foregoing pattern is formed, the fifth conductive film is patterned by a patterning process, and a fifth conductive layer is formed on the seventh insulating layer. In some examples, the fifth conductive layer may also be referred to as a second source drain metal layer.

Fig. 15A is a schematic view of the first display region of fig. 6 after forming the fifth conductive layer. Fig. 15B is a schematic view of the fifth conductive layer in fig. 15A. Fig. 15C is a schematic view of a first sub-region of fig. 15A.

In some examples, as shown in fig. 15A to 15C, the fifth conductive layer of the first display region may include at least: the plurality of data lines (e.g., data lines DL (j-4), DL (j-3), DL (j-2), DL (j-1), DL (j), DL (j+1), DL (j+2), DL (j+3), DL (j+4), DL (j+5), DL (j+6), DL (j+7)), the plurality of first anode connection electrodes (e.g., first anode connection electrodes 422a, 422b, 422c, and 422 d), the plurality of first power connection electrodes (e.g., first power connection electrodes 423a, 423b, and 423 c), and the plurality of first shielding electrodes (e.g., first shielding electrodes 421a and 421 b).

In some examples, the plurality of data lines may be substantially in a folded line shape extending in the second direction Y. Four first sub-pixels in each first sub-region are electrically connected with four data lines in a one-to-one correspondence. The data line DL (j) may be electrically connected to the first connection electrode 401 through the forty-first via hole V41, and thus electrically connected to the fourth transistor of the first pixel circuit 11 a. The data line DL (j+1) may be electrically connected to the eleventh connection electrode 411 through the forty-fifth via hole V45, and thus electrically connected to the fourth transistor of the first pixel circuit 11 b. The data line DL (j+2) may be electrically connected to the fourth transistor of the first pixel circuit 11 c. The data line DL (j+3) may be electrically connected to the fourth transistor of the first pixel circuit 11 d.

In some examples, four data lines electrically connected to four first pixel circuits within a first sub-region may be divided into two groups to bypass a second sub-region adjacent to the first sub-region in the second direction Y. For example, the data line DL (j) connected to the first pixel circuit 11a and the data line DL (j+1) connected to the first pixel circuit 11b may bypass the adjacent second sub-region in the second direction Y from one side in the opposite direction of the first direction X, and the data line DL (j+2) connected to the first pixel circuit 11c and the data line DL (j+2) connected to the first pixel circuit 11d may bypass the adjacent second sub-region in the second direction Y from one side in the first direction X. The data line is bent to bypass the second subarea, so that occupied space of the wiring is reduced, and light transmittance of the first display area is improved.

In some examples, the first anode connection electrodes 422a, 422b, 422c, and 422d may be substantially rectangular in shape. The first anode connection electrodes 422a and 422b may be located between the data lines DL (j) and DL (j+1), and the first anode connection electrodes 422c and 422d may be located between the data lines DL (j+2) and DL (j+3).

In some examples, the first anode connection electrode 422a may be electrically connected to the sixth connection electrode 406 through the forty-third via hole V43, thereby achieving an electrical connection to the sixth transistor of the first pixel circuit 11 a. The first anode connection electrode 422b may be electrically connected to the sixteenth connection electrode 416 through the forty-sixth via hole V46, thereby achieving an electrical connection to the sixth transistor of the first pixel circuit 11 b. The first anode connection electrode 422c may be electrically connected to the sixth transistor of the first pixel circuit 11 c. The first anode connection electrode 422d may be electrically connected to the sixth transistor of the first pixel circuit 11 d.

In some examples, the first power connection electrodes 423a, 423b, and 423c may be substantially rectangular in shape. The first power connection electrode 423a may be located at one side of the data line DL (j) in the opposite direction of the first direction X, the first power connection electrode 423b may be located between the data lines DL (j+1) and DL (j+2), and the first power connection electrode 423c may be located at one side of the data line DL (j+3) in the first direction X.

In some examples, the first power connection electrode 423a may be electrically connected to the fifth connection electrode 405 through a forty-second via V42, thereby achieving an electrical connection to the fifth transistor and the storage capacitor of the first pixel circuit 11 a. The second power connection electrode 423b may be electrically connected to the fifteenth connection electrode 415 through a forty-fourth via hole V44, thereby achieving an electrical connection to the fifth transistor and the storage capacitor of the first pixel circuits 11b and 11 c. The third power connection electrode 423c may be electrically connected to the fifth transistor and the storage capacitor of the first pixel circuit 11 d.

In some examples, the first shielding electrodes 421a and 421b can be substantially n-shaped in shape. The first shielding electrode 421a may be located between the data lines DL (j) and DL (j+1), and the first shielding electrode 421b may be located between the data lines DL (j+2) and DL (j+3). The orthographic projection of the first shielding electrode 421a on the substrate may cover the orthographic projection of the second connection electrode 402 and the twelfth connection electrode 412 on the substrate, and may implement shielding of the first node of the first pixel circuit 11a and the first node of the first pixel circuit 11b, thereby shielding the influence of the remaining signals on the first nodes of the first pixel circuits 11a and 11 b. The second shielding electrode 421b can realize shielding of the first node of the first pixel circuit 11c and the first node of the first pixel circuit 11d, thereby shielding the influence of the remaining signals on the first nodes of the first pixel circuits 11c and 11 d.

(10) And forming an eighth insulating layer. In some examples, an eighth insulating film is coated on the substrate on which the foregoing pattern is formed, and the eighth insulating film is patterned by a patterning process to form an eighth insulating layer. In some examples, the eighth insulating layer may also be referred to as a second planar layer.

Fig. 16 is a schematic view of a first sub-region of fig. 6 after formation of the eighth insulating layer. In some examples, as shown in fig. 16, the eighth insulating layer of the first display region may be opened with a plurality of vias, for example, may include fifty-first through fifty-ninth vias V51 through V59. The eighth insulating layer in the fiftieth through fiftieth vias V51 through V59 may be removed, exposing a portion of the surface of the fifth conductive layer.

(11) And forming a sixth conductive layer. In some examples, a sixth conductive film is deposited on the substrate on which the foregoing pattern is formed, the sixth conductive film is patterned by a patterning process, and a sixth conductive layer is formed on the eighth insulating layer. In some examples, the sixth conductive layer may also be referred to as a third source drain metal layer.

Fig. 17A is a schematic view of the first display region of fig. 6 after forming the sixth conductive layer. Fig. 17B is a schematic view of the sixth conductive layer in fig. 17A. Fig. 17C is a schematic view of a first sub-region of fig. 17A.

In some examples, as shown in fig. 17A to 17C, the sixth conductive layer of the first display region may include at least: a plurality of second anode connection electrodes (e.g., second anode connection electrodes 431a, 431b, 431c and 431 d), a plurality of third anode connection electrodes (e.g., third anode connection electrodes 432a, 432b, 432c and 432 d), and a first power supply line 44.

In some examples, the first power line 44 of the first display area may have a mesh structure. The first power line 44 of the first sub-region may be substantially symmetrical about the first center line O1. The first power line 44 of the first sub-region may include: the first extension sections 441a and 441b, the second extension sections 442a and 442b, the third extension sections 443a, 443b and 443c, and the fourth extension sections 444a and 444b. The first extension sections 441a and 441b, the second extension sections 442a and 442b, the third extension sections 443a, 443b and 443c, and the fourth extension sections 444a and 444b may be integrally connected to each other. The second sub-region may be surrounded by first extension segments 441a and 441b in the first sub-region adjacent in the second direction Y, fourth extension segments 444a and 44b in the first sub-region adjacent in the first direction X. The first, third and fourth extension segments of the first power line 44 of different first sub-regions may be correspondingly electrically connected to form a grid-like design within the overall first display.

In some examples, the first extension sections 441a and 441b may be substantially shaped as a bar extending along the first direction X. The first extension section 441a may be positioned at one side of the first shield electrodes 421a and 421b in the opposite direction of the second direction Y, and the first extension section 441b may be positioned at one side of the first shield electrodes 421a and 421b in the second direction Y.

In some examples, the second extension sections 442a and 442b may be substantially bar-shaped extending in the second direction Y. The second extension 442a may be electrically connected to the first shielding electrode 421a through the fifty-first via V51, and the second extension 442b may be electrically connected to the first shielding electrode 421b through the fifty-second via V52. Both ends of the second extension section 442a are electrically connected with the first extension sections 441a and 441b, respectively, and both ends of the second extension section 442b may be electrically connected with the first extension sections 441a and 441b, respectively.

In some examples, the third extension sections 443a, 443b, and 443c may have a shape substantially of a bar shape extending in the second direction Y. The third extension 443a may be electrically connected to the first power connection electrode 423a through a fifty-third via V53, the third extension 443b may be electrically connected to the first power connection electrode 423b through a fifty-fourth via V54, and the third extension 443c may be electrically connected to the first power connection electrode 423c through a fifty-fifth via V55. Both ends of the third extension 443a may be electrically connected to the first extension 441a and 441b, respectively, both ends of the third extension 443b may be electrically connected to the first extension 441a and 441b, respectively, and both ends of the third extension 443c may be electrically connected to the first extension 441a and 441b, respectively. The three third extension sections and the two second extension sections may be disposed at intervals along the first direction X.

In some examples, the fourth extension 444a and 444b may be generally bar-shaped extending along the second direction Y. Both ends of the fourth extension 444a may be electrically connected to the first extension 441a and 441b, respectively, and both ends of the fourth extension 444b may be electrically connected to the first extension 441a and 441b, respectively. The fourth extension segment 444a is located at a side of the third extension segment 443a in the opposite direction to the first direction X, and the fourth extension segment 444b is located at a side of the third extension segment 443c in the first direction X.

In some examples, in the first sub-region, two first extension sections 441a and 441b, two second extension sections 442a and 442b, and three third extension sections 443a, 443b, and 443c of the first power line 44 may be connected to surround to form four receiving areas. The four accommodation areas are in one-to-one correspondence with the four first pixel circuits, and a second anode connecting electrode can be arranged in each accommodation area.

The mesh design of the first power line in the first sub-region of the present example may ensure a symmetrical design of the circuit structure layer, so that display differences (e.g., left-right viewing angle differences) at different viewing angles due to the circuit structure layer may be avoided.

In some examples, the second anode connection electrode 431a may be located at a receiving area between the third extension 443a and the second extension 442 a. The second anode connection electrode 431a may have a shape of a substantially dumbbell extending in the second direction Y. The second anode connection electrode 431a may be electrically connected to the first anode connection electrode 422a through the fifty-sixth via hole V56, thereby electrically connecting to the sixth transistor of the first pixel circuit 11 a.

In some examples, the second anode connection electrode 431b may be located at a receiving area between the third extension 443b and the second extension 442 a. The second anode connection electrode 432b may have a shape substantially of a dumbbell extending in the second direction Y. The second anode connection electrode 431b may be electrically connected to the first anode connection electrode 422b through a fifty-seventh via hole V57, thereby realizing an electrical connection to the sixth transistor of the first pixel circuit 11 b.

In some examples, the second anode connection electrode 431c may be located at a receiving area between the third extension 443b and the second extension 442 b. The second anode connection electrode 432c may have a shape substantially of a dumbbell extending in the second direction Y. The second anode connection electrode 431c may be electrically connected to the first anode connection electrode 422c through the fifty-eighth via hole V58, thereby realizing an electrical connection to the sixth transistor of the first pixel circuit 11 c.

In some examples, the second anode connection electrode 431d may be located at a receiving area between the third extension 443c and the second extension 442 b. The second anode connection electrode 432d may have a shape substantially of a dumbbell extending in one direction crossing both the first direction and the second direction. The second anode connection electrode 432d may be electrically connected to the first anode connection electrode 422d through the fifty-ninth via hole V59, and electrically connected to the sixth transistor of the first pixel circuit 11 d.

In some examples, the third anode connection electrodes 432a, 432b, 432c, and 432d are generally rectangular in shape, with rounded corners and rounded corners. The third anode connection electrodes 432a, 432b, 432c and 432d may be located in a region surrounded by the first extension sections 441a and 441b adjacent in the second direction Y, and the fourth extension sections 444a and 44b adjacent in the first direction X. The third anode connection electrodes 432a and 432b are aligned along the first direction X and adjacent to the first extension 441a within one first sub-region in the second direction Y. The third anode connection electrodes 423c and 423d may be aligned in the first direction X and adjacent to the first extension section 441b in the other first sub-region in the second direction Y.

(12) And forming a ninth insulating layer. In some examples, a ninth insulating film is coated on the substrate on which the foregoing pattern is formed, and the ninth insulating film is patterned by a patterning process to form a ninth insulating layer. In some examples, the ninth insulating layer may also be referred to as a third planarization layer.

Fig. 18 is a schematic view of the first display region of fig. 6 after forming the ninth insulating layer. In some examples, as shown in fig. 18, the ninth insulating layer of the first display region may be opened with a plurality of vias, for example, may include sixty-one via V61 to sixty-eight via V68. The ninth insulating layer in the sixty-eleventh through sixty-eighth vias V61 through V68 may be removed to expose a portion of the surface of the sixth conductive layer.

Thus, the circuit structure layer can be prepared and completed. The film structure of the circuit structure layer of the second display area is similar to that of the first display area, so that the description is omitted.

(13) And forming a conductive connection layer. In some examples, a transparent conductive film is deposited on a substrate on which the foregoing pattern is formed, and the transparent conductive film is patterned by a patterning process to form a conductive connection layer. In this example, one conductive connection layer is described as an example. However, the present embodiment is not limited thereto. In other examples, a plurality of conductive connection layers may be provided, and a planarization layer may be provided between adjacent conductive connection layers.

Fig. 19A is a schematic view of the first display region of fig. 6 after the conductive connection layer is formed. Fig. 19B is a schematic view of the conductive connection layer in fig. 19A.

In some examples, as shown in fig. 19A and 19B, the conductive connection layer of the first display region may include: a plurality of conductive connection lines (e.g., conductive connection lines 15a, 15b, 15c, and 15 d), and a plurality of fourth anode connection electrodes (e.g., fourth anode connection electrodes 461a, 461b, 461c, and 461 d).

In some examples, the fourth anode connection electrodes 461a, 461b, 461c, and 461d may be substantially rectangular in shape, and the rectangle may have rounded corners or chamfers. The fourth anode connection electrode 461a may be electrically connected to the second anode connection electrode 431a through a sixty-first via V61. The fourth anode connection electrode 461b may be electrically connected to the second anode connection electrode 431b through a sixty-second via V62. The fourth anode connection electrode 461c may be electrically connected to the second anode connection electrode 431c through a sixty-third via V63. The fourth anode connection electrode 461d may be electrically connected to the second anode connection click 431d through a sixty-fourth via V64.

In some examples, the plurality of conductive connection lines may extend at least along the first direction X, may extend from the first display region to the second display region, and may be electrically connected with the second pixel circuits of the second display region. The conductive connection line 15a may be electrically connected to the third anode connection electrode 432a through a sixty-fifth via V65, the conductive connection line 15b may be electrically connected to the third anode connection electrode 432c through a sixty-sixth via V66, the conductive connection line 15c may be electrically connected to the third anode connection electrode 432b through a sixty-seventh via V67, and the conductive connection line 15d may be electrically connected to the third anode connection electrode 432d through a sixty-eighth via V68. The orthographic projection of the electrically conductive connection line on the substrate may overlap with the orthographic projection of the at least one first pixel circuit on the substrate. For example, the front projections of the electrically conductive connection lines 15a, 15b, 15c and 15d on the substrate may each overlap with the front projections of the four first pixel circuits connected to the four first light emitting elements of the first light emitting unit of the b+1th row of the a-th column on the substrate.

In some examples, the conductive connection layer may employ a transparent conductive material, such as ITO. The electrically conductive connection lines, although passing through the second sub-region, may avoid affecting the light transmittance of the second sub-region.

(14) And forming a light emitting structure layer. In some examples, a tenth insulating film is coated on the substrate on which the foregoing pattern is formed, and the tenth insulating film is patterned by a patterning process to form a tenth insulating layer. The tenth insulating layer may be provided with a plurality of vias, and the plurality of vias may expose a portion of the surface of the conductive connection layer. Then, an anode film is deposited on the substrate with the patterns, and the anode film is patterned by a patterning process to form an anode layer.

Fig. 20 is a schematic view of the first display region of fig. 6 after the anode layer is formed. In some examples, as shown in fig. 20, the first display area may include: the anode of the first light emitting element (for example, the anode 211a of the first light emitting element 21a, the anode 211b of the first light emitting element 21b, the anode 211c of the first light emitting element 21c, the anode 211d of the first light emitting element 21 d), and the anode of the second light emitting element (for example, the anode 221a of the second light emitting element 22a, the anode 221b of the second light emitting element 22b, the anode 221c of the second light emitting element 22c, and the anode 221d of the second light emitting element 22 d) are plural.

In some examples, the anode 211a of the first light emitting element 21a emitting the first color light may be electrically connected to the fourth anode connection electrode 461a through a via hole opened in the tenth insulating layer. The anode 211b of the first light emitting element 21b emitting the second color light may be electrically connected to the fourth anode connecting electrode 461c through a via hole opened in the tenth insulating layer. The anode 211c of the first light emitting element 21c emitting the third color light may be electrically connected to the fourth anode connecting electrode 461b through a via hole opened in the tenth insulating layer. The anode 211d of the first light emitting element 21d emitting the third color light may be electrically connected to the fourth anode connecting electrode 461d through a via hole opened in the tenth insulating layer.

In some examples, the anode 221a of the second light emitting element 22a emitting the first color light may be electrically connected to the conductive connection line 15c through a via hole opened in the tenth insulating layer. The anode 221b of the second light emitting element 22b emitting the second color light may be electrically connected to the conductive connection line 15a through a via hole opened in the tenth insulating layer. The anode 221c of the second light emitting element 22c emitting the third color light may be electrically connected to the conductive connection line 15b through a via hole opened in the tenth insulating layer. The anode 221d of the second light emitting element 22d emitting the third color light may be electrically connected to the conductive connection line 15d through a via hole opened in the tenth insulating layer.

In some examples, a pixel defining film is coated on a substrate on which the foregoing pattern is formed, and a pixel defining layer is formed through masking, exposure, and development processes. The pixel defining layer may be formed with a plurality of pixel openings exposing the anode layer. An organic light emitting layer is formed in the pixel opening formed as described above, and the organic light emitting layer is connected to the anode layer. And then, depositing a cathode film, patterning the cathode film through a patterning process to form a cathode pattern, wherein the cathode is connected with the organic light-emitting layer.

In some examples, as shown in fig. 6, the pixel defining layer of the first display region may form a plurality of first pixel openings (e.g., first pixel openings 210a, 210b, 210c, and 210 d) and a plurality of second pixel openings (e.g., second pixel circuits 220a, 220b, 220c, and 220 d). The shapes of the plurality of first pixel openings and the plurality of second pixel openings may be substantially circular.

In some examples, the first pixel opening 210a may expose a portion of the surface of the anode electrode 211a, the first pixel opening 210b may expose a portion of the surface of the anode electrode 211b, the first pixel opening 210c may expose a portion of the surface of the anode electrode 211c, and the first pixel opening 210d may expose a portion of the surface of the anode electrode 211 d. The second pixel opening 220a may expose a portion of the surface of the anode electrode 221a, the second pixel opening 220b may expose a portion of the surface of the anode electrode 221b, the second pixel opening 220c may expose a portion of the surface of the anode electrode 221c, and the second pixel opening 220d may expose a portion of the surface of the anode electrode 221 d.

In some examples, the light emitting area of the first light emitting element 21b that emits the second color light may be larger than the light emitting area of the first light emitting element 21a that emits the first color light. The light emitting area of the first light emitting element 21a emitting the first color light may be larger than the light emitting area of the first light emitting element 21c or 21d emitting the third color light. The light emitting areas of the first light emitting elements 21c and 21d emitting the third color light may be the same. The light emitting area of the light emitting element of this example may refer to the area of the overlapping region of the anode electrode and the organic light emitting layer and the cathode electrode exposed by the pixel opening of the pixel defining layer.

In some examples, the light emitting area of the second light emitting element 22b that emits the second color light may be larger than the light emitting area of the second light emitting element 22a that emits the first color light. The light emitting area of the second light emitting element 22a emitting the first color light may be larger than the light emitting area of the second light emitting element 22c or 22d emitting the third color light. The light emitting areas of the second light emitting elements 22c and 22d emitting the third color light may be the same.

In some examples, the light emitting area of the first light emitting element may be larger than the light emitting area of the second light emitting element emitting the same color light. For example, the ratio of the light emitting areas of the second light emitting element and the first light emitting element emitting the same color light may be 0.4 to 0.8, for example, may be about 0.5. For example, the light emitting area of the second light emitting element 22a emitting the first color light may be about half the light emitting area of the first light emitting element 21a emitting the first color light. The light emitting area of the second light emitting element 22b emitting the second color light may be about half the light emitting area of the first light emitting element 21b emitting the second color light. The light emitting area of the second light emitting element 22c (or 22 d) emitting the third color light may be about half the light emitting area of the first light emitting element 21c (or 21 d) emitting the third color light.

By reducing the light emitting area of the second light emitting element, the situation that the brightness of the second light emitting element is dark due to low current density caused by large load of the conductive connecting wire can be reduced, and the brightness of the second light emitting element is improved.

In some examples, the pixel definition layer of the first sub-region may employ a black material to block the first pixel circuit and the trace of the first sub-region, and the pixel definition layer of the second sub-region may employ a transparent material to increase the light transmittance of the second sub-region. The present embodiment is not limited thereto.

In some examples, after the light emitting structure layer is prepared, an encapsulation layer may be formed on the cathode, and the encapsulation layer may include a stacked structure of inorganic material/organic material/inorganic material.

In some examples, the first, second, third, fourth, fifth, and sixth conductive layers may be a metal material such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or an alloy material of the above metals such as aluminum neodymium (AlNd) or molybdenum niobium (MoNb), may be a single-layer structure, or a multi-layer composite structure such as Mo/Cu/Mo, or the like. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, and the sixth insulating layer may employ any one or more of silicon oxide (SiOx, x > 0), silicon nitride (SiNy, y > 0), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The seventh insulating layer, the eighth insulating layer, and the ninth insulating layer may be made of an organic material such as polyimide, acryl, or polyethylene terephthalate. The pixel defining layer may be made of polyimide, acryl, or polyethylene terephthalate. The anode layer can be made of reflective material such as metal, and the cathode can be made of transparent conductive material. However, the present embodiment is not limited thereto.

The structure of the display substrate of the present embodiment and the process of manufacturing the same are merely an exemplary illustration. In some exemplary embodiments, the corresponding structures may be altered and patterning processes may be increased or decreased as desired. The preparation process of the embodiment can be realized by using the existing mature preparation equipment, can be well compatible with the existing preparation process, and has the advantages of simple process realization, easy implementation, high production efficiency, low production cost and high yield.

In some examples, the structures of the second pixel circuit and the third pixel circuit of the second display region may be substantially the same as the structure of the first pixel circuit, the light emitting areas of the third light emitting element and the first light emitting element emitting the same color light may be substantially the same, and the structure of the third light emitting element of the second display region may be substantially the same as the structure of the first light emitting element, so that a detailed description thereof will be omitted.

The display substrate provided by the example is internally provided with the first pixel circuit connected with the first light-emitting element of the first display area, externally provided with the second pixel circuit connected with the second light-emitting element, and reasonably arranged with the light-emitting element externally provided with the pixel circuit and the light-emitting element internally provided with the pixel circuit, so that the optimal combination of the light transmittance and the size of the first display area is realized, and the performance and the user experience of the display substrate are improved.

FIG. 21 is a diagram illustrating a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 21, the first sub-region a11 and the second sub-region a12 of the first display area may be disposed at intervals along the second direction Y. The first sub-area a11 may include a row of first light emitting units 2a (including a plurality of first light emitting units 2a sequentially arranged in the first direction X), and the second sub-area a12 may include a row of second light emitting units 2b (including a plurality of second light emitting units 2b sequentially arranged in the first direction X). In the second direction Y, the first light emitting unit 2a and the second light emitting unit 2b may be aligned and disposed at intervals.

In some examples, as shown in fig. 21, the first light emitting unit 2a may include: a first light emitting element 21a emitting light of a first color, a first light emitting element 21b emitting light of a second color, and two first light emitting elements 21c and 21d emitting light of a third color. The second light emitting unit 2b may include: a second light emitting element 22a emitting light of the first color, a second light emitting element 22b emitting light of the second color, and two second light emitting elements 22c and 22d emitting light of the third color. The arrangement of the light emitting elements in this example can be referred to the description of the foregoing embodiments, and thus will not be repeated here.

According to the display substrate, the first light-emitting units and the second light-emitting units are arranged at intervals in the second direction, so that the light-emitting elements arranged outside the pixel circuits and the light-emitting elements arranged inside the pixel circuits can be reasonably distributed, the optimal combination of the light transmittance and the size of the first display area is realized, and the performance and the user experience of the display substrate are improved. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

FIG. 22 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 22, the first sub-region a11 and the second sub-region a12 of the first display area may be disposed at intervals along the first direction X. The first sub-area a11 may include a row of first light emitting units 2a (including a plurality of first light emitting units 2a sequentially arranged in the second direction Y), and the second sub-area a12 may include a row of second light emitting units 2b (including a plurality of second light emitting units 2b sequentially arranged in the second direction Y). In the first direction X, the first light emitting unit 2a and the second light emitting unit 2b may be aligned and disposed at intervals.

According to the display substrate, the first light-emitting units and the second light-emitting units are arranged at intervals in the first direction, so that the light-emitting elements outside the pixel circuits and the light-emitting elements inside the pixel circuits can be reasonably distributed, the optimal combination of the light transmittance and the size of the first display area is realized, and the performance and the user experience of the display substrate are improved. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

FIG. 23 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 23, the first sub-region a11 and the second sub-region a12 of the first display region may be disposed at intervals in both the first direction X and the second direction Y. The first sub-area a11 may include two first light emitting units 2a sequentially arranged in the first direction X, and the second sub-area a12 may include two second light emitting units 2b sequentially arranged in the first direction X. In the first direction X, the two first light emitting units 2a and the two second light emitting units 2b may be aligned and disposed at intervals. In the second direction Y, one first light emitting unit 2a and one second light emitting unit 2b may be aligned and disposed at intervals. However, the present embodiment is not limited thereto. In other examples, two first light emitting units and one second light emitting unit may be disposed at intervals in the first direction, or two first light emitting units and one second light emitting unit may be disposed at intervals in the second direction.

The display substrate of this example sets up through setting up two first light emitting units and two second light emitting units at first direction and second direction interval, can carry out reasonable layout to the external light emitting component of pixel circuit and the built-in light emitting component of pixel circuit to realize the optimal combination of light transmissivity and the size of first display region, thereby promote display substrate's performance and user experience. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

FIG. 24 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 24, the first sub-region a11 and the second sub-region a12 of the first display region may be spaced apart along both the first direction X and the second direction Y. The first sub-area a11 may comprise a first light emitting unit 2a and the second sub-area a12 may comprise a second light emitting unit 2b. In the second direction Y, the first light emitting unit 2a and the second light emitting unit 2b may be aligned and disposed at intervals. In the first direction X, the first light emitting unit 2a and the second light emitting unit 2b may be aligned and disposed at intervals.

In some examples, as shown in fig. 24, the first light emitting unit 2a may include: a first light emitting element 21a emitting light of a first color, a first light emitting element 21b emitting light of a second color, and two first light emitting elements 21c and 21d emitting light of a third color. Wherein the first light emitting elements 21a and 21b may be arranged at intervals in the same column of light emitting elements, the first light emitting elements 21c and 21d may be arranged at intervals in the same column of light emitting elements, and the first light emitting elements 21a, 21b, 21c and 21d may be arranged in different rows of light emitting elements.

In some examples, as shown in fig. 24, the second light emitting unit 2b may include: a second light emitting element 22a emitting light of the first color, a second light emitting element 22b emitting light of the second color, and two second light emitting elements 22c and 22d emitting light of the third color. Wherein the second light emitting elements 22a and 22b may be arranged at intervals in the same column of light emitting elements, the second light emitting elements 22c and 22d may be arranged at intervals in the same column of light emitting elements, and the second light emitting elements 22a, 22b, 22c and 22d may be arranged in different rows of light emitting elements.

According to the display substrate, the first light-emitting units (comprising four first light-emitting elements longitudinally arranged in two rows) and the second light-emitting units (comprising four second light-emitting elements longitudinally arranged in two rows) are arranged at intervals in the first direction and the second direction, so that the light-emitting elements arranged outside the pixel circuit and the light-emitting elements arranged inside the pixel circuit can be reasonably distributed, the optimal combination of the light transmittance and the size of the first display region is realized, and the performance and the user experience of the display substrate are improved. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

FIG. 25 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 25, the first sub-region a11 and the second sub-region a12 of the first display area may be disposed at intervals along the first direction X. The first sub-area a11 may include a row of first light emitting units 2a (including a plurality of first light emitting units 2a sequentially arranged in the second direction Y), and the second sub-area a12 may include a row of second light emitting units 2b (including a plurality of second light emitting units 2b sequentially arranged in the second direction Y). In the first direction X, the first light emitting unit 2a and the second light emitting unit 2b may be aligned and disposed at intervals.

According to the display substrate, the first light-emitting units (comprising four first light-emitting elements longitudinally arranged in two rows) and the second light-emitting units (comprising four second light-emitting elements longitudinally arranged in two rows) are arranged at intervals in the first direction, so that the light-emitting elements externally arranged in the pixel circuit and the light-emitting elements internally arranged in the pixel circuit can be reasonably distributed, the optimal combination of the light transmittance and the size of the first display region is realized, and the performance and the user experience of the display substrate are improved. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

FIG. 26 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 26, the first sub-region a11 and the second sub-region a12 of the first display area may be disposed at intervals along the second direction Y. The first sub-area a11 may include a row of first light emitting units 2a (including a plurality of first light emitting units 2a sequentially arranged in the first direction X), and the second sub-area a12 may include a row of second light emitting units 2b (including a plurality of second light emitting units 2b sequentially arranged in the first direction X). In the second direction Y, the first light emitting unit 2a and the second light emitting unit 2b may be aligned and disposed at intervals.

According to the display substrate, the first light-emitting units (comprising four first light-emitting elements longitudinally arranged in two rows) and the second light-emitting units (comprising four second light-emitting elements longitudinally arranged in two rows) are arranged at intervals in the second direction, so that the light-emitting elements externally arranged in the pixel circuit and the light-emitting elements internally arranged in the pixel circuit can be reasonably distributed, the optimal combination of the light transmittance and the size of the first display region is realized, and the performance and the user experience of the display substrate are improved. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

FIG. 27 is a diagram illustrating a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 27, the first sub-region a11 and the second sub-region a12 of the first display region may be spaced apart along both the first direction X and the second direction Y. The first sub-area a11 may comprise a first light emitting unit 2a and the second sub-area a12 may comprise a second light emitting unit 2b. In the second direction Y, the first light emitting unit 2a and the second light emitting unit 2b may be aligned and disposed at intervals. In the first direction X, the first light emitting unit 2a and the second light emitting unit 2b may be aligned and disposed at intervals.

In some examples, as shown in fig. 27, the first light emitting unit 2a may include: a first light emitting element 21a emitting light of a first color, a first light emitting element 21b emitting light of a second color, and a first light emitting element 21c emitting light of a third color. The first light emitting elements 21a and 21b may be arranged at intervals in the same column of light emitting elements, the first light emitting element 21c may be arranged in one column of light emitting elements, and the first light emitting elements 21a, 21b, and 21c may be arranged in different rows of light emitting elements. The arrangement of the three first light emitting elements of the first light emitting unit 2a is substantially triangular.

In some examples, as shown in fig. 27, the second light emitting unit 2b may include: a second light emitting element 22a emitting light of the first color, a second light emitting element 22b emitting light of the second color, and second light emitting elements 22c and 22d emitting light of the third color. Wherein the second light emitting elements 22a and 22b may be arranged at intervals in the same column of light emitting elements, the second light emitting element 22c may be arranged in one column of light emitting elements, and the second light emitting elements 22a, 22b and 22c may be arranged in different rows of light emitting elements. The arrangement of the three first light emitting elements of the second light emitting unit 2b is substantially triangular.

The display substrate of this example is through setting up first light emitting unit (including three first light emitting component that is triangle-shaped and arrange) and second light emitting unit (including three second light emitting component that is triangle-shaped and arrange) at first direction and the equal interval setting of second direction, can carry out reasonable overall arrangement to the light emitting component that pixel circuit is external and the light emitting component that pixel circuit is built-in to realize the optimal combination of the light transmissivity and the size of first display area, thereby promote display substrate's performance and user experience. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

FIG. 28 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 28, the first sub-region a11 and the second sub-region a12 of the first display area may be disposed at intervals along the second direction Y. The first sub-area a11 may include a row of first light emitting units 2a, and the second sub-area a12 may include a row of second light emitting units 2b. In the second direction Y, the first light emitting unit 2a and the second light emitting unit 2b may be aligned and disposed at intervals.

According to the display substrate, the first light-emitting units (comprising three first light-emitting elements which are arranged in a triangle shape) and the second light-emitting units (comprising three second light-emitting elements which are arranged in a triangle shape) are arranged at intervals in the second direction, so that the light-emitting elements which are arranged outside the pixel circuit and the light-emitting elements which are arranged inside the pixel circuit can be reasonably distributed, the optimal combination of the light transmittance and the size is realized, and the performance and the user experience of the display substrate are improved. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

Fig. 29 is a diagram illustrating another example of the first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 29, the first sub-region a11 and the second sub-region a12 of the first display area may be disposed at intervals along the first direction X. The first sub-area a11 may comprise a column of first light emitting units 2a and the second sub-area a12 may comprise a column of second light emitting units 2b. In the first direction X, the first light emitting unit 2a and the second light emitting unit 2b may be aligned and disposed at intervals.

According to the display substrate, the first light-emitting units (comprising three first light-emitting elements which are arranged in a triangle shape) and the second light-emitting units (comprising three second light-emitting elements which are arranged in a triangle shape) are arranged at intervals in the first direction, so that the light-emitting elements which are arranged outside the pixel circuit and the light-emitting elements which are arranged inside the pixel circuit can be reasonably distributed, the optimal combination of the light transmittance and the size of the first display area is realized, and the performance and the user experience of the display substrate are improved. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

FIG. 30 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 30, the first sub-region a11 and the second sub-region a12 of the first display region may be spaced apart along both the first direction X and the second direction Y. The first sub-area a11 may comprise a first light emitting unit 2a and the second sub-area a12 may comprise a second light emitting unit 2b. The first and second light emitting units 2a and 2b may be aligned and spaced apart in the first and second directions X and Y.

In some examples, as shown in fig. 30, the first light emitting unit 2a may include: a first light emitting element 21a emitting light of a first color, a first light emitting element 21b emitting light of a second color, and a first light emitting element 21c emitting light of a third color. Wherein the first light emitting elements 21a, 21c and 21b may be sequentially arranged along the first direction X. The second light emitting unit 2b may include: a second light emitting element 22a emitting light of the first color, a second light emitting element 22b emitting light of the second color, and second light emitting elements 22c and 22d emitting light of the third color. Wherein the second light emitting elements 22a, 22c and 22b may be sequentially arranged along the first direction X. The light emitting elements of this example may be periodically arranged along the first direction X in accordance with the light emitting element emitting the first color light, the light emitting element emitting the third color light, and the light emitting element emitting the second color light as one repeating unit, and the light emitting elements emitting the same color light may be aligned in the second direction Y.

According to the display substrate, the first light-emitting units (comprising three first light-emitting elements distributed along the first direction) and the second light-emitting units (comprising three second light-emitting elements distributed along the first direction) are arranged at intervals in the first direction and the second direction, and the light-emitting elements with the external pixel circuits and the light-emitting elements with the internal pixel circuits can be reasonably distributed, so that the optimal combination of the light transmittance and the size of the first display region is realized, and the performance and the user experience of the display substrate are improved. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

FIG. 31 is a diagram illustrating a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 31, the first sub-region a11 and the second sub-region a12 of the first display area may be disposed at intervals along the second direction Y. The first sub-area a11 may include a row of first light emitting units 2a, and the second sub-area a12 may include a row of second light emitting units 2b. In the second direction Y, the first light emitting unit 2a and the second light emitting unit 2b may be aligned and disposed at intervals. However, the present embodiment is not limited thereto. In other examples, the first sub-region and the second sub-region may be spaced apart along the first direction X. The first sub-region may comprise a column of first light emitting units and the second sub-region may comprise a column of second light emitting units.

According to the display substrate, the first light-emitting units (comprising three first light-emitting elements distributed along the first direction) and the second light-emitting units (comprising three second light-emitting elements distributed along the first direction) are arranged at intervals in the second direction, so that the light-emitting elements outside the pixel circuit and the light-emitting elements inside the pixel circuit can be reasonably distributed, the optimal combination of the light transmittance and the size of the first display region is realized, and the performance and the user experience of the display substrate are improved. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

FIG. 32 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 32, the light emitting elements of the first display region may be periodically arranged in the first direction X, and the light emitting elements emitting the same color light may be staggered in the second direction Y in accordance with a repeating unit of the light emitting element emitting the second color light (e.g., blue light B), the light emitting element emitting the first color light (e.g., red light R), and the light emitting element emitting the third color light (e.g., green light G). Wherein the light emitting elements of the first color in the row of repeating units may be aligned in the first direction Y with the light emitting elements of the second color in the row of repeating units. Adjacent rows of light emitting elements may be arranged in such a manner that one light emitting element is shifted in the second direction Y.

In some examples, as shown in fig. 32, the first sub-region a11 and the second sub-region a12 of the first display region may be disposed at intervals in a fourth direction D4 intersecting both the first direction X and the second direction Y. The first sub-area a11 may include a plurality of first light emitting units 2a sequentially disposed along the third direction D3, and the second sub-area a12 may include a plurality of second light emitting units 2b sequentially disposed along the third direction D3, and the third direction D3 and the fourth direction D4 may intersect, for example, may be perpendicular to each other. The first light emitting unit 2a may include three first light emitting elements, and the second light emitting unit 2b may include three second light emitting elements.

According to the display substrate, the first light-emitting units (comprising three first light-emitting elements distributed along the first direction) and the second light-emitting units (comprising three second light-emitting elements distributed along the first direction) are arranged at intervals along the fourth direction intersecting with the first direction and the second direction, and the light-emitting elements arranged outside the pixel circuit and the light-emitting elements arranged inside the pixel circuit can be reasonably distributed, so that the optimal combination of the light transmittance and the size of the first display area is realized, and the performance and the user experience of the display substrate are improved. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

FIG. 33 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 33, the light emitting elements of the first display region may be periodically arranged along the first direction X, and the light emitting elements emitting the same color light may be staggered in the second direction Y, as one repeating unit, in accordance with the light emitting elements emitting the first color light (e.g., blue light R), the light emitting elements emitting the second color light (e.g., blue light B), and the light emitting elements emitting the third color light (e.g., green light G). The light emitting elements of the first color in the repeating unit of one row may be aligned with the center line of the light emitting elements of the second color and the light emitting elements of the third color in the repeating unit of the previous row in the second direction. Adjacent rows of light emitting elements may be arranged with 1.5 light emitting elements offset in the second direction Y.

In some examples, as shown in fig. 33, the first sub-region a11 and the second sub-region a12 of the first display area may be disposed at intervals in the first direction X. The first sub-area a11 may include a plurality of first light emitting units 2a sequentially disposed in the second direction Y, and adjacent first light emitting units 2a may be misaligned. The second sub-area a12 may include a plurality of second light emitting units 2b sequentially disposed in the second direction Y, and adjacent second light emitting units 2b may be misaligned. The first light emitting unit 2a may include three first light emitting elements, and the second light emitting unit 2b may include three second light emitting elements.

According to the display substrate, the first light-emitting units (comprising three first light-emitting elements distributed along the first direction) and the second light-emitting units (comprising three second light-emitting elements distributed along the first direction) are arranged at intervals in the first direction, so that the light-emitting elements outside the pixel circuit and the light-emitting elements inside the pixel circuit can be reasonably distributed, the optimal combination of the light transmittance and the size of the first display region is realized, and the performance and the user experience of the display substrate are improved. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

FIG. 34 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 34, the plurality of first light emitting units 2a and the plurality of second light emitting units 2b of the first display region may be arranged at intervals in a plurality of circumferential regions around the center of the first display region. The first sub-area a11 and the second sub-area a12 may be arranged at intervals along a direction from the center to the edge. The first sub-area a11 may include at least one first light emitting unit 2a, and the second sub-area a12 may include a plurality of second light emitting units 2b. The number of first light emitting units 2a in the different first sub-areas a11 may gradually increase and the number of first light emitting units 2b in the different second sub-areas a12 may gradually increase in a direction from the center to the edge. The first light emitting unit 2a may include three or four first light emitting elements, and the second light emitting unit 2b may include three or four second light emitting elements. The present embodiment is not limited thereto.

According to the display substrate of the example, the first light-emitting units and the second light-emitting units are arranged at intervals in the direction from the center of the circle to the edge, the light-emitting elements outside the pixel circuits and the light-emitting elements inside the pixel circuits are reasonably distributed, and the optimal combination of the light transmittance and the size of the first display area is achieved, so that the performance and the user experience of the display substrate are improved. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

FIG. 35 is a diagram illustrating another example of a first display area according to at least one embodiment of the present utility model. In some examples, as shown in fig. 35, the light emitting elements of the first display region may be arranged in the following manner: the plurality of light emitting elements emitting the third color light (e.g., green light G) are arranged in a plurality of rows and a plurality of columns, the light emitting elements emitting the first color light (e.g., red light R) and the second color light (e.g., blue light B) are arranged at intervals in the row direction and the column direction, and the light emitting elements emitting the first color light and the light emitting elements emitting the third color light are arranged in different rows and different columns.

In some examples, as shown in fig. 35, the first light emitting unit may include one first light emitting element, and the second light emitting unit may include a first second light emitting element. In the first direction X, a first light emitting unit and a second light emitting unit are arranged at intervals. Wherein, in a row of light emitting elements, the first light emitting element and the second light emitting element are arranged at intervals. For example, the first light emitting element and the second light emitting element emitting the third color light (G) are arranged at a spacing; the first light emitting element emitting the first color light (R) and the second light emitting element emitting the second color light (B) are arranged at intervals, or the first light emitting element emitting the second color light (B) and the second light emitting element emitting the first color light (R) are arranged at intervals.

In some examples, one first light emitting unit and one second light emitting unit are disposed at intervals, or two first light emitting units and two second light emitting units are disposed at intervals, in the second direction Y. Wherein, in a row of light-emitting elements, the first light-emitting element and the second light-emitting element which emit the third color light (G) are arranged at intervals one by one; in another column of light emitting elements, two first light emitting elements (including a first light emitting element emitting the first color light (R) and a first light emitting element emitting the first color light (B)) and two second light emitting elements (including a second light emitting element emitting the first color light (R) and a first light emitting element emitting the second color light (B)) are arranged at intervals.

According to the display substrate of the example, the single first light emitting element and the single second light emitting element are arranged at intervals in the first direction, and the single first light emitting element or the two first light emitting elements and the two second light emitting elements are arranged at intervals in the second direction, so that the light emitting elements arranged outside the pixel circuit and the light emitting elements arranged inside the pixel circuit are reasonably distributed, the optimal combination of the light transmittance and the size of the first display area is realized, and the performance and the user experience of the display substrate are improved. The rest of the description of the display substrate of this example can refer to the description of the foregoing embodiments, so that the description thereof will not be repeated here.

Fig. 36 is a schematic view of a display device according to at least one embodiment of the utility model. As shown in fig. 36, the present embodiment provides a display device including: a display substrate 91, and a sensor 92 located on the light-emitting side of the light-emitting structure layer away from the display substrate 91. The sensor 92 may be located on the non-display surface side of the display substrate 91. There may be overlap of the front projection of the sensor 92 on the display substrate 91 with the first display area A1.

In some examples, the display substrate 91 may be a flexible OLED display substrate, a QLED display substrate, a Micro-LED display substrate, or a Mini-LED display substrate. The display device may be a product having an image (including a still image or a moving image, wherein the moving image may be a video) display function. For example, the display device may be: any one of a display, a television, a billboard, a digital photo frame, a laser printer with a display function, a telephone, a mobile phone, a picture screen, a personal digital assistant (PDA, personal Digital Assistant), a digital camera, a portable camcorder, a viewfinder, a navigator, a vehicle, a large-area wall, an information inquiry apparatus (such as a business inquiry apparatus for an e-government, a bank, a hospital, an electric power department, etc.), a monitor, and the like. As another example, the display device may be a micro-display, and any product of VR device or AR device including the micro-display.

The drawings in the present utility model relate only to the structure to which the present utility model relates, and other structures may be referred to as general designs. Features of embodiments of the utility model, i.e. embodiments, may be combined with each other to give new embodiments without conflict. It should be noted that the above-described examples or implementations are merely exemplary and not limiting. Accordingly, the utility model is not limited to what has been particularly shown and described herein, and various modifications, substitutions, or omissions may be made in the form and details of the implementations without departing from the scope of the utility model.

Claims

1. A display substrate, comprising:

a substrate including a first display region and a second display region located at least one side of the first display region;

a plurality of first light emitting units and a plurality of second light emitting units located in the first display area; the first light emitting unit comprises at least one first light emitting element, and the second light emitting unit comprises at least one second light emitting element; the first light emitting unit is adjacent to at least one second light emitting unit;

a plurality of first pixel circuits located in the first display area; at least one first pixel circuit of the plurality of first pixel circuits is electrically connected to the at least one first light emitting element and configured to drive the at least one first light emitting element to emit light;

A plurality of second pixel circuits located in the second display area; at least one second pixel circuit of the plurality of second pixel circuits is electrically connected to the at least one second light emitting element and configured to drive the at least one second light emitting element to emit light.

2. The display substrate according to claim 1, wherein the plurality of first light emitting units and the plurality of second light emitting units are arranged at intervals in at least one of a first direction and a second direction; the first direction intersects the second direction.

3. The display substrate according to claim 2, wherein one first light emitting unit and one second light emitting unit are arranged at intervals in the first direction; in the second direction, a first light emitting unit and a second light emitting unit are disposed at intervals.

4. The display substrate according to claim 2, wherein the plurality of first light emitting units include: a plurality of columns of first light emitting units; each column of first light-emitting units comprises a plurality of first light-emitting units which are sequentially arranged along the second direction;

the plurality of second light emitting units includes: a plurality of columns of second light emitting units, each column of second light emitting units including a plurality of second light emitting units sequentially arranged along the second direction;

In the first direction, a column of first light emitting units and a column of second light emitting units are arranged at intervals.

5. The display substrate according to claim 2, wherein the plurality of first light emitting units includes a plurality of rows of first light emitting units, each row of first light emitting units including a plurality of first light emitting units disposed in sequence along the first direction;

the plurality of second light emitting units include a plurality of rows of second light emitting units, each row of second light emitting units including a plurality of second light emitting units sequentially arranged along the first direction;

in the second direction, a row of first light emitting units and a row of second light emitting units are arranged at intervals.

6. The display substrate according to claim 2, wherein first and second light emitting units adjacent in the first direction are arranged in alignment, and first and second light emitting units adjacent in the second direction are arranged in alignment;

alternatively, there is a misalignment of the first light emitting unit and the second light emitting unit adjacent in the second direction.

7. The display substrate according to claim 1, wherein a ratio of light emitting areas of the second light emitting element and the first light emitting element which emit light of the same color is less than 1.

8. The display substrate according to any one of claims 1 to 7, wherein the at least one first light emitting unit includes the same number of first light emitting elements as the at least one second light emitting unit includes the same number of second light emitting elements.

9. The display substrate of claim 8, wherein the at least one first light emitting unit comprises four first light emitting elements: a first light emitting element emitting light of a first color, a first light emitting element emitting light of a second color, and two first light emitting elements emitting light of a third color;

the at least one second light emitting unit includes the following four second light emitting elements: a second light emitting element emitting light of the first color, a second light emitting element emitting light of the second color, and two second light emitting elements emitting light of the third color.

10. The display substrate of claim 9, wherein the plurality of first light emitting elements and the plurality of second light emitting elements of the first display region are arranged in a plurality of rows and a plurality of columns;

in the at least one first light emitting unit, the two first light emitting elements emitting the third color light are arranged in the same column, the first light emitting element emitting the first color light and the first light emitting element emitting the second color light are arranged in the same column, and the four first light emitting elements of the first light emitting unit are arranged in different rows;

In the at least one second light emitting unit, the two second light emitting elements emitting the third color light are arranged in the same column, the second light emitting element emitting the first color light and the second light emitting element emitting the second color light are arranged in the same column, and the four first light emitting elements of the second light emitting unit are arranged in different rows.

11. The display substrate of claim 9, wherein the plurality of first light emitting elements and the plurality of second light emitting elements of the first display region are arranged in a plurality of rows and a plurality of columns;

in the at least one first light emitting unit, the two first light emitting elements emitting the third color light are arranged in the same row, the first light emitting element emitting the first color light and the first light emitting element emitting the second color light are arranged in the same row, and the four first light emitting elements of the first light emitting unit are arranged in different columns;

in the at least one second light emitting unit, the two second light emitting elements emitting the third color light are arranged in the same row, the first light emitting element emitting the first color light and the second light emitting element emitting the second color light are arranged in the same row, and the four second light emitting elements of the second light emitting unit are arranged in different columns.

12. The display substrate according to claim 11, wherein four first light emitting elements in the first light emitting unit are electrically connected in one-to-one correspondence with four first pixel circuits, the four first pixel circuits being sequentially arranged along a first direction, and an orthographic projection of each first pixel circuit on the substrate at least partially overlaps an orthographic projection of the connected first light emitting element on the substrate.

13. The display substrate according to claim 12, wherein the four first pixel circuits are symmetrically disposed about a first center line of the four first pixel circuits along the first direction, a first one and a second one of the four first pixel circuits are symmetrically disposed about a second center line of the two first pixel circuits along the first direction, and a third one and a fourth one of the four first pixel circuits are symmetrically disposed about a third center line of the two first pixel circuits along the first direction.

14. The display substrate according to claim 12, wherein the four first pixel circuits are electrically connected to a first power line, and the first power line is in a grid shape in the first display region.

15. The display substrate according to claim 12, wherein in a direction perpendicular to the display substrate, the display substrate comprises: a circuit structure layer on the substrate; the circuit structure layer includes the plurality of first pixel circuits and the plurality of second pixel circuits; each of the plurality of first pixel circuits and the plurality of second pixel circuits includes: at least one first type transistor, at least one second type transistor, and a storage capacitor;

the circuit structure layer includes: a first semiconductor layer, a first conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and a sixth conductive layer provided over the substrate;

the first semiconductor layer includes at least: an active layer of a first type transistor of the pixel circuit; the first conductive layer includes at least: a gate electrode of a first type transistor of the pixel circuit, a first electrode of a storage capacitor; the second conductive layer includes at least: a second electrode of the storage capacitor of the pixel circuit; the second semiconductor layer includes at least: an active layer of a second type transistor of the pixel circuit; the third conductive layer includes at least: a gate of a second type transistor of the pixel circuit; the fourth conductive layer includes at least: a plurality of connection electrodes; the fifth conductive layer includes at least: a plurality of data lines; the sixth conductive layer includes at least: a first power line.

16. The display substrate of claim 15, wherein the first display region comprises: a plurality of first sub-regions and a plurality of second sub-regions; at least one first sub-area of the plurality of first sub-areas is provided with at least one first light emitting unit and at least one second sub-area of the plurality of second sub-areas is provided with at least one second light emitting unit;

the second conductive layer further includes: a first scan line, a light emission control line, a first reset control line, and a second reset control line electrically connected to the first pixel circuit; the first scan line, the light emission control line, the first reset control line, and the second reset control line extend in a first direction;

in a second direction, the first scan line and the first reset control line bypass from one side of the second sub-region, and the light emission control line and the second reset control line bypass from the other side of the second sub-region; the second direction intersects the first direction.

17. The display substrate of claim 15, wherein the first display region comprises: a plurality of first sub-regions and a plurality of second sub-regions; at least one first sub-area of the plurality of first sub-areas is provided with at least one first light emitting unit and at least one second sub-area of the plurality of second sub-areas is provided with at least one second light emitting unit;

The third conductive layer further includes: a first initial signal line, a second initial signal line, a third initial signal line, and a second scan line electrically connected to the first pixel circuit; the first initial signal line, the second initial signal line, the third initial signal line, and the second scan line extend in a first direction;

in a second direction, the first initial signal line and the second scan line bypass from one side of the second sub-region, and the second initial signal line and the third initial signal line bypass from the other side of the second sub-region; the second direction intersects the first direction.

18. The display substrate according to claim 1, wherein a ratio of the number of the first light emitting unit to the number of the second light emitting unit in the first display area is 0.8 to 1.2.

19. The display substrate of claim 1, wherein the first display region has a light transmittance that is greater than the light transmittance of the second display region;

the display substrate further includes: a plurality of third light emitting elements and a plurality of third pixel circuits in the second display region, at least one third pixel circuit of the plurality of third pixel circuits being electrically connected to at least one third light emitting element of the plurality of third light emitting elements and configured to drive the at least one third light emitting element to emit light;

The plurality of second pixel circuits are arranged between the plurality of third pixel circuits at intervals.

20. The display substrate of claim 1, wherein a front projection of the at least one first pixel circuit at the substrate overlaps a front projection of the at least one first light emitting element at the substrate;

the at least one second pixel circuit is electrically connected with the at least one second light emitting element through at least one conductive connection line; the orthographic projection of the at least one second pixel circuit on the substrate and the orthographic projection of the at least one second light emitting element on the substrate are not overlapped.

21. The display substrate of claim 20, wherein an orthographic projection of the at least one electrically conductive connection line at the substrate overlaps an orthographic projection of the at least one first pixel circuit at the substrate.

22. A display device comprising a display substrate according to any one of claims 1 to 21, and a sensor on a non-display side of the display substrate, the front projection of the sensor on the display substrate at least partially overlapping the first display area of the display substrate.