CN220342748U

CN220342748U - Display device

Info

Publication number: CN220342748U
Application number: CN202321177660.8U
Authority: CN
Inventors: 全裕珍; 李元世; 张东玄
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-05-16
Filing date: 2023-05-16
Publication date: 2024-01-12
Anticipated expiration: 2033-05-16
Also published as: CN117082900A

Abstract

The present utility model provides a display device, comprising: a substrate including a first region, a second region surrounding at least a portion of the first region, and a third region surrounding at least a portion of the second region; a first display element disposed on the first region and including a first pixel electrode; a second display element disposed on the first region and including a second pixel electrode; a third display element disposed on the first region and including a third pixel electrode; and a first connection wiring electrically connecting the first display elements to each other, the first connection wiring overlapping at least a portion of the second pixel electrode and the third pixel electrode.

Description

Display device

Technical Field

The present utility model relates to a display device.

Background

Recently, the use of display devices is being diversified. In addition, since the thickness of the display device is reduced and the weight thereof is reduced, the range of use thereof is tending to be wide.

Various functions are added to the display device in combination with or in association with the expansion of the area occupied by the region in which the image is displayed in the display device. As a solution for adding various functions, research into a display device having an area for displaying an image while performing various functions is continuing.

In order to perform the functions, the region for displaying the image and for various functions needs to have high transmittance for light, sound, and the like. On the other hand, as long as high transmittance is maintained in the region for various functions while displaying an image, resolution can be reduced.

Disclosure of Invention

An object of an embodiment of the present utility model is to provide a display device capable of having high transmittance.

According to one aspect of the present utility model, there is provided a display device including: a substrate including a first region, a second region surrounding at least a portion of the first region, and a third region surrounding at least a portion of the second region; a first display element disposed on the first region and including a first pixel electrode; a second display element disposed on the first region and including a second pixel electrode; a third display element disposed on the first region and including a third pixel electrode; and a first connection wiring electrically connecting the first display elements to each other, the first connection wiring overlapping at least a portion of the second pixel electrode and the third pixel electrode.

In this embodiment, the method may further include: and a second connection wiring that electrically connects the second display elements to each other, the second connection wiring overlapping at least a part of the first pixel electrode and the third pixel electrode.

In this embodiment, the method may further include: and a third connection wiring that electrically connects the third display elements to each other, the third connection wiring overlapping at least a part of the first pixel electrode and the second pixel electrode.

In this embodiment, the first connection wiring, the second connection wiring, and the third connection wiring may have an overall shape of an x-shape in a plane.

In this embodiment, at least a part of the first connection wirings and at least a part of the second connection wirings may be parallel to each other.

In this embodiment, at least a part of the first connection wirings and at least a part of the third connection wirings may be parallel to each other.

In this embodiment, the first connection wiring, the second connection wiring, and the third connection wiring may be arranged in the same layer.

In this embodiment, the first connection wiring may electrically connect the two first display elements, and the second connection wiring may electrically connect the two second display elements.

In the present embodiment, the third connection wiring may electrically connect the two third display elements.

In the present embodiment, the third connection wiring may electrically connect four of the third display elements.

In this embodiment, the method may further include: a fourth display element disposed on the second region and including a fourth pixel electrode; a fifth display element disposed on the second region and including a fifth pixel electrode; a sixth display element disposed on the second region and including a sixth pixel electrode; and a fourth connection wiring so that the fourth display elements are electrically connected to each other.

In this embodiment, the fourth connection wiring may be disposed in the same layer as the fourth pixel electrode.

In this embodiment, the method may further include: a first pixel circuit disposed on the second region; and a second pixel circuit disposed on the second region.

In this embodiment, the first pixel electrode may be electrically connected to the first pixel circuit.

In this embodiment, the fourth pixel electrode may overlap at least a portion of the second pixel circuit.

In this embodiment, the method may further include: a first thin film transistor including a first semiconductor layer including a silicon semiconductor and a first gate electrode overlapping at least a portion of the first semiconductor layer, the first semiconductor layer being disposed on the substrate; a first interlayer insulating layer covering the first thin film transistor; a second thin film transistor including a second semiconductor layer including an oxide semiconductor and a second gate electrode overlapping at least a portion of the second semiconductor layer, the second semiconductor layer being disposed over the first interlayer insulating layer; and a second interlayer insulating layer covering the second thin film transistor.

In this embodiment, the first connection wiring may include an oxide semiconductor.

In this embodiment, the first connection wiring may be disposed in the same layer as the second semiconductor layer.

In this embodiment, the first region may include a transmissive region.

In this embodiment, the method may further include: and a component overlapping the first region.

According to another aspect of the present utility model, there is provided a display device including: a substrate including a first region, a second region surrounding at least a portion of the first region, and a third region surrounding at least a portion of the second region; a first display element disposed on the first region and including a first pixel electrode; a first connection wiring that electrically connects at least a part of the first display elements; a second display element disposed on the second region and including a second pixel electrode; and a second connection wiring that electrically connects at least a part of the second display element, at least a part of the first connection wiring overlapping at least a part of the first pixel electrode.

In this embodiment, the second pixel electrode may overlap at least a portion of the second pixel circuit.

In this embodiment, the second connection wiring may be disposed in the same layer as the second pixel electrode.

In this embodiment, the first region may include a transmissive region.

Other aspects, features, and advantages in addition to the foregoing will become apparent from the following detailed description, the claims, and the accompanying drawings for practicing the utility model.

According to an embodiment of the present utility model as described above, a display device with improved transmittance can be provided by overlapping the connection wiring with the pixel electrode. Of course, the scope of the present utility model is not limited to this effect.

Drawings

Fig. 1 and 2 are perspective views schematically showing a display device according to an embodiment of the present utility model.

Fig. 3 is a sectional view schematically showing a display device according to an embodiment of the present utility model.

Fig. 4 is an equivalent circuit diagram schematically showing a pixel circuit electrically connected to a display element according to an embodiment of the present utility model.

Fig. 5 is an equivalent circuit diagram schematically showing a pixel circuit electrically connected to a display element according to an embodiment of the present utility model.

Fig. 6 and 7 are plan views schematically showing a display panel according to an embodiment of the present utility model.

Fig. 8 is a sectional view schematically showing a display device according to an embodiment of the present utility model.

Fig. 9 is a sectional view schematically showing a display device according to an embodiment of the present utility model.

Fig. 10 is a plan view schematically showing a display panel according to an embodiment of the present utility model.

Fig. 11 is a sectional view schematically showing a display panel according to an embodiment of the present utility model.

Fig. 12 is a plan view schematically showing a display panel according to an embodiment of the present utility model.

Fig. 13 is a sectional view schematically showing a display panel according to an embodiment of the present utility model.

Fig. 14 is a plan view schematically showing a display panel according to an embodiment of the present utility model.

(description of the reference numerals)

OLED: organic light-emitting element

CWL: connection wiring

1: display device

10: display panel

211: pixel electrode

Detailed Description

While the utility model is susceptible to various modifications and alternative embodiments, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. The effects, features and methods of achieving them will become apparent with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present utility model is not limited to the embodiments disclosed hereinafter, but may be embodied in various forms.

In the following examples, the terms first, second, etc. are not used in a limiting sense and are used for distinguishing one constituent element from another.

In the following embodiments, singular expressions include plural expressions, as long as they are not explicitly indicated as different in the text.

In the following embodiments, the terms including or having the features and constituent elements described in the specification are used to indicate the existence of the features and constituent elements, and do not exclude additional possibilities of one or more other features and constituent elements in advance.

In the following embodiments, when a portion such as a film, a region, or a constituent element is described as being located on or over another portion, it includes not only a case where it is located directly on another portion but also a case where another film, a region, a constituent element, or the like is interposed therebetween.

In the drawings, the size of constituent elements may be enlarged or reduced for convenience of explanation. For example, for convenience of explanation, the dimensions and thickness of each of the structures shown in the drawings are arbitrarily shown, and therefore, the present utility model is not necessarily limited to the case shown in the drawings.

In this specification, "a and/or B" means A, B or a and B. In this specification, "at least one of a and B" means A, B or a and B.

In the following embodiments, the meaning of the wiring "extending in the first direction or the second direction" includes not only a case of extending in a straight line shape but also a case of extending in a zigzag or curved line in the first direction or the second direction.

In the following embodiments, when expressed as "on plane", it means a case when viewing the object portion from above, and when expressed as "on section", it means a case when viewing a section taken perpendicularly to the object portion on the side. In the following examples, when expressed as "overlapping", it includes "in-plane" and "in-section" overlapping.

Hereinafter, embodiments of the present utility model will be described in detail with reference to the accompanying drawings, and the same or corresponding constituent elements will be given the same reference numerals when described with reference to the drawings.

Referring to fig. 1 and 2, the display device 1 may display an image. The display device 1 may include pixels PX. The pixel PX may be defined as a region where the display element emits light. Each of the pixels PX may mean a sub-pixel (sub-pixel), and includes a display element such as an organic light emitting diode OLED. For example, the pixel PX may emit red, green, blue, or white light.

In an embodiment, the pixels PX may be provided in plural in the display device 1. The plurality of pixels PX may emit light, respectively, and an image may be displayed. In an embodiment, the pixels PX may include a first pixel PX1, a second pixel PX2 (refer to fig. 10), a third pixel PX3 (refer to fig. 10), a fourth pixel PX4, a fifth pixel PX5 (refer to fig. 12), a sixth pixel PX6 (refer to fig. 12), and a seventh pixel PX7. The first pixel PX1, the second pixel PX2, the third pixel PX3, the fourth pixel PX4, the fifth pixel PX5, the sixth pixel PX6, and the seventh pixel PX7 may be provided in plural.

The display device 1 may include a first area AR1, a second area AR2, a third area AR3, and a fourth area AR4. The pixels PX may be disposed in the first region AR1, the second region AR2, and the third region AR 3. Accordingly, the first, second, and third areas AR1, AR2, and AR3 may be display areas in which images are displayed. At this time, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be disposed in the first area AR1, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 may be disposed in the second area AR2, and the seventh pixel PX7 may be disposed in the third area AR 3. The pixels PX may not be disposed in the fourth area AR4. Therefore, the fourth area AR4 may be a non-display area in which an image is not displayed.

At least one of the first area AR1 and the second area AR2 may be an area where the pixels PX are arranged while overlapping the components. For example, the first area AR1 may be an area where the pixels PX are arranged while overlapping the components. Alternatively, the first area AR1 and the second area AR2 may be areas where the pixels PX are arranged while being entirely overlapped with the components. In an embodiment, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may be disposed in the first area AR 1. The fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 may be disposed in the second area AR 2. Accordingly, the first area AR1 and the second area AR2 may be areas where images are displayed, and may be areas under which components are disposed.

At least one of the first region AR1 and the second region AR2 may overlap the component. Therefore, the first region AR1 and/or the second region AR2 in the display device 1 are required to have high light transmittance or high acoustic transmittance. For example, the light transmittance of the display device 1 in the first region AR1 and/or the second region AR2 may be about 10% or more, 25% or more, 40% or more, 50% or more, 85% or more, or 90% or more. In an embodiment, the light transmittance of the display device 1 in the first region AR1 may be higher than the light transmittance of the display device 1 in the second region AR 2.

In an embodiment, the first area AR1 may be provided with at least one in the display device 1. For example, the display device 1 may include one first area AR1 or a plurality of first areas AR1.

In an embodiment, the second region AR2 may surround at least a portion of the first region AR1. For example, as shown in fig. 1, the second region AR2 may entirely surround the first region AR1. Alternatively, as shown in fig. 2, the second area AR2 may be disposed at one side of the first area AR1. For example, the first region AR1 and the second region AR2 may be arranged side by side along a first direction (e.g., x-direction or-x-direction). Alternatively, the first region AR1 and the second region AR2 may be arranged side by side along the second direction (e.g., the y-direction or the-y-direction). The second region AR2 may be disposed at both sides of the first region AR1.

In an embodiment, the first area AR1 and the second area AR2 may be disposed on an upper side of the display device 1. However, the present utility model is not limited thereto. The first area AR1 and the second area AR2 may be disposed below, right side, or left side of the display device 1.

In one embodiment, at least one of the first region AR1 and the second region AR2 may be provided in various shapes such as a polygon such as a circle, an ellipse, a quadrangle, etc., a star shape, or a diamond shape on a plane (for example, xy plane). Fig. 1 shows that the first region AR1 and the second region AR2 are each provided in a circular shape, and fig. 2 shows that the first region AR1 and the second region AR2 are each provided in a quadrangular shape.

The third region AR3 may surround at least a portion of the first region AR1 and/or the second region AR2. In an embodiment, as shown in fig. 1, the second area AR2 entirely surrounds the first area AR1, and the third area AR3 entirely surrounds the second area AR2. Alternatively, as shown in fig. 2, the third region AR3 may entirely surround the first region AR1 and/or the second region AR2. The resolution of the display device 1 in the third area AR3 may be higher than or equal to the resolution of the display device 1 in the first area AR 1.

The fourth region AR4 may surround at least a portion of the third region AR3. In an embodiment, the fourth area AR4 may entirely surround the third area AR3. As described above, the pixels PX may not be arranged in the fourth area AR 4.

Fig. 3 is a cross-sectional view summarizing a display device according to an embodiment of the present utility model. Specifically, Fig. 3 is a cross-sectional view of the display device 1 shown in Fig. 1 along the A-A' line.

Referring to fig. 3, display device 1 may include a display panel 10, a panel protection member PB, an assembly 20, and a cover window CW. The display panel 10 may include a substrate 100, an insulating layer IL, a pixel circuit PC, a display element DPE, an encapsulation layer ENL, a touch sensor layer TSL, and an optical function layer OFL.

The display device 1 may include a first area AR1, a second area AR2, and a third area AR3. The display device 1 includes a substrate 100, and as another expression, the substrate 100 may include a first region AR1, a second region AR2, and a third region AR3. That is, the first region AR1, the second region AR2, and the third region AR3 may be defined in the substrate 100. Hereinafter, the case where the substrate 100 includes the first region AR1, the second region AR2, and the third region AR3 will be mainly described in detail.

The substrate 100 may be made of an insulating material such as glass, quartz, or a polymer resin. The substrate 100 may be a rigid (rib) substrate or a flexible (flexible) substrate that is flexible, foldable, rollable, or the like.

The insulating layer IL and the pixel circuit PC may be disposed on the substrate 100. The insulating layer IL may insulate the constituent elements of the display panel 10. The insulating layer IL may include at least one of an organic substance and an inorganic substance.

The pixel circuit PC may be electrically connected to the display element DPE to drive the display element DPE. The pixel circuit PC may be disposed in the insulating layer IL. In an embodiment, the pixel circuit PC may include a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3. The first pixel circuit PC1 and the second pixel circuit PC2 may be disposed in the second area AR 2. The third pixel circuit PC3 may be disposed in the third area AR3. In an embodiment, the pixel circuit PC may not be disposed in the first area AR 1. Accordingly, the transmittance (e.g., light transmittance) of the display panel 10 in the first region AR1 may be relatively higher than the transmittance of the display panel 10 in the second region AR2 and the third region AR3.

The display element DPE may be disposed on the insulating layer IL. In an embodiment, the display element DPE may be an organic light emitting element (organic light emitting diode) including an organic light emitting layer. Alternatively, the display element DPE may be a light emitting element LED. The dimensions of the light emitting element LED may be micro (micro) dimensions or nano (nano) dimensions. For example, the light emitting element may be a micro (micro) light emitting element. Alternatively, the light emitting element may be a nanorod (nanod) light emitting element. The nanorod light emitting element may include gallium nitride (GaN). In an embodiment, a color conversion layer may be disposed on the nanorod light emitting element, and the color conversion layer may include quantum dots. Alternatively, the display element DPE may be a quantum dot light emitting element (Quantum dot Light Emitting Diode) including a quantum dot light emitting layer. Alternatively, the display element DPE may be an inorganic light emitting element including an inorganic semiconductor. Hereinafter, the display element DPE is mainly described in detail as an organic light emitting element.

The display panel 10 may include a plurality of display requirements DPE. The plurality of display elements DPE may be arranged in the first region AR1, the second region AR2, and the third region AR 3. In an embodiment, the display element DPE may emit light to implement the pixel PX. For example, the display element DPE arranged in the first area AR1 may emit light to realize the first pixel PX1. The display element DPE arranged in the second area AR2 may emit light to realize the fourth pixel PX4. The display element DPE arranged in the third area AR3 may emit light to realize the seventh pixel PX7. Accordingly, the display device 1 can display images in the first area AR1, the second area AR2, and the third area AR 3.

In an embodiment, a plurality of display elements DPE may be electrically connected to one first pixel circuit PC1. Therefore, the plurality of display elements DPE can be made to emit light by the first pixel circuits PC1 having a small number, and the transmittance of the first region AR1 can be improved.

The first pixel circuit PC1 disposed in the second region AR2 and the display element DPE disposed in the first region AR1 can be electrically connected through the intermediate connection wiring MWL. The intermediate connection wiring MWL may extend from the second area AR2 to the first area AR1. Therefore, the intermediate connection wiring MWL may be arranged in the first area AR1 and the second area AR 2.

The intermediate connection wiring MWL may include a transparent conductive substance. For example, the intermediate connection wiring MWL may be provided with a transparent conductive oxide (Transparent Conducting Oxide, TCO). The intermediate connection wiring MWL may include Indium Tin Oxide (ITO), indium zinc oxide (IZO; indium zinc oxide), zinc oxide (ZnO; zinc oxide), indium oxide (In ₂ O ₃ : an indium oxide), an indium gallium oxide (IGO; indium gallium oxide) or aluminum zinc oxide (AZO; aluminum zinc oxide) and the like.

In an embodiment, a plurality of display elements DPE may be electrically connected to one second pixel circuit PC2. Therefore, the plurality of display elements DPE can be made to emit light with the small number of second pixel circuits PC2.

The encapsulation layer ENL may cover the display element DPE. In an embodiment, the encapsulation layer ENL may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. The at least one inorganic encapsulation layer may comprise aluminum oxide (Al ₂ O ₃ ) Titanium oxide (TiO) ₂ ) Tantalum oxide (Ta) ₂ O ₅ ) Zinc oxide (ZnO), silicon oxide (SiO) ₂ ) Silicon nitride (SiN) _X ) And at least one inorganic substance selected from silicon oxynitride (SiON). The at least one organic encapsulation layer may comprise a substance of the polymer (polymer) series. Examples of the material of the polymer series include acrylic resins, epoxy resins, polyimide resins, and polyethylene resins. In an embodiment, the at least one organic encapsulation layer may include an acrylate (acrylate).

In an embodiment, the encapsulation layer ENL may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330, which are sequentially stacked. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may prevent or reduce penetration of foreign substances such as moisture into the organic encapsulation layer 320 and/or the display element DPE.

Alternatively, the encapsulation layer ENL may be configured such that the substrate 100 and the transparent member, that is, the sealing substrate are bonded by the sealing member to seal the internal space between the substrate 100 and the sealing substrate. In this case, the internal space may be provided with a moisture absorbent, a filler, or the like. The sealing member may be a sealant. Alternatively, the sealing member may include a substance cured by laser. For example, the sealing member may be a glass frit (fret). Specifically, the sealing member may include an organic sealing agent, i.e., a urethane-based resin, an epoxy-based resin, an acrylic resin, or an inorganic sealing agent, i.e., silicon (silicone), or the like. As the urethane resin, for example, urethane acrylate and the like can be used. As the acrylic resin, for example, butyl acrylate, ethylhexyl acrylate, or the like can be used. On the other hand, the sealing member may include a substance by thermal curing.

The touch sensor layer TSL may obtain coordinate information according to an external input (e.g., a touch event). The touch sensor layer may include a touch electrode and a touch wiring connected to the touch electrode. The touch sensor layer TSL may sense an external input by a self-capacitance manner or a mutual capacitance manner.

The touch sensor layer TSL may be disposed on the encapsulation layer ENL. In an embodiment, the touch sensor layer TSL may be disposed directly above the encapsulation layer ENL. In this case, an adhesive layer such as an optically transparent adhesive may not be disposed between the touch sensor layer TSL and the encapsulation layer ENL. Alternatively, the touch sensor layer TSL may be bonded to the encapsulation layer ENL through an adhesive layer such as an optically transparent adhesive after being separately formed on the touch substrate.

The optical function layer OFL may include an antireflection layer. The anti-reflection layer may reduce the reflectivity of light (external light) incident from the outside toward the display device 1. In an embodiment, the optical functional layer OFL may be a polarizing film. Alternatively, the optical function layer OFL may be provided by a filter plate including a black matrix and a color filter.

The cover window CW may be disposed on the display panel 10. The cover window CW may protect the display panel 10. The cover window CW may include at least one of glass, sapphire, and plastic. For example, the cover window CW may be Ultra-Thin tempered Glass (UTG), transparent polyimide (Colorless Polyimide, CPI).

The panel protection member PB may be disposed under the substrate 100. The panel protection member PB may support and protect the substrate 100. In an embodiment, an opening pb_op overlapping the first region AR1 may be defined in the panel protection part PB. As another expression, the panel protection member PB may be provided with an opening pb_op overlapping the first region AR 1. In an embodiment, the opening pb_op of the panel protection member PB may also overlap the first area AR1 and the second area AR 2. The panel protection part PB may include polyethylene terephthalate (polyethylene terephthalate) or polyimide (polyimide).

The assembly 20 may be disposed under the display panel 10. In one embodiment, the assembly 20 may be located on the opposite side of the cover window CW from the display panel 10. In an embodiment, the component 20 may overlap the first region AR 1. Alternatively, the assembly 20 may overlap the first region AR1 and the second region AR 2.

The module 20 may include an imaging element as a camera using infrared rays, visible rays, or the like. Alternatively, the component 20 may be a solar cell, a flash, an illuminance sensor, a proximity sensor, an iris sensor. Alternatively, the assembly 20 may have a function of receiving sound. In order to minimize the functional limitation of such a component 20, the pixel circuit PC may not be arranged in the first area AR1 where the component 20 is arranged below. That is, the first pixel circuit PC1 that drives the display element DPE arranged in the first area AR1 may be arranged in the second area AR2 instead of being arranged in the first area AR 1. Accordingly, the transmittance (e.g., light transmittance) of the display panel 10 in the first region AR1 may be higher than the transmittance (e.g., light transmittance) of the display panel 10 in the second region AR 2.

Fig. 4 is an equivalent circuit diagram schematically showing a pixel circuit PC electrically connected to a display element DPE according to an embodiment of the present utility model.

Referring to fig. 4, the pixel circuit PC may include a driving thin film transistor T1, a switching thin film transistor T2, and a storage capacitor Cst.

The switching thin film transistor T2 may be electrically connected to the scan line SL and the data line DL, respectively, and transmit a data signal (or a data voltage) input from the data line DL to the driving thin film transistor T1 based on a scan signal (or a switching voltage) input from the scan line SL. The storage capacitor Cst may be electrically connected to the switching thin film transistor T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between the voltage received from the switching thin film transistor T2 and the driving voltage ELVDD supplied to the driving voltage line PL.

The driving thin film transistor T1 may be electrically connected to the driving voltage line PL and the storage capacitor Cst, respectively, and control a driving current flowing from the driving voltage line PL through the display element DPE in correspondence with a voltage value stored in the storage capacitor Cst. The display element DPE can emit light with a predetermined luminance by the driving current. The counter electrode of the display element DPE may receive the common voltage ELVSS.

Fig. 4 shows that the pixel circuit PC includes two thin film transistors and one storage capacitor, but the pixel circuit PC may include three or more thin film transistors.

Fig. 5 is an equivalent circuit diagram schematically showing a pixel circuit PC electrically connected to a display element DPE according to an embodiment of the present utility model.

Referring to fig. 5, the pixel circuit PC may include a plurality of thin film transistors T1 to T7 and a storage capacitor Cst. The plurality of thin film transistors T1 to T7 and the storage capacitor Cst may be connected to the signal lines SL1, SL2, SLp, SLn, EL, DL, the first initialization voltage line VL1, the second initialization voltage line VL2, and the driving voltage line PL. At least any one of such wirings, for example, the driving voltage line PL may be shared in adjacent pixels.

The plurality of thin film transistors T1 to T7 may include a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initialization thin film transistor T4, a operation control thin film transistor T5, a light emission control thin film transistor T6, and a second initialization thin film transistor T7.

The display element DPE may include a first electrode (e.g., a pixel electrode) that receives a driving current by connecting the light emission control thin film transistor T6 to the driving thin film transistor T1 as a medium, and a second electrode (e.g., a counter electrode) that receives the common voltage ELVSS. The display element DPE may generate light of a luminance corresponding to the driving current.

Some of the plurality of thin film transistors T1 to T7 may be NMOS (n-channel MOSFET), and the others may be PMOS (p-channel MOSFET). For example, the compensation thin film transistor T3 and the first initialization thin film transistor T4 among the plurality of thin film transistors T1 to T7 may be NMOS (n-channel MOSFET; n-channel MOSFET) and the rest may be PMOS (p-channel MOSFET; p-channel MOSFET). Alternatively, the compensation thin film transistor T3, the first initializing thin film transistor T4, and the second initializing thin film transistor T7 among the plurality of thin film transistors T1 to T7 may be NMOS, and the rest may be PMOS. Alternatively, the plurality of thin film transistors T1 to T7 may be NMOS or PMOS. The plurality of thin film transistors T1 to T7 may include amorphous silicon or polycrystalline silicon. The thin film transistor of the NMOS may include an oxide semiconductor as needed. Hereinafter, for convenience, a case where the compensation thin film transistor T3 and the first initialization thin film transistor T4 are NMOS (n-channel MOSFET) including an oxide semiconductor and the rest are PMOS (p-channel MOSFET) will be described.

The signal lines may include a first scan line SL1 transmitting the first scan signal Sn to the switching thin film transistor T2, a second scan line SL2 transmitting the second scan signal Sn' to the compensation thin film transistor T3, a previous scan line SLp transmitting the previous scan signal Sn-1 to the first initialization thin film transistor T4, a next scan line SLn transmitting the next scan signal sn+1 to the second initialization thin film transistor T7, a light emission control line EL transmitting the light emission control signal En to the operation control thin film transistor T5 and the light emission control thin film transistor T6, and a data line DL crossing the first scan line SL1 and transmitting the data signal Dm.

The driving voltage line PL may transmit the driving voltage ELVDD to the driving thin film transistor T1, the first initializing voltage line VL1 may transmit the first initializing voltage Vint1 initializing the driving thin film transistor T1, and the second initializing voltage line VL2 may transmit the second initializing voltage Vint2 initializing the first electrode of the display element DPE.

The driving gate electrode of the driving thin film transistor T1 may be connected to the storage capacitor Cst through the second node N2, any one of the source region and the drain region of the driving thin film transistor T1 may be connected to the driving voltage line PL through the operation control thin film transistor T5 through the first node N1, and the other one of the source region and the drain region of the driving thin film transistor T1 may be electrically connected to the first electrode of the display element DPE through the light emission control thin film transistor T6 through the third node N3. The driving thin film transistor T1 may supply a driving current to the display element DPE according to the switching operation of the switching thin film transistor T2 receiving the data signal Dm. That is, the driving thin film transistor T1 may control an amount of current flowing from the first node N1 electrically connected to the driving voltage line PL to the display element DPE in correspondence with the voltage applied to the second node N2, which is changed according to the data signal Dm.

The switching gate electrode of the switching thin film transistor T2 may be connected to the first scan line SL1 transmitting the first scan signal Sn, any one of the source region and the drain region of the switching thin film transistor T2 may be connected to the data line DL, and the other one of the source region and the drain region of the switching thin film transistor T2 may be connected to the driving voltage line PL via the operation control thin film transistor T5 while being connected to the driving thin film transistor T1 through the first node N1. The switching thin film transistor T2 may transmit the data signal Dm from the data line DL to the first node N1 in correspondence with a voltage applied to the first scan line SL 1. That is, a switching operation of the switching thin film transistor T2 to transmit the data signal Dm transmitted to the data line DL to the driving thin film transistor T1 through the first node N1 according to the first scan signal Sn received through the first scan line SL1 is turned on may be performed.

The compensation gate electrode of the compensation thin film transistor T3 is connected to the second scan line SL2. Any one of the source region and the drain region of the compensation thin film transistor T3 may be connected to the first electrode of the display element DPE through the light emission control thin film transistor T6 via the third node N3. The other of the source and drain regions of the compensation thin film transistor T3 may be connected to the lower electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving thin film transistor T1 through the second node N2. Such a compensation thin film transistor T3 may diode-connect the driving thin film transistor T1 according to the second scan signal Sn' received through the second scan line SL2.

The first initializing gate electrode of the first initializing thin film transistor T4 may be connected to the previous scan line SLp. Any one of the source region and the drain region of the first initialization thin film transistor T4 may be connected to the first initialization voltage line VL1. The other of the source region and the drain region of the first initializing thin film transistor T4 may be connected to the lower electrode CE1 of the storage capacitor Cst, the driving gate electrode of the driving thin film transistor T1, and the like through the second node N2. The first initialization thin film transistor T4 may apply the first initialization voltage Vint1 from the first initialization voltage line VL1 to the second node N2 corresponding to the voltage applied to the previous scan line SLp. That is, an initialization operation in which the first initialization thin film transistor T4 transmits the first initialization voltage Vint1 to the driving gate electrode of the driving thin film transistor T1 according to the previous scan signal Sn-1 received through the previous scan line SLp to initialize the voltage of the driving gate electrode of the driving thin film transistor T1 may be performed.

The operation control gate electrode of the operation control thin film transistor T5 may be connected to the light emission control line EL, and either one of the source region and the drain region of the operation control thin film transistor T5 may be connected to the driving voltage line PL and the other may be connected to the driving thin film transistor T1 and the switching thin film transistor T2 through the first node N1.

The light emission control gate electrode of the light emission control thin film transistor T6 may be connected to the light emission control line EL, any one of the source region and the drain region of the light emission control thin film transistor T6 may be connected to the driving thin film transistor T1 and the compensation thin film transistor T3 through the third node N3, and the other one of the source region and the drain region of the light emission control thin film transistor T6 may be electrically connected to the first electrode of the display element DPE.

The operation control thin film transistor T5 and the light emission control thin film transistor T6 may be simultaneously turned on according to the light emission control signal En received through the light emission control line EL, so that the driving voltage ELVDD is transmitted to the display element DPE such that the driving current flows to the display element DPE.

The second initializing gate electrode of the second initializing thin film transistor T7 may be connected to the subsequent scan line SLn, any one of the source region and the drain region of the second initializing thin film transistor T7 may be connected to the first electrode of the display element DPE, and the other of the source region and the drain region of the second initializing thin film transistor T7 may be connected to the second initializing voltage line VL2, thereby receiving the second initializing voltage Vint2. The second initializing thin film transistor T7 may initialize the first electrode of the display element DPE according to the subsequent scan signal sn+1 received through the subsequent scan line SLn. The latter scan line SLn may be the same as the first scan line SL 1. At this time, the corresponding scanning lines may function as the first scanning line SL1 or may function as the subsequent scanning line SLn by transmitting the same electric signal with a time difference therebetween.

The second initializing transistor T7 may be connected to the subsequent scan line SLn. However, the present utility model is not limited thereto, and the second initialization transistor T7 may be connected to the light emission control line EL to be driven according to the light emission control signal En.

The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2. The lower electrode CE1 of the storage capacitor Cst may be connected to the driving gate electrode of the driving thin film transistor T1 through the second node N2, and the upper electrode CE2 of the storage capacitor Cst may be connected to the driving voltage line PL. The storage capacitor Cst may store therein an electric charge corresponding to a difference between the driving gate electrode voltage and the driving voltage ELVDD of the driving thin film transistor T1.

As described above, part of the plurality of thin film transistors T1 to T7 may include an oxide semiconductor. For example, the compensation thin film transistor T3 and the first initialization thin film transistor T4 may include an oxide semiconductor.

In order to have high reliability in the case of polysilicon, it is possible to accurately control the flow of current as intended. Therefore, in the case of the driving thin film transistor T1 which directly affects the luminance of the display device, the semiconductor layer made of polysilicon having high reliability is made to be included, and based on this, a high-resolution display device can be realized. On the other hand, the oxide semiconductor has high carrier mobility (high carrier mobility) and low leakage current, and therefore, even if the driving time is long, the voltage drop is not large. That is, in the case of an oxide semiconductor, even in the case of low-frequency driving, the color change of an image according to voltage drop is not large, and therefore, low-frequency driving is possible. Accordingly, a display device in which power consumption is reduced while preventing occurrence of leakage current can be realized by making the compensation thin film transistor T3 and the first initialization thin film transistor T4 include an oxide semiconductor.

On the other hand, such an oxide semiconductor is sensitive to light, and therefore, the amount of current or the like may vary due to light from the outside. Therefore, a metal layer may be provided under the oxide semiconductor to absorb or reflect light from the outside. Each of the compensation thin film transistor T3 and the first initialization thin film transistor T4 including an oxide semiconductor may be configured with a gate electrode in each of above and below the oxide semiconductor layer. That is, the metal layer located under the oxide semiconductor may overlap with the oxide semiconductor when viewed in the z-axis direction.

Fig. 6 and 7 are plan views schematically showing a display panel 10 according to an embodiment of the present utility model. In fig. 6 and 7, the same reference numerals as those in fig. 1 and 2 denote the same components, respectively, and thus, duplicate descriptions are omitted.

Referring to fig. 6 and 7, the display panel 10 may include a substrate 100, a pixel circuit PC, and pixels PX. In an embodiment, the substrate 100 may include a first area AR1, a second area AR2, a third area AR3, and a fourth area AR4. As shown in fig. 6, the second region AR2 may entirely surround the first region AR1. Alternatively, as shown in fig. 7, the second area AR2 may be disposed at one side of the first area AR1. The third region AR3 may surround at least a portion of the first region AR1 and/or the second region AR 2. The fourth region AR4 may surround at least a portion of the third region AR 3.

The pixel circuit PC may include a first pixel circuit PC1, a second pixel circuit PC2, and a third pixel circuit PC3. In an embodiment, the first pixel circuit PC1 and the second pixel circuit PC2 may be disposed in the second area AR 2. The third pixel circuit PC3 may be disposed in the third area AR 3. That is, the pixel circuit PC may not be arranged in the first area AR 1.

The pixel PX may be implemented as a display element such as an organic light emitting element. The pixels PX may include a first pixel PX1, a second pixel PX2 (see fig. 10), a third pixel PX3 (see fig. 10), a fourth pixel PX4, a fifth pixel PX5 (see fig. 12), a sixth pixel PX6 (see fig. 12), and a seventh pixel PX7. The first pixel PX1, the second pixel PX2, and the third pixel PX3 may be disposed in the first area AR 1. The first pixel PX1 may be electrically connected with the first pixel circuit PC 1. In an embodiment, the first pixel PX1 may be electrically connected with the first pixel circuit PC1 through the intermediate connection wiring MWL. In an embodiment, any one of the plurality of first pixels PX1 may be electrically connected with another one of the plurality of first pixels PX 1. At this time, any one of the plurality of first pixels PX1 and another one of the plurality of first pixels PX1 may be connected to one first pixel circuit PC1 to emit light identically.

The fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 may be disposed in the second area AR 2. The fourth pixel PX4 may be electrically connected to the second pixel circuit PC 2. The fourth pixel PX4 may overlap the second pixel circuit PC 2. In an embodiment, any one of the plurality of fourth pixels PX4 may be electrically connected with another one of the plurality of fourth pixels PX 4. At this time, any one of the plurality of fourth pixels PX4 and another one of the plurality of fourth pixels PX4 may be connected to the one second pixel circuit PC2 to emit light in the same manner.

The seventh pixel PX7 may be disposed in the third area AR 3. The seventh pixel PX7 may be electrically connected to the third pixel circuit PC3. The seventh pixel PX7 may overlap the third pixel circuit PC3.

In an embodiment, the resolution of the display panel 10 in the first area AR1 and/or the second area AR2 may be less than or equal to the resolution of the display panel in the third area AR 3. For example, the resolution of the display panel 10 in the first area AR1 and/or the second area AR2 may be about 1/2, 3/8, 1/3, 1/4, 2/9, 1/8, 1/9, or 1/16, etc. of the resolution of the display panel 10 in the third area AR 3.

The fourth area AR4 may be a non-display area in which the pixels PX are not arranged. In the fourth region AR4, a first scan driving circuit SDRV1, a second scan driving circuit SDRV2, a PAD, a driving voltage supply line 11, and a common voltage supply line 13 may be configured.

Either one of the first scan driving circuit SDRV1 and the second scan driving circuit SDRV2 may apply a scan signal to the pixel circuit PC through the scan line SL. In an embodiment, the first scan driving circuit SDRV1 and the second scan driving circuit SDRV2 may be located at opposite sides across the third area AR 3. In an embodiment, any one of the plurality of pixels PX may receive a scan signal from the first scan driving circuit SDRV1, and another one of the plurality of pixels PX may receive a scan signal from the second scan driving circuit SDRV 2.

The PAD may be disposed in a PAD area PADA that is one side of the fourth area AR 4. The PAD may be exposed without being covered by an insulating layer and connected to the display circuit board 40. The display driving section 41 may be disposed in the display circuit board 40.

The display driving section 41 may generate signals to be transmitted to the first scan driving circuit SDRV1 and the second scan driving circuit SDRV 2. The display driving unit 41 may generate a data signal, and the generated data signal may be transmitted to the pixel circuit PC through the fan-out wiring FW and the data line DL connected to the fan-out wiring FW.

The display driving part 41 may supply the driving voltage ELVDD (refer to fig. 4) to the driving voltage supply line 11, and may supply the common voltage ELVSS (refer to fig. 4) to the common voltage supply line 13. The driving voltage ELVDD may be supplied to the pixel circuit PC through the driving voltage line PL connected to the driving voltage supply line 11, and the common voltage ELVSS may be supplied to the counter electrode of the display element connected to the common voltage supply line 13.

Fig. 8 is a sectional view schematically showing a display device according to an embodiment of the present utility model. Specifically, fig. 8 is a sectional view schematically showing the display panel 10 of fig. 6 along a line B-B'.

Referring to fig. 8, the display panel 10 may include a substrate 100, an insulating layer IL, a third pixel circuit PC3, a seventh organic light emitting element OLED7 as a display element, and a pixel defining film 215.

The substrate 100 may include glass or a polymer resin such as polyethersulfone, polyarylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyimide, polycarbonate, cellulose triacetate, cellulose acetate propionate, and the like. In one embodiment, the substrate 100 may be a multi-layered structure including a base layer including the above-described polymer resin and a barrier layer (not shown). The substrate 100 including the polymer resin may have flexible, crimpable, bendable characteristics.

The insulating layer IL may be disposed on the substrate 100. The insulating layer IL may include an inorganic insulating layer IIL and an organic insulating layer OIL. In an embodiment, the inorganic insulating layer IIL may include a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, a first interlayer insulating layer 115, a third gate insulating layer 117, and a second interlayer insulating layer 119.

The third pixel circuit PC3 may be disposed in the third area AR 3. The third pixel circuit PC3 may include a first thin film transistor TFT1, a second thin film transistor TFT2, and a storage capacitor Cst. The first thin film transistor TFT1 may include a first semiconductor layer Act1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. The second thin film transistor TFT2 may include a second semiconductor layer Act2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2. The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2.

The buffer layer 111 may be disposed on the substrate 100. The buffer layer 111 may include silicon nitride (SiN _X ) Silicon oxynitride (SiON) and silicon oxide (SiO) ₂ ) Such inorganic insulators may be single or multi-layered including the inorganic insulators described above.

The first semiconductor layer Act1 may include a silicon semiconductor. The first semiconductor layer Act1 may include polysilicon. Alternatively, the first semiconductor layer Act1 may include amorphous (amorphlus) silicon. Alternatively, the first semiconductor layer Act1 may include an oxide semiconductor or include an organic semiconductor or the like. The first semiconductor layer Act1 may include a channel region, and a drain region and a source region respectively disposed at both sides of the channel region.

The first gate electrode GE1 may overlap the first semiconductor layer Act 1. Specifically, the first gate electrode GE1 may overlap with the channel region of the first semiconductor layer Act 1. The first gate electrode GE1 may include a low-resistance metal substance. The first gate electrode GE1 may include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed of multiple layers or a single layer including the above-described materials.

A first gate insulating layer 112 may be disposed between the first semiconductor layer Act1 and the first gate electrode GE1. Accordingly, the first semiconductor layer Act1 may be insulated from the first gate electrode GE1. The first gate insulating layer 112 may include silicon oxide (SiO ₂ ) Silicon nitride (SiN) _X ) Silicon oxynitride (SiON), aluminum oxide (Al) ₂ O ₃ ) Titanium oxide (TiO) ₂ ) Tantalum oxide (Ta) ₂ O ₅ ) Hafnium oxide (HfO) ₂ ) And/or zinc oxide (ZnO) _x ) Inorganic insulating material such as zinc oxide (ZnO) _x ) May be ZnO and/or ZnO ₂ 。

The second gate insulating layer 113 may cover the first gate electrode GE1. The second gate insulating layer 113 may be disposed on the first gate electrode GE1. The second gate insulating layer 113 may include silicon oxide (SiO ₂ ) Silicon nitride (SiN) _X ) Silicon oxynitride (SiON), aluminum oxide (Al) ₂ O ₃ ) Titanium oxide (TiO) ₂ ) Tantalum oxide (Ta) ₂ O ₅ ) Hafnium oxide (HfO) ₂ ) And/or zinc oxide (ZnO) _x ) Inorganic insulating material such as zinc oxide (ZnO) _x ) May be ZnO and/or ZnO ₂ . The upper electrode CE2 may be disposed on the second gate insulating layer 113. The upper electrode CE2 may overlap the first gate electrode GE1 disposed therebelow. At this time, the upper electrode CE2 and the first gate electrode GE1 may overlap with each other through the second gate insulating layer 113 to form the storage capacitor Cst. That is, the first gate electrode GE1 of the first thin film transistor TFT1 may serve as a lower portion of the storage capacitor CstThe electrode CE1 functions. As described above, the storage capacitor Cst and the first thin film transistor TFT1 may be formed to overlap. However, the present utility model is not limited thereto. For example, the storage capacitor Cst may be formed not to overlap the first thin film transistor TFT 1.

The upper electrode CE2 may include aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and/or copper (Cu), and may be a single layer or a multilayer of the above.

The first interlayer insulating layer 115 may cover the upper electrode CE2. The first interlayer insulating layer 115 may include silicon oxide (SiO ₂ ) Silicon nitride (SiN) _X ) Silicon oxynitride (SiON), aluminum oxide (Al) ₂ O ₃ ) Titanium oxide (TiO) ₂ ) Tantalum oxide (Ta) ₂ O ₅ ) Hafnium oxide (HfO) ₂ ) Or zinc oxide (ZnO) _x ) Etc., zinc oxide (ZnO _x ) May be ZnO and/or ZnO ₂ . The first interlayer insulating layer 115 may be a single layer or a plurality of layers including the above-described inorganic insulator.

The second semiconductor layer Act2 may be disposed on the first interlayer insulating layer 115. The second semiconductor layer Act2 may include an oxide semiconductor. For example, the second semiconductor layer Act2 may be formed of Zn oxide, in—zn oxide, ga—in—zn oxide, or the like as a Zn oxide-based substance. Alternatively, the second semiconductor layer Act2 may be provided by an IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O) semiconductor including a metal such as indium (In), gallium (Ga), or tin (Sn) In zinc oxide (ZnO).

In an embodiment, the second semiconductor layer Act2 may include a channel region, and source and drain regions disposed at both sides of the channel region. The source region and the drain region of the second semiconductor layer Act2 can be formed by adjusting the carrier concentration of the oxide semiconductor to be conductive. For example, the source region and the drain region of the second semiconductor layer Act2 may be formed by increasing the carrier concentration of the oxide semiconductor by plasma treatment using a hydrogen-series gas, a fluorine-series gas, or a combination thereof.

The third gate insulating layer 117 may cover the second semiconductor layer Act2. The third gate insulating layer 117 may be disposed between the second semiconductor layer Act2 and the second gate electrode GE 2. In one embodiment, the third gate insulating layer 117 may be integrally disposed on the substrate 100. Alternatively, the third gate insulating layer 117 may be patterned along the shape of the second gate electrode GE 2. The third gate insulating layer 117 may include silicon oxide (SiO ₂ ) Silicon nitride (SiN) _X ) Silicon oxynitride (SiON), aluminum oxide (Al) ₂ O ₃ ) Titanium oxide (TiO) ₂ ) Tantalum oxide (Ta) ₂ O ₅ ) Hafnium oxide (HfO) ₂ ) Or zinc oxide (ZnO) _x ) Etc., zinc oxide (ZnO _x ) May be ZnO and/or ZnO ₂ . The third gate insulating layer 117 may be a single layer or a plurality of layers including the above-described inorganic insulator.

The second gate electrode GE2 may be disposed on the third gate insulating layer 117. The second gate electrode GE2 may overlap the second semiconductor layer Act2. Specifically, the second gate electrode GE2 may overlap with the channel region of the second semiconductor layer Act2. The second gate electrode GE2 may include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed of multiple layers or a single layer including the above-described materials.

The second interlayer insulating layer 119 may cover the second gate electrode GE2. The second interlayer insulating layer 119 may include silicon oxide (SiO ₂ ) Silicon nitride (SiN) _X ) Silicon oxynitride (SiON), aluminum oxide (Al) ₂ O ₃ ) Titanium oxide (TiO) ₂ ) Tantalum oxide (Ta) ₂ O ₅ ) Hafnium oxide (HfO) ₂ ) Or zinc oxide (ZnO) _x ) Etc., zinc oxide (ZnO _x ) May be ZnO and/or ZnO ₂ . The second interlayer insulating layer 119 may be a single layer or a plurality of layers including the above-described inorganic insulating material.

The first source electrode SE1 and the first drain electrode DE1 may be disposed on the second interlayer insulating layer 119. The first source electrode SE1 and/or the first drain electrode DE1 may be electrically connected to the first semiconductor layer Act 1. The first source electrode SE1 and/or the first drain electrode DE1 may be electrically connected to the first semiconductor layer Act1 through a contact hole defined in the insulating layer.

The second source electrode SE2 and the second drain electrode DE2 may be disposed on the second interlayer insulating layer 119. The second source electrode SE2 and/or the second drain electrode DE2 may be electrically connected to the second semiconductor layer Act 2. The second source electrode SE2 and/or the second drain electrode DE2 may be electrically connected to the second semiconductor layer Act2 through a contact hole defined in the insulating layer.

The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may include a material having excellent conductivity. The first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and may be formed of a plurality of layers or a single layer including the above materials. In an embodiment, the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2 may have a multi-layer structure of Ti/Al/Ti.

The first thin film transistor TFT1 having the first semiconductor layer Act1 including a silicon semiconductor has high reliability, and thus can be used as a driving thin film transistor to realize a high quality display panel 10.

The oxide semiconductor has high carrier mobility (high carrier mobility) and low leakage current, and thus, even if the driving time is long, the voltage drop may not be large. That is, even at the time of low-frequency driving, the color change of the image according to the voltage drop is not large, and therefore, low-frequency driving is possible. As described above, there is an advantage in that the leakage current is small in the case of the oxide semiconductor, and therefore, the oxide semiconductor can be used for at least one of the other thin film transistors other than the driving thin film transistor to prevent the leakage current while reducing power consumption. For example, the second thin film transistor TFT2 may be used as a switching thin film transistor. Alternatively, when the third pixel circuit PC3 includes a plurality of thin film transistors, some of the plurality of thin film transistors may use a silicon semiconductor, and the remaining thin film transistors may use an oxide semiconductor.

The lower gate electrode BGE may be disposed under the second semiconductor layer Act 2. In an embodiment, the lower gate electrode BGE may be disposed between the second gate insulating layer 113 and the first interlayer insulating layer 115. In one embodiment, the lower gate electrode BGE may receive a gate signal. In this case, the second thin film transistor TFT2 may have a double gate electrode structure in which gate electrodes are disposed above and below the second semiconductor layer Act 2.

In an embodiment, the sub-wiring SWL may be disposed between the third gate insulating layer 117 and the second interlayer insulating layer 119. In an embodiment, the sub-wiring SWL may be electrically connected to the lower gate electrode BGE through a contact hole defined in the first interlayer insulating layer 115 and the third gate insulating layer 117.

In an embodiment, a lower blocking layer BSL may be disposed between the substrate 100 and the third pixel circuit PC 3. In an embodiment, the lower blocking layer BSL may overlap the first thin film transistor TFT 1. A constant voltage may be applied to the lower blocking layer BSL. As the lower blocking layer BSL is disposed under the first thin film transistor TFT1, the first thin film transistor TFT1 may be less affected by the peripheral interference signal, thereby improving the reliability of the first thin film transistor TFT 1.

The lower blocking layer BSL may include a transparent conductive substance. For example, the lower blocking layer BSL may be provided by a transparent conductive oxide (Transparent Conducting Oxide, TCO). The lower blocking layer BSL may include Indium Tin Oxide (ITO), indium zinc oxide (IZO; indium zinc oxide), zinc oxide (ZnO; zinc oxide), indium oxide (In ₂ O ₃ : an indium oxide), an indium gallium oxide (IGO; indium gallium oxide) or aluminum zinc oxide (AZO; aluminum zinc oxide) and the like.

The organic insulating layer OIL may be disposed on the inorganic insulating layer IIL. In one embodiment, the organic insulating layer OIL may be disposed on the substrate 100. The organic insulating layers OIL may include a first organic insulating layer OIL1, a second organic insulating layer OIL2, a third organic insulating layer OIL3, and a fourth organic insulating layer OIL4. However, the present utility model is not limited thereto. The organic insulating layer OIL may also include a first organic insulating layer OIL1 and a second organic insulating layer OIL2 or include a first organic insulating layer OIL1, a second organic insulating layer OIL2 and a third organic insulating layer OIL3. That is, the organic insulating layer OIL may be provided by two or three layers, not four layers.

The first organic insulation layer OIL1 may be configured to cover the first source electrode SE1, the first drain electrode DE1, the second source electrode SE2, and the second drain electrode DE2. The first organic insulating layer OIL1 may include an organic substance. For example, the first organic insulating layer OIL1 may include an organic insulator such as a general polymer such as polymethyl methacrylate (PMMA) or Polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a para-xylene polymer, a vinyl alcohol polymer, or a blend thereof.

The first connection electrode CM1 may be disposed on the first organic insulation layer OIL 1. At this time, the first connection electrode CM1 may be electrically connected to the third pixel circuit PC3 through a contact hole defined in the first organic insulation layer OIL 1. For example, the first connection electrode CM1 may be electrically connected to the first source electrode SE1 or the first drain electrode DE1 through a contact hole defined in the first organic insulation layer OIL 1.

The first connection electrode CM1 may include a material having excellent conductivity. The first connection electrode CM1 may include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed of multiple layers or a single layer including the above-described materials. In an embodiment, the first connection electrode CM1 may have a Ti/Al/Ti multilayer structure.

The second organic insulation layer OIL2 may be configured to cover the first connection electrode CM1. The second organic insulating layer OIL2 may include an organic substance. In an embodiment, the second organic insulating layer OIL2 may include the same substance as the first organic insulating layer OIL 1. Alternatively, the second organic insulating layer OIL2 may include a different substance from the first organic insulating layer OIL 1.

The second connection electrode CM2 may be disposed on the second organic insulation layer OIL 2. At this time, the second connection electrode CM2 may be electrically connected to the first connection electrode CM1 through a contact hole defined in the second organic insulation layer OIL 2.

The second connection electrode CM2 may include a material having excellent conductivity. The second connection electrode CM2 may include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed of multiple layers or a single layer including the above-described materials. In an embodiment, the second connection electrode CM2 may have a Ti/Al/Ti multilayer structure.

The third organic insulation layer OIL3 may be configured to cover the second connection electrode CM2. The third organic insulating layer OIL3 may include an organic substance. In an embodiment, the third organic insulating layer OIL3 may include the same substance as the first organic insulating layer OIL 1. Alternatively, the third organic insulating layer OIL3 may include a substance different from the first organic insulating layer OIL 1.

The third connection electrode CM3 may be disposed on the third organic insulation layer OIL 3. At this time, the third connection electrode CM3 may be electrically connected to the second connection electrode CM2 through a contact hole defined in the third organic insulation layer OIL 3. However, the third connection electrode CM3 may be omitted. When the third connection electrode CM3 is omitted, the pixel electrode 211 may be directly electrically connected to the second connection electrode CM2.

The third connection electrode CM3 may include a material having excellent conductivity. The third connection electrode CM3 may include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and may be formed of multiple layers or a single layer including the above-described materials. In an embodiment, the third connection electrode CM3 may have a Ti/Al/Ti multilayer structure.

The fourth organic insulation layer OIL4 may be configured to cover the third connection electrode CM3. The fourth organic insulating layer OIL4 may include an organic substance. In an embodiment, the fourth organic insulating layer OIL4 may include the same substance as the first organic insulating layer OIL 1. Alternatively, the fourth organic insulating layer OIL4 may include a substance different from the first organic insulating layer OIL 1.

The seventh organic light emitting element OLED7 as a display element may be disposed on the organic insulating layer OIL. The seventh organic light emitting element OLED7 may be electrically connected to the pixel circuit. The seventh organic light emitting element OLED7 in the third region AR3 may be electrically connected to the third pixel circuit PC3 to realize the third pixel PX3. In an embodiment, the seventh organic light emitting element OLED7 may overlap the third pixel circuit PC 3. The seventh organic light emitting element OLED7 may include a pixel electrode 211, an intermediate layer 212, and a counter electrode 213.

The pixel electrode 211 may be disposed on the organic insulation layer OIL. For example, the pixel electrode 211 may be disposed on the fourth organic insulating layer OIL 4. The pixel electrode 211 may be electrically connected to the third connection electrode CM3 through a contact hole defined in the fourth organic insulation layer OIL 4. The pixel electrode 211 may include Indium Tin Oxide (ITO), indium zinc oxide (IZO; indium zinc oxide), zinc oxide (ZnO), indium oxide (In) ₂ O ₃ : an indium oxide), an indium gallium oxide (IGO; indium gallium oxide) or aluminum zinc oxide (AZO; aluminum zinc oxide) and the like. Alternatively, the pixel electrode 211 may include a reflective film including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or a compound thereof. Alternatively, the pixel electrode 211 may further include a reflective film formed of ITO, IZO, znO or In on/under the reflective film ₂ O ₃ And (3) forming a film.

A pixel defining film 215 defining an opening 215OP exposing at least a portion of the pixel electrode 211 may be disposed on the pixel electrode 211. Specifically, the opening 215OP defined in the pixel defining film 215 may expose a central portion of the pixel electrode 211. The pixel defining film 215 may include an organic insulator and/or an inorganic insulator. The light emitting region of the light emitted from the seventh organic light emitting element OLED7 can be defined by the opening 215 OP.

The intermediate layer 212 may include a light emitting layer. The light emitting layer may include a low molecular substance or a high molecular substance, and may emit red, green, blue, or white light. When the light emitting Layer includes a low molecular substance, the intermediate Layer 212 may have a hole injection Layer (HIL: hole Injection Layer), a hole transport Layer (HTL: hole Transport Layer), a light emitting Layer (EML: emission Layer), an electron transport Layer (ETL: el)ectron Transport Layer), electron injection layer (EIL: electron Injection Layer) and the like laminated in a single or composite structure, may include copper phthalocyanine (CuPc: copper phthalocyanine), N '-bis (naphthalen-1-yl) -N, N' -diphenyl-benzidine (N, N '-Di (naphthalen-1-yl) -N, N' -diphenyl-benzodine: NPB), tris-8-hydroxyquinoline aluminum (tris-8-hydroxyquinoline aluminum: alq ₃ ) And the like. Such a layer may be formed by a vacuum evaporation method.

When the light-emitting layer includes a polymer substance, the intermediate layer 212 may have a structure including a hole-transporting layer and a light-emitting layer. In this case, the hole transport layer may include PEDOT, and the light emitting layer may include a polymer such as PPV (Poly-phenyl-vinylene) and Polyfluorene (Polyfluorene). Such an intermediate layer 212 may be formed by a screen printing or inkjet printing method, a laser thermal transfer printing method (LITI; laser induced thermal imaging), or the like.

The counter electrode 213 may be disposed on the intermediate layer 212. The counter electrode 213 may be made of a conductive substance having a low work function. For example, the counter electrode 213 may include a (semi) transparent layer including silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or an alloy thereof, or the like. Alternatively, the counter electrode 213 may further include ITO, IZO, znO or In on the (semi) transparent layer including the above substances ₂ O ₃ And the like.

Fig. 9 is a sectional view schematically showing a display device according to an embodiment of the present utility model. Specifically, fig. 9 is a sectional view schematically showing the display panel 10 of fig. 6 along the line C-C'. In fig. 9, the same reference numerals as those in fig. 8 denote the same components, and thus, duplicate descriptions are omitted.

Referring to fig. 9, the display panel 10 may include a substrate 100, an insulating layer IL, a first pixel circuit PC1, a second pixel circuit PC2, a first organic light emitting element OLED1, a fourth organic light emitting element OLED4, and a pixel defining film 215.

In an embodiment, the first pixel circuit PC1, the second pixel circuit PC2, and the fourth organic light emitting element OLED4 may be disposed in the second region AR2, and the first organic light emitting element OLED1 may be disposed in the first region AR 1. The first organic light emitting element OLED1 disposed on the first region AR1 may emit light to realize the first pixel PX1. The fourth organic light emitting element OLED4 disposed on the second region AR2 may emit light to realize the fourth pixel PX4.

The first pixel circuit PC1 and the second pixel circuit PC2 may be disposed on the second area AR 2. The first and second pixel circuits PC1 and PC2 may include first and second thin film transistors TFT1 and TFT2 and a storage capacitor Cst, respectively. The first thin film transistor TFT1 may include a first semiconductor layer Act1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1. The second thin film transistor TFT2 may include a second semiconductor layer Act2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2. The storage capacitor Cst may include a lower electrode CE1 and an upper electrode CE2.

The first connection electrode CM1 may be disposed on the first organic insulation layer OIL1 of the second region AR2, the second connection electrode CM2 may be disposed on the second organic insulation layer OIL2, and the third connection electrode CM3 may be disposed on the third organic insulation layer OIL 3. In addition, the first intermediate connection electrode MCM1 may be disposed on the second interlayer insulating layer 119 of the first region AR1, the second intermediate connection electrode MCM2 may be disposed on the first organic insulating layer OIL1, the third intermediate connection electrode MCM3 may be disposed on the second organic insulating layer OIL2, and the fourth intermediate connection electrode MCM4 may be disposed on the third organic insulating layer OIL 3.

The first intermediate connection electrode MCM1 of the first region AR1 may be provided with the same material at the same layer as the first source electrode SE1 of the second region AR 2. The second intermediate connection electrode MCM2 of the first region AR1 may be provided with the same substance at the same layer as the first connection electrode CM1 of the second region AR 2. The third intermediate connection electrode MCM3 of the first region AR1 may be provided with the same material at the same layer as the second connection electrode CM2 of the second region AR 2. The fourth intermediate connection electrode MCM4 of the first region AR1 may be provided with the same substance at the same layer as the third connection electrode CM3 of the second region AR 2.

In an embodiment, the fourth organic light emitting element OLED4 may be disposed on the fourth organic insulating layer OIL4 of the second region AR 2. However, the present utility model is not limited thereto. As described below with reference to fig. 12, the fifth organic light emitting element OLED5 (see fig. 12) and the sixth organic light emitting element OLED6 (see fig. 12) may be disposed on the second region AR 2. The fourth organic light emitting element OLED4 may include a fourth pixel electrode 211d, an intermediate layer 212, and a counter electrode 213.

In an embodiment, a fourth connection wiring CWL4 may be disposed on the second area AR 2. The fourth connection wiring CWL4 may be disposed on the fourth organic insulating layer OIL 4. The fourth connection wiring CWL4 may be provided with the same material in the same layer as the fourth pixel electrode 211d of the fourth organic light emitting element OLED4. The fourth connection wiring CWL4 may be provided integrally with the fourth pixel electrode 211 d.

The fourth connection wiring CWL4 may electrically connect the fourth organic light emitting elements OLED4 to each other. The two fourth organic light emitting elements OLED4 may be electrically connected to each other through the fourth connection wiring CWL 4. As another representation, the two fourth pixel electrodes 211d may be electrically connected to each other through the fourth connection wiring CWL 4. However, the present utility model is not limited thereto. The two or more fourth organic light emitting elements OLED4 may be electrically connected by one fourth connection wiring CWL 4.

The second pixel circuit PC2 disposed on the second region AR2 is electrically connected to one fourth organic light emitting element OLED4, and one fourth organic light emitting element OLED4 and the other fourth organic light emitting element OLED4 are electrically connected through the fourth connection wiring CWL4, and thus, the two fourth organic light emitting elements OLED4 can be driven by one second pixel circuit PC 2.

The fourth organic light emitting element OLED4 is illustrated in fig. 9, but the fifth organic light emitting element OLED5 and the sixth organic light emitting element OLED6 may be provided identically or similarly.

In an embodiment, the first organic light emitting element OLED1 may be disposed on the fourth organic insulating layer OIL4 of the first region AR 1. However, the present utility model is not limited thereto. As described below with reference to fig. 10, the second organic light emitting element OLED2 (see fig. 10) and the third organic light emitting element OLED3 (see fig. 10) may be disposed on the first region AR 1. The first organic light emitting element OLED1 may include a first pixel electrode 211a, an intermediate layer 212, and a counter electrode 213.

The pixel circuit may not be disposed on the first area AR1. Specifically, the first organic light emitting element OLED1 may be disposed on the first region AR1, but a pixel circuit (for example, a first pixel circuit PC 1) for driving the first organic light emitting element OLED1 disposed on the first region AR1 is disposed on the second region AR 2. That is, the first organic light emitting element OLED1 disposed on the first region AR1 may be driven by the first pixel circuit PC1 disposed on the second region AR 2.

In an embodiment, the first pixel circuit PC1 disposed on the second region AR2 and the first organic light emitting element OLED1 disposed on the first region AR1 may be electrically connected through the intermediate connection wiring MWL. The intermediate connection wiring MWL may be disposed on the second organic insulation layer OIL 2. However, the present utility model is not limited thereto. For example, the intermediate connection wiring MWL may be disposed on the first organic insulating layer OIL1 or on the third organic insulating layer OIL 3. The intermediate connection wiring MWL may extend from the second area AR2 to the first area AR1. The intermediate connection wiring MWL may be disposed in the first area AR1 and the second area AR 2.

In an embodiment, the intermediate connection wiring MWL may be electrically connected to the first pixel circuit PC1 disposed on the second area AR 2. In addition, the intermediate connection wiring MWL may be electrically connected to the first organic light emitting element OLED1 disposed on the first region AR1. Specifically, the intermediate connection wiring MWL may be electrically connected to the first pixel circuit PC1 through the first connection electrode CM 1. In addition, the intermediate connection wiring MWL may be electrically connected to the first organic light emitting element OLED1 through the fourth intermediate connection electrode MCM 4. Based on this, the first pixel circuit PC1 disposed on the second region AR2 and the first organic light emitting element OLED1 disposed on the first region AR1 can be electrically connected.

In an embodiment, the first connection wiring CWL1 may be disposed on the first area AR 1. The first connection wiring CWL1 may be disposed on the first interlayer insulating layer 115. The first connection wiring CWL1 may be provided with the same substance in the same layer as the second semiconductor layer Act 2.

The first connection wiring CWL1 may electrically connect the first organic light emitting elements OLED1 to each other. The two first organic light emitting elements OLED1 may be electrically connected to each other through the first connection wiring CWL1. As another representation, the two first pixel electrodes 211a may be electrically connected to each other through the first connection wiring CWL1. However, the present utility model is not limited thereto. The two or more first organic light emitting elements OLED1 may be electrically connected by one first connection wiring CWL1.

The first pixel circuit PC1 disposed on the second region AR2 is electrically connected to one first organic light emitting element OLED1, and one first organic light emitting element OLED1 and the other first organic light emitting element OLED1 are electrically connected through the first connection wiring CWL1, and thus, the two first organic light emitting elements OLED1 can be driven by one first pixel circuit PC 1.

Fig. 10 is a plan view schematically showing a display panel according to an embodiment of the present utility model, and fig. 11 is a sectional view schematically showing a display panel according to an embodiment of the present utility model. Specifically, fig. 10 is a plan view schematically showing a part of the first area AR1, and fig. 11 is a sectional view schematically showing the display panel of fig. 10 along the line D-D'.

Referring to fig. 10 and 11, the display panel 10 may include a substrate 100, an insulating layer IL, an organic light emitting element OLED as a display element, and a connection wiring CWL.

In an embodiment, the first region AR1 may include a transmissive region TW. As another expression, a transmissive region TW may be defined in the first region AR 1. The transmission region TW is a region having higher light transmittance than the first region AR1 except for the transmission region TW, and the transmission region TW may be a region where a conductive material or an insulating layer is not deposited in order to improve light transmittance. For example, the transmission region TW may be a region where the connection wiring CWL and the pixel electrodes 211a, 211b, 211c are not evaporated.

An organic light emitting element OLED as a display element may be disposed on the substrate 100. The organic light emitting element OLED may be provided in plural. In an embodiment, the organic light emitting element OLED may include a first organic light emitting element OLED1 as a first display element, a second organic light emitting element OLED2 as a second display element, and a third organic light emitting element OLED3 as a third display element. In an embodiment, the first organic light emitting element OLED1, the second organic light emitting element OLED2, and the third organic light emitting element OLED3 may be provided in plurality, respectively.

In an embodiment, the plurality of display elements may implement the first pixel PX1, the second pixel PX2, and the third pixel PX3 that emit light of different wavelength bands from each other. In this specification, a pixel means a light emitting region as a minimum unit for realizing an image. On the other hand, when an organic light-emitting element is used as a display element, a light-emitting region can be defined by the opening portion 215OP of the pixel defining film 215.

In an embodiment, the first organic light emitting element OLED1 as the first display element may implement the first pixel PX1. The second organic light emitting element OLED2 as the second display element may implement the second pixel PX2. The third organic light emitting element OLED3 as the third display element may implement the third pixel PX3.

In an embodiment, the first pixel PX1, the second pixel PX2, and the third pixel PX3 may emit one of red light, green light, and blue light, respectively. For example, the first, second, and third pixels PX1, PX2, and PX3 may emit red, blue, and green light, respectively. Alternatively, the display panel 10 may further include sub-pixels emitting white light.

In an embodiment, an organic light emitting element OLED may be disposed on the first region AR1 as a display element. The organic light emitting elements OLED may include a first organic light emitting element OLED1, a second organic light emitting element OLED2, and a third organic light emitting element OLED3. Accordingly, the first organic light emitting element OLED1, the second organic light emitting element OLED2, and the third organic light emitting element OLED3 may be disposed on the first region AR 1. The first organic light emitting elements OLED1 may include first pixel electrodes 211a, respectively, the second organic light emitting elements OLED2 may include second pixel electrodes 211b, respectively, and the third organic light emitting elements OLED3 may include third pixel electrodes 211c, respectively.

In an embodiment, on the xy plane, the respective pixels PX1, PX2, PX3 arranged on the first area AR1 may be provided in an egg-like shape. As another expression, the pixels PX1, PX2, PX3 disposed in the first region AR1 may be provided in a deformed circular shape on the xy plane. As yet another expression, on the xy plane, the respective pixels PX1, PX2, PX3 arranged on the first region AR1 may be provided in an elliptical (oval) shape. However, the present utility model is not limited thereto. On the xy plane, the pixels PX1, PX2, PX3 disposed in the first region AR1 may be provided in a shape such as a circle, a quadrangle, or a polygon.

Alternatively, the pixels PX1, PX2, PX3 are realized by the organic light emitting elements OLED, and therefore, each of the organic light emitting elements OLED disposed on the first region AR1 may be provided in an egg-like shape on the xy plane. As another expression, each of the organic light emitting elements OLED disposed on the first region AR1 may be provided in a deformed circular shape on the xy plane. As yet another expression, each of the organic light emitting elements OLED disposed on the first region AR1 may have an elliptical (oval) shape on the xy plane. However, the present utility model is not limited thereto. In the xy plane, each of the organic light emitting elements OLED disposed in the first region AR1 may have a circular shape, a quadrangular shape, a polygonal shape, or the like.

At this time, the shape of the organic light emitting element OLED may mean the shape of the pixel electrode. Accordingly, the pixel electrodes 211a, 211b, 211c disposed on the first region AR1 may be provided in an egg-like shape on the xy plane. As another expression, the pixel electrodes 211a, 211b, 211c arranged on the first region AR1 may be provided in a deformed circular shape on the xy plane. As yet another expression, the pixel electrodes 211a, 211b, 211c arranged on the first region AR1 may be provided in an elliptical (oval) shape on the xy plane. However, the present utility model is not limited thereto. The pixel electrodes 211a, 211b, 211c disposed in the first region AR1 may be provided in a circular shape, a quadrangular shape, a polygonal shape, or the like on the xy plane.

As described above, the pixel circuit PC (see fig. 3) may not be disposed in the first region AR 1. Accordingly, the organic light emitting element OLED disposed on the first region AR1 may be electrically connected to the first pixel circuit PC1 (see fig. 3) disposed on the second region AR2 (see fig. 3) through the intermediate connection wiring MWL (see fig. 3).

Specifically, the first pixel circuit PC1 disposed on the second region AR2 may be electrically connected to one first organic light emitting element OLED1 disposed on the first region AR1 through the intermediate connection wiring MWL. The first pixel circuit PC1 disposed on the second region AR2 may be electrically connected to one of the second organic light emitting elements OLED2 disposed on the first region AR1 through the intermediate connection wiring MWL. The first pixel circuit PC1 disposed on the second region AR2 may be electrically connected to one third organic light emitting element OLED3 disposed on the first region AR1 through the intermediate connection wiring MWL. In this case, the intermediate connection wiring MWL may be provided with the same material at the same layer as the second connection electrode CM2 (see fig. 8) or the third connection electrode CM3 (see fig. 8) described above with reference to fig. 8. Accordingly, the light transmittance of the display panel 10 in the first region AR1 may be increased.

In an embodiment, the connection wiring CWL may be disposed on the first area AR 1. The connection wirings CWL may include a first connection wiring CWL1, a second connection wiring CWL2, and a third connection wiring CWL3.

In an embodiment, the connection wiring CWL may electrically connect the organic light emitting elements OLED to each other. The first connection wiring CWL1 may electrically connect the first organic light emitting elements OLED1 to each other. The two first organic light emitting elements OLED1 may be electrically connected to each other through the first connection wiring CWL 1. As another representation, the two first pixel electrodes 211a may be electrically connected to each other through the first connection wiring CWL 1. The second connection wiring CWL2 may electrically connect the second organic light emitting elements OLED2 to each other. The two second organic light emitting elements OLED2 may be electrically connected to each other through the second connection wiring CWL 2. As another representation, the two second pixel electrodes 211b may be electrically connected to each other through the second connection wiring CWL 2. The third connection wiring CWL3 may electrically connect the third organic light emitting elements OLED3 to each other. The four third organic light emitting elements OLED3 may be electrically connected to each other through the third connection wiring CWL3. As another representation, the four third pixel electrodes 211c may be electrically connected to each other through the third connection wiring CWL3.

In an embodiment, the connection wiring CWL disposed on the first region AR1 may overlap at least a portion of the organic light emitting element OLED. The connection wiring CWL disposed on the first region AR1 may overlap at least a portion of the pixel electrodes 211a, 211b, 211 c. Specifically, the first connection wiring CWL1 may overlap at least a portion of the second pixel electrode 211b of the second organic light emitting element OLED2 and the third pixel electrode 211c of the third organic light emitting element OLED 3. The second connection wiring CWL2 may overlap at least a portion of the third pixel electrode 211c of the third organic light emitting element OLED 3. In addition, the third connection wiring CWL3 may overlap at least a portion of the second pixel electrode 211b of the second organic light emitting element OLED 2. The area of the transmission region TW included in the first region AR1 can be increased by overlapping the connection wiring CWL disposed on the first region AR1 with at least a portion of the pixel electrodes 211a, 211b, 211c of the organic light emitting element OLED, whereby the light transmittance of the display panel 10 in the first region AR1 can be improved.

Referring to fig. 11, an insulating layer IL, a first pixel electrode 211a, a second pixel electrode 211b, a third pixel electrode 211c, a pixel defining film 215, an intermediate layer 212, and a counter electrode 213 may be disposed on the substrate 100.

As illustrated in fig. 8, the insulating layer IL may include an inorganic insulating layer IL and an organic insulating layer OIL. The inorganic insulating layer IIL may include a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, a first interlayer insulating layer 115, a third gate insulating layer 117, and a second interlayer insulating layer 119. The organic insulating layers OIL may include a first organic insulating layer OIL1, a second organic insulating layer OIL2, a third organic insulating layer OIL3, and a fourth organic insulating layer OIL4.

In an embodiment, the first connection wire CWL1 may be disposed on the first interlayer insulating layer 115. The first connection wiring CWL1 may include an oxide semiconductor. For example, the first connection wiring CWL1 may be formed of Zn oxide, in-Zn oxide, ga-In-Zn oxide, or the like as a Zn oxide-based substance. Alternatively, the first connection wiring CWL1 may be provided by an IGZO (In-Ga-Zn-O), ITZO (In-Sn-Zn-O), or IGTZO (In-Ga-Sn-Zn-O) semiconductor including a metal such as indium (In), gallium (Ga), or tin (Sn) In zinc oxide (ZnO). The first connection wiring CWL1 may be provided with the same substance in the same layer as the second semiconductor layer Act2 (see fig. 8) described above in fig. 8.

In one embodiment, the first, second, and third connection wirings CWL1, CWL2, and CWL3 may be provided with the same substance in the same layer. Since the first connection wiring CWL1 and the second semiconductor layer Act2 are provided with the same substance in the same layer, the second connection wiring CWL2 and the third connection wiring CWL3 may be provided with the same substance in the same layer as the second semiconductor layer Act 2.

The organic light emitting element OLED can be connected by the connection wiring CWL provided in the same layer and made of the same substance as the second semiconductor layer Act2 disposed on the third region AR3 (see fig. 8), thereby reducing the number of masks used in the manufacturing process of the display device. Based on this, the manufacturing process of the display device can be simplified. Further, the connection wiring CWL disposed in the first region AR1 can be provided with an oxide semiconductor having high light transmittance, and therefore, the light transmittance of the first region AR1 can be increased. By widening the width or thickening the thickness of the connection wiring CWL, even in the case where the connection wiring CWL is provided with an oxide semiconductor, occurrence of a luminance difference between sub-pixels due to resistivity can be prevented or reduced.

The first intermediate connection electrode MCM1 may be disposed on the second interlayer insulating layer 119. The second intermediate connection electrode MCM2 may be disposed on the first organic insulation layer OIL 1. A third intermediate connection electrode MCM3 may be disposed on the second organic insulation layer OIL 2. A fourth intermediate connection electrode MCM4 may be disposed on the third organic insulation layer OIL 3. The first pixel electrode 211a, the second pixel electrode 211b, and the third pixel electrode 211c may be disposed on the fourth organic insulating layer OIL 4.

In an embodiment, the first pixel electrode 211a may be electrically connected to the first connection wiring CWL 1. At this time, since a plurality of insulating layers are present between the first pixel electrode 211a and the first connection wiring CWL1, the first pixel electrode 211a and the first connection wiring CWL1 are not electrically connected through one contact hole, but may be electrically connected through the first intermediate connection electrode MCM1, the second intermediate connection electrode MCM2, the third intermediate connection electrode MCM3, and the fourth intermediate connection electrode MCM4 located between the first pixel electrode 211a and the first connection wiring CWL 1. For example, the first intermediate connection electrode MCM1 may be electrically connected to the first connection wiring CWL1 through a contact hole defined in the third gate insulating layer 117 and the second interlayer insulating layer 119. The second intermediate connection electrode MCM2 may be electrically connected to the first intermediate connection electrode MCM1 through a contact hole defined in the first organic insulation layer OIL 1. The third intermediate connection electrode MCM3 may be electrically connected to the second intermediate connection electrode MCM2 through a contact hole defined in the second organic insulation layer OIL 2. The fourth intermediate connection electrode MCM4 may be electrically connected to the third intermediate connection electrode MCM3 through a contact hole defined in the third organic insulation layer OIL 3. The first pixel electrode 211a may be electrically connected to the fourth intermediate connection electrode MCM4 through a contact hole defined in the fourth organic insulation layer OIL 4. Accordingly, the first connection wiring CWL1 and the first pixel electrode 211a may be electrically connected through the first intermediate connection electrode MCM1, the second intermediate connection electrode MCM2, the third intermediate connection electrode MCM3, and the fourth intermediate connection electrode MCM 4. The first pixel electrode 211a and the first connection wiring CWL1 are mainly described in fig. 11, but the second pixel electrode 211b and the second connection wiring CWL2, and the third pixel electrode 211c and the third connection wiring CWL3 may be electrically connected by the same or similar method.

An opening 215OP may be defined in the pixel defining film 215. At least a portion of the first pixel electrode 211a may be exposed through an opening 215OP defined in the pixel defining film 215. In addition, a light emitting region of light emitted from the first organic light emitting element OLED1 may be defined by the opening 215OP.

In an embodiment, a contact hole for connecting the first connection wiring CWL1 and the first pixel electrode 211a may overlap with an opening 215OP defined in the pixel defining film 215. That is, a contact hole for connecting the first connection wiring CWL1 and the first pixel electrode 211a may be located under the opening 215OP defined in the pixel defining film 215. Based on this, the area of the transmission region TW included in the first region AR1 can be increased, and thus, the light transmittance of the display panel 10 in the first region AR1 can be improved.

As described above, the first connection wiring CWL1 may overlap at least a portion of the second pixel electrode 211b and/or the third pixel electrode 211 c. In addition, the second connection wiring CWL2 may overlap at least a portion of the third pixel electrode 211 c. However, the present utility model is not limited thereto. The second connection wiring CWL2 may overlap at least a portion of the first pixel electrode 211 a. The third connection wiring CWL3 may overlap at least a portion of the second pixel electrode 211 b. However, the present utility model is not limited thereto. The third connection wiring CWL3 may overlap at least a portion of the first pixel electrode 211 a.

Fig. 12 is a plan view schematically showing a display panel according to an embodiment of the present utility model, and fig. 13 is a sectional view schematically showing a display panel according to an embodiment of the present utility model. Specifically, fig. 12 is a plan view schematically showing a part of the second area AR2, and fig. 13 is a sectional view schematically showing the display panel of fig. 12 along the line E-E'.

Referring to fig. 12 and 13, the display panel 10 may include a substrate 100, an insulating layer IL, an organic light emitting element OLED as a display element, and a connection wiring CWL.

An organic light emitting element OLED as a display element may be disposed on the substrate 100. The organic light emitting element OLED may be provided in plural. In an embodiment, the organic light emitting elements OLED may include a fourth organic light emitting element OLED4 as a fourth display element, a fifth organic light emitting element OLED5 as a fifth display element, and a sixth organic light emitting element OLED6 as a sixth display element. In one embodiment, the fourth organic light emitting element OLED4, the fifth organic light emitting element OLED5, and the sixth organic light emitting element OLED6 may be provided in plurality.

In an embodiment, the plurality of display elements may implement the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 that emit light of different wavelength bands from each other. In this specification, a subpixel means a light emitting region as a minimum unit for realizing an image. On the other hand, when an organic light-emitting element is used as a display element, a light-emitting region can be defined by the opening portion 215OP of the pixel defining film 215.

In an embodiment, the fourth organic light emitting element OLED4 as a fourth display element may implement the fourth pixel PX4. The fifth organic light emitting element OLED5 as the fifth display element may implement the fifth pixel PX5. The sixth organic light emitting element OLED6 as the sixth display element may realize the sixth pixel PX6.

In an embodiment, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 may emit one of red light, green light, and blue light, respectively. For example, the fourth pixel PX4, the fifth pixel PX5, and the sixth pixel PX6 may emit red light, blue light, and green light, respectively. Alternatively, the display panel 10 may further include sub-pixels emitting white light.

In an embodiment, an organic light emitting element OLED may be disposed on the second region AR2 as a display element. The organic light emitting elements OLED may include a fourth organic light emitting element OLED4, a fifth organic light emitting element OLED5, and a sixth organic light emitting element OLED6. Accordingly, the fourth organic light emitting element OLED4, the fifth organic light emitting element OLED5, and the sixth organic light emitting element OLED6 may be disposed on the second region AR 2. The fourth organic light emitting elements OLED4 may include fourth pixel electrodes 211d, respectively, the fifth organic light emitting elements OLED5 may include fifth pixel electrodes 211e, respectively, and the sixth organic light emitting elements OLED6 may include sixth pixel electrodes 211f, respectively.

In an embodiment, each of the pixels PX4, PX5, PX6 disposed on the second area AR2 may be provided in an egg-like shape on the xy plane. As another expression, the pixels PX4, PX5, PX6 disposed in the second region AR2 may be provided in a deformed circular shape on the xy plane. As yet another expression, the respective pixels PX4, PX5, PX6 arranged on the second region AR2 may be provided in an elliptical (oval) shape on the xy plane. However, the present utility model is not limited thereto. On the xy plane, the pixels PX4, PX5, PX6 disposed in the second region AR2 may be provided in a shape such as a circle, a quadrangle, or a polygon.

Alternatively, the pixels PX4, PX5, PX6 are realized by the organic light emitting elements OLED, and therefore, each of the organic light emitting elements OLED disposed on the second region AR2 may be provided in an egg-shape on the xy plane. As another expression, each of the organic light emitting elements OLED disposed on the second region AR2 may be provided in a deformed circular shape on the xy plane. As yet another expression, each of the organic light emitting elements OLED disposed on the second region AR2 may have an elliptical (oval) shape on the xy plane. However, the present utility model is not limited thereto. In the xy plane, each of the organic light emitting elements OLED disposed in the second region AR2 may have a circular shape, a quadrangular shape, a polygonal shape, or the like.

At this time, the shape of the organic light emitting element OLED may mean the shape of the pixel electrode. Accordingly, the pixel electrodes 211d, 211e, 211f disposed on the second region AR2 may be provided in an egg-like shape on the xy plane. As another expression, the pixel electrodes 211d, 211e, 211f arranged on the second region AR2 may be provided in a deformed circular shape on the xy plane. As yet another expression, the pixel electrodes 211d, 211e, 211f arranged on the second region AR2 may have an elliptical (oval) shape on the xy plane. However, the present utility model is not limited thereto. The pixel electrodes 211d, 211e, 211f disposed in the second region AR2 may be provided in a circular shape, a quadrangular shape, a polygonal shape, or the like on the xy plane.

As described in fig. 3 above, a plurality of organic light emitting elements OLED as a plurality of display elements may be electrically connected to one second pixel circuit PC2. At this time, the organic light emitting elements OLED may be electrically connected to each other through the connection wiring CWL.

In an embodiment, the connection wiring CWL may be disposed on the second area AR 2. The connection wirings CWL may include a fourth connection wiring CWL4, a fifth connection wiring CWL5, and a sixth connection wiring CWL6.

In an embodiment, the connection wiring CWL may electrically connect the organic light emitting elements OLED to each other. The fourth connection wiring CWL4 may electrically connect the fourth organic light emitting elements OLED4 to each other. The two fourth organic light emitting elements OLED4 may be electrically connected to each other through the fourth connection wiring CWL 4. As another representation, the two fourth pixel electrodes 211d may be electrically connected to each other through the fourth connection wiring CWL 4. The fifth connection wiring CWL5 may electrically connect the fifth organic light emitting elements OLED5 to each other. The two fifth organic light emitting elements OLED5 may be electrically connected to each other through the fifth connection wiring CWL 5. As another representation, the two fifth pixel electrodes 211e may be electrically connected to each other through the fifth connection wiring CWL 5. The sixth connection wiring CWL6 may electrically connect the sixth organic light emitting elements OLED6 to each other. The four sixth organic light emitting elements OLED6 may be electrically connected to each other through the sixth connection wiring CWL 6. As another representation, the four sixth pixel electrodes 211f may be electrically connected to each other through the sixth connection wiring CWL 6.

Referring to fig. 13, an insulating layer IL, a fourth pixel electrode 211d, a fifth pixel electrode 211e, a sixth pixel electrode 211f, a pixel defining film 215, an intermediate layer 212, and a counter electrode 213 may be disposed on the substrate 100.

As described in fig. 8 above, the insulating layer IL may include an inorganic insulating layer IIL and an organic insulating layer OIL. The inorganic insulating layer IIL may include a buffer layer 111, a first gate insulating layer 112, a second gate insulating layer 113, a first interlayer insulating layer 115, a third gate insulating layer 117, and a second interlayer insulating layer 119. The organic insulating layers OIL may include a first organic insulating layer OIL1, a second organic insulating layer OIL2, a third organic insulating layer OIL3, and a fourth organic insulating layer OIL4.

The second pixel circuit PC2 may be disposed on the substrate 100. The two fourth organic light emitting elements OLED4 may be driven by one second pixel circuit PC2. At this time, the second pixel circuit PC2 may overlap with one fourth organic light emitting element OLED4. However, the second pixel circuit PC2 may not overlap with the remaining one fourth organic light emitting element OLED4. The second pixel circuit PC2 may be provided in the same or similar manner as the third pixel circuit PC3 described above in fig. 8. However, the present utility model is not limited thereto. The second pixel circuit PC2 may be provided separately from the third pixel circuit PC 3.

The second pixel circuit PC2 may be electrically connected to the fourth organic light emitting element OLED4 through the first, second, and third connection electrodes CM1, CM2, and CM3 disposed on the first, second, and third organic insulating layers OIL1, OIL2, and OIL3, respectively. Specifically, the second pixel circuit PC2 may be electrically connected to the fourth pixel electrode 211d of the fourth organic light emitting element OLED4 through the first, second, and third connection electrodes CM1, CM2, and CM3 disposed on the first, second, and third organic insulating layers OIL1, OIL2, and OIL3, respectively. Accordingly, the second pixel circuit PC2 can drive the fourth organic light emitting element OLED4 disposed thereabove.

The fourth pixel electrode 211d may be disposed on the fourth organic insulating layer OIL 4. A pixel defining film 215 defining an opening 215OP exposing at least a portion of the fourth pixel electrode 211d may be disposed on the fourth pixel electrode 211d. In addition, an intermediate layer 212 and a counter electrode 213 may be disposed on the fourth pixel electrode 211d.

In addition, a fourth connection wiring CWL4 may be disposed on the fourth organic insulating layer OIL 4. In one embodiment, the fourth connection wiring CWL4 may be provided with the same substance in the same layer as the fourth pixel electrode 211d.

In one embodiment, the fourth connecting wire CWL4, the fifth connecting wire CWL5, and the sixth connecting wire CWL6 may be provided with the same substance in the same layer. Since the fourth connection wiring CWL4 and the fourth pixel electrode 211d are provided with the same substance in the same layer, the fifth connection wiring CWL5 and the sixth connection wiring CWL6 may be provided with the same substance in the same layer as the fourth pixel electrode 211d.

The organic light emitting element OLED can be connected by the connection wiring CWL provided with the same substance in the same layer as the fourth pixel electrode 211d, thereby reducing the number of masks used for the manufacturing process of the display device. Based on this, the manufacturing process of the display device can be simplified.

In an embodiment, the fourth connection wiring CWL4 may electrically connect the fourth pixel electrodes 211d spaced apart from each other. That is, the two fourth organic light emitting elements OLED4 may be electrically connected to each other through the fourth connection wiring CWL 4. The fourth pixel electrode 211d and the fourth connection wiring CWL4 may be provided with the same substance in the same layer and electrically connected to each other, and thus the fourth pixel electrode 211d and the fourth connection wiring CWL4 may be integrally provided. However, the present utility model is not limited thereto. The fourth pixel electrode 211d and the fourth connection wiring CWL4 may be provided to be spaced apart from each other, and may be electrically connected to each other through separate wirings. Although the fourth pixel electrode 211d and the fourth connection wiring CWL4 are mainly described in fig. 13, the fifth pixel electrode 211e and the fifth connection wiring CWL5, and the sixth pixel electrode 211f and the sixth connection wiring CWL6 may be electrically connected by the same or similar method.

Fig. 14 is a plan view schematically showing a display panel according to an embodiment of the present utility model. Specifically, fig. 14 is a plan view schematically showing a part of the first area AR 1. In fig. 14, the same reference numerals as those in fig. 10 denote the same components, and thus their repetitive description is omitted.

Referring to fig. 14, the display panel 10 may include an organic light emitting element OLED as a display element and a connection wiring CWL.

In an embodiment, the connection wiring CWL may electrically connect the organic light emitting elements OLED to each other. The first connection wiring CWL1 may electrically connect the first organic light emitting elements OLED1 to each other. The two first organic light emitting elements OLED1 may be electrically connected to each other through the first connection wiring CWL 1. As another representation, the two first pixel electrodes 211a may be electrically connected to each other through the first connection wiring CWL 1. The second connection wiring CWL2 may electrically connect the second organic light emitting elements OLED2 to each other. The two second organic light emitting elements OLED2 may be electrically connected to each other through the second connection wiring CWL 2. As another representation, the two second pixel electrodes 211b may be electrically connected to each other through the second connection wiring CWL 2. The third connection wiring CWL3 may electrically connect the third organic light emitting elements OLED3 to each other. The two third organic light emitting elements OLED3 may be electrically connected to each other through the third connection wiring CWL3. As another representation, the two third pixel electrodes 211c may be electrically connected to each other through the third connection wiring CWL3.

In an embodiment, the connection wiring CWL disposed on the first region AR1 may overlap at least a portion of the organic light emitting element OLED. The connection wiring CWL disposed on the first region AR1 may overlap at least a portion of the pixel electrodes 211a, 211b, 211 c. For example, the first connection wiring CWL1 may overlap at least a portion of the third pixel electrode 211c of the third organic light emitting element OLED 3. The second connection wiring CWL2 may overlap at least a portion of the first pixel electrode 211a of the first organic light emitting element OLED1 and the third pixel electrode 211c of the third organic light emitting element OLED 3. In addition, the third connection wiring CWL3 may overlap at least a portion of the second pixel electrode 211b of the second organic light emitting element OLED 2. However, the present utility model is not limited thereto. The first connection wiring CWL1 may overlap at least a portion of the second pixel electrode 211b of the second organic light emitting element OLED2, and the third connection wiring CWL3 may overlap at least a portion of the first pixel electrode 211a of the first organic light emitting element OLED 1.

The area of the transmission region TW included in the first region AR1 can be increased by overlapping the connection wiring CWL disposed on the first region AR1 with at least a portion of the pixel electrodes 211a, 211b, 211c of the organic light emitting element OLED, whereby the light transmittance of the display panel 10 in the first region AR1 can be improved.

In an embodiment, the overall shape of the connection wiring CWL may be x-shaped in the xy plane. For example, on the xy plane, the first connection wiring CWL1 may extend integrally in a first direction (e.g., a +x direction) and a diagonal direction (e.g., a third direction) of a second direction (e.g., a +y direction) intersecting the first direction (e.g., the +x direction). In the xy plane, the third connection wiring CWL3 may integrally extend in a fourth direction crossing the third direction. In addition, on the xy plane, a part of the second connection wirings CWL2 may extend in the third direction and the fourth direction, respectively. Accordingly, the overall shape of the first, second, and third connecting wirings CWL1, CWL2, and CWL3 may be x-shaped.

In an embodiment, at least a portion of the first connection wirings CWL1 and at least a portion of the second connection wirings CWL2 may be parallel to each other. For example, at least a portion of the first connection wirings CWL1 and at least a portion of the second connection wirings CWL2 may be parallel to each other in the second direction (e.g., the +y direction). In addition, at least a portion of the first connection wirings CWL1 and at least a portion of the second connection wirings CWL2 may be parallel to each other in the third direction.

In addition, at least a part of the first connection wiring CWL1 and at least a part of the third connection wiring CWL3 may be parallel to each other. For example, at least a part of the first connection wirings CWL1 and at least a part of the third connection wirings CWL3 may be parallel to each other in the fourth direction.

The utility model has been described with reference to the embodiments shown in the drawings, which are merely illustrative, and it will be understood by those skilled in the art that various modifications and equivalent embodiments may be implemented based on them. Accordingly, the true technical scope of the present utility model should be determined by the technical idea of the appended claims.

Claims

1. A display device is characterized by comprising:

a substrate including a first region, a second region surrounding at least a portion of the first region, and a third region surrounding at least a portion of the second region;

a first display element disposed on the first region and including a first pixel electrode;

a second display element disposed on the first region and including a second pixel electrode;

a third display element disposed on the first region and including a third pixel electrode;

A first connection wiring for electrically connecting the first display elements to each other,

the first connection wiring overlaps at least a portion of the second pixel electrode and the third pixel electrode.

2. The display device of claim 1, wherein the display device comprises a display device,

the display device further includes:

a second connection wiring so that the second display elements are electrically connected to each other,

the second connection wiring overlaps at least a portion of the first pixel electrode and the third pixel electrode.

3. The display device of claim 2, wherein the display device comprises a display device,

the display device further includes:

a third connection wiring so that the third display elements are electrically connected to each other,

the third connection wiring overlaps at least a part of the first pixel electrode and the second pixel electrode.

4. A display device according to claim 3, wherein,

the first connection wiring, the second connection wiring, and the third connection wiring have an overall shape of an x-shape in plan view.

5. A display device according to claim 3, wherein,

at least a part of the first connection wirings and at least a part of the second connection wirings are parallel to each other.

6. A display device according to claim 3, wherein,

at least a part of the first connection wirings and at least a part of the third connection wirings are parallel to each other.

7. A display device according to claim 3, wherein,

the first connection wiring, the second connection wiring, and the third connection wiring are arranged in the same layer.

8. A display device according to claim 3, wherein,

the first connection wiring electrically connects the two first display elements, and the second connection wiring electrically connects the two second display elements.

9. The display device of claim 8, wherein the display device comprises a display device,

the third connection wiring electrically connects two of the third display elements, or the third connection wiring electrically connects four of the third display elements.

10. The display device of claim 1, wherein the display device comprises a display device,

the display device further includes:

a fourth display element disposed on the second region and including a fourth pixel electrode;

a fifth display element disposed on the second region and including a fifth pixel electrode;

A sixth display element disposed on the second region and including a sixth pixel electrode; and

and fourth connection wirings for electrically connecting the fourth display elements to each other.