CN220323802U - Trimming circuit and semiconductor device - Google Patents
Trimming circuit and semiconductor device Download PDFInfo
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- CN220323802U CN220323802U CN202322168984.1U CN202322168984U CN220323802U CN 220323802 U CN220323802 U CN 220323802U CN 202322168984 U CN202322168984 U CN 202322168984U CN 220323802 U CN220323802 U CN 220323802U
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- 238000009966 trimming Methods 0.000 title claims abstract description 32
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 230000001105 regulatory effect Effects 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 13
- 238000012986 modification Methods 0.000 description 5
- 230000004048 modification Effects 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000001276 controlling effect Effects 0.000 description 1
- 230000005662 electromechanics Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000002123 temporal effect Effects 0.000 description 1
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Abstract
The embodiment of the application provides a trimming circuit and a semiconductor element, wherein the trimming circuit comprises: the decoding circuit generates an output signal according to the fusing signal and the selection signal, and the output signal is used for determining the fuse to be fused; the decoding circuit includes: a switch control circuit that outputs a switch control signal; a selection circuit that generates a selection signal, the selection circuit being connected to the switch control circuit at the first terminal and receiving the switch control signal, the selection circuit outputting the generated selection signal through the second terminal; and an output circuit that generates an output signal; the selection circuit is provided with a first transistor, a drain electrode of the first transistor is connected with a first terminal, a grid electrode of the first transistor receives an enabling control signal, a source electrode of the first transistor is connected with a plurality of transistors connected in series, and the plurality of transistors receive a preset clock signal. This reduces the size of the decoding circuit and prevents the chip size of the semiconductor integrated circuit from increasing.
Description
Technical Field
The present application relates to the field of electromechanics, and in particular, to a trimming circuit and a semiconductor device.
Background
In a semiconductor device, variations in circuit characteristics occur due to variations in manufacturing steps and variations in circuit components. In order to reduce variations in circuit characteristics, when high accuracy is required, fine adjustment of the resistance value is performed by using a fuse in which a large current cut portion is connected in parallel with a resistor in an electrical characteristic inspection stage of a manufacturing process.
It should be noted that the foregoing description of the background art is only for the purpose of facilitating a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background section of the present application.
Disclosure of Invention
The inventors found that: when the trimming circuit selects the cut fuse, the target fuse is selected in the decoding circuit, but the decoding circuit is performed by a logic circuit of CMOS. However, in the related art, in order to improve the accuracy of trimming, the number of fuses to be selected in the decoding circuit needs to be increased, which leads to an increase in the scale of the logic circuit and, in turn, to an increase in the chip size of the semiconductor integrated circuit.
In view of the problems noted in the background art, embodiments of the present application provide a trimming circuit and a semiconductor device.
According to a first aspect of embodiments of the present application, there is provided a trimming circuit comprising:
the decoding circuit generates an output signal according to the fusing signal and the selection signal, wherein the output signal is used for determining the fuse to be fused;
the decoding circuit includes:
a switch control circuit that outputs a switch control signal;
a selection circuit that generates the selection signal, the selection circuit being connected to the switch control circuit at a first terminal and receiving the switch control signal, the selection circuit outputting the generated selection signal through a second terminal; and
an output circuit that generates the output signal, the output circuit being connected to the selection circuit at the second terminal and receiving the selection signal; the output circuit further has a third terminal that receives the fusing signal, and a fourth terminal that outputs the generated output signal to the fuse;
the selection circuit is provided with a first transistor, a drain electrode of the first transistor is connected with the first terminal, a grid electrode of the first transistor receives an enabling control signal, a source electrode of the first transistor is connected with a plurality of transistors connected in series, and the plurality of transistors receive a preset clock signal.
According to a second aspect of the embodiments of the present application, the switch control circuit includes two P-type MOS transistors, wherein sources of the two P-type MOS transistors are connected to a regulated power supply, a drain of one of the two P-type MOS transistors is connected to the first terminal, and another of the two P-type MOS transistors is connected to the second terminal.
According to a third aspect of the embodiments of the present application, the switch control circuit includes two resistors, wherein one end of the two resistors is connected to a regulated power supply, the other end of one of the two resistors is connected to the first terminal, and the other end of the other one of the two resistors is connected to the second terminal.
According to a fourth aspect of embodiments of the present application, the number of the plurality of transistors is N, where N is an integer greater than 1.
According to a fifth aspect of embodiments of the present application, the plurality of transistors connected in series further has a ground terminal.
According to a sixth aspect of the embodiments of the present application, the plurality of transistors are N-type MOS transistors.
According to a seventh aspect of the embodiments of the present application, when the output signal is an ON signal, the fuse is controlled to blow, otherwise, the fuse is controlled not to blow.
According to an eighth aspect of embodiments of the present application, there is provided a semiconductor element comprising the trimming circuit according to any one of the first to eighth aspects of embodiments of the present application.
One of the beneficial effects of the embodiment of the application is that: in the trimming circuit according to the embodiment of the present utility model, the scale of the decoding circuit can be reduced by connecting the MOS devices in series, and thus, even when the accuracy requirement for trimming is high, the chip size of the semiconductor integrated circuit can be prevented from increasing.
Specific embodiments of the present application are disclosed in detail below with reference to the following description and drawings, indicating the manner in which the principles of the present application may be employed. It should be understood that the embodiments of the present application are not limited in scope thereby. The embodiments of the present application include many variations, modifications and equivalents within the scope of the terms of the appended claims.
Features that are described and/or illustrated with respect to one embodiment may be used in the same way or in a similar way in one or more other embodiments in combination with or instead of the features of the other embodiments.
It should be emphasized that the term "comprises/comprising" when used herein is taken to specify the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps or components.
Drawings
Elements and features described in one drawing or one implementation of an embodiment of the present application may be combined with elements and features shown in one or more other drawings or implementations. Furthermore, in the drawings, like reference numerals designate corresponding parts throughout the several views, and may be used to designate corresponding parts as used in more than one embodiment.
The accompanying drawings, which are included to provide a further understanding of the embodiments of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the principles of the application. It is apparent that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art. In the drawings:
FIG. 1 is a schematic diagram of a decoding circuit in a trimming circuit according to an embodiment of the present application;
FIG. 2 is another schematic diagram of a decoding circuit in the trimming circuit according to the embodiments of the present application;
FIG. 3 is a schematic diagram of a selection circuit in a decoding circuit according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an output circuit in a decoding circuit according to an embodiment of the present application;
FIG. 5 is another schematic diagram of a decoding circuit in the trimming circuit according to the embodiment of the present application
FIG. 6 is a schematic diagram of a prior art fuse-selective decoding circuit;
fig. 7 is a schematic diagram showing the configuration of logic circuit elements used in a decoding circuit according to the related art.
Detailed Description
The foregoing and other features of the present application will become apparent from the following description, with reference to the accompanying drawings. In the specification and drawings, there have been specifically disclosed specific embodiments of the present application which are indicative of some of the embodiments in which the principles of the present application may be employed, it being understood that the present application is not limited to the described embodiments, but, on the contrary, the present application includes all modifications, variations and equivalents falling within the scope of the appended claims. Various embodiments of the present application are described below with reference to the accompanying drawings. These embodiments are merely exemplary and are not limiting of the present application.
In the embodiments of the present application, the terms "first," "second," "upper," "lower," and the like are used to distinguish between different elements from their names, but do not denote a spatial arrangement or temporal order of the elements, which should not be limited by the terms. The term "and/or" includes any and all combinations of one or more of the associated listed terms. The terms "comprises," "comprising," "including," "having," and the like, are intended to reference the presence of stated features, elements, components, or groups of components, but do not preclude the presence or addition of one or more other features, elements, components, or groups of components.
In the embodiments of the present application, the singular forms "a," an, "and" the "include plural referents and should be construed broadly to mean" one "or" one type "and not limited to" one "or" another; furthermore, the term "comprising" is to be interpreted as including both the singular and the plural, unless the context clearly dictates otherwise. Furthermore, the term "according to" should be understood as "at least partially according to … …", and the term "based on" should be understood as "based at least partially on … …", unless the context clearly indicates otherwise.
Embodiments of the present application are described below with reference to the accompanying drawings.
The embodiment of the application provides a fine tuning circuit, which comprises: fig. 1 and 2 are two schematic diagrams of a decoding circuit 100 in the trimming circuit according to the embodiment of the present application, and as shown in fig. 1, the decoding circuit 100 includes: a switch control circuit 1, a selection circuit 2, and an output circuit 3.
As shown in fig. 1 and 2, the switch control circuit 1 is connected with the selection circuit 2 at the first terminal 10, the selection circuit 2 is connected with the output circuit 3 at the second terminal 20, further, the fusing signal 101 is connected to the output circuit 3 through the third segment 30, and the output circuit 3 outputs the output signal 102 through the 4 th terminal 40.
As shown in fig. 2, the switch control circuit 1 has two P-type MOS transistors, wherein sources of the two P-type MOS transistors 11-1 and 12-1 are connected to a regulated power supply, the regulated current can provide current for the decoding circuit, a drain of one of the two P-type MOS transistors 11-1 is connected to the first terminal 10, and a drain of the other of the two P-type MOS transistors 12-1 is connected to the second terminal 20.
In the above embodiment, the switch control circuit has two P-type MOS transistors, but this arrangement is merely an example, and fig. 5 is another schematic diagram of the decoding circuit in the trimming circuit according to the embodiment of the present application, as shown in fig. 5, the switch control circuit 1 may further include two resistors 11-2 and 12-2, one end of the two resistors 11-2 and 12-2 is connected to the regulated power supply, the other end of one of the two resistors 11-2 is connected to the first terminal 10, and the other end of the other one of the two resistors 12-2 is connected to the second terminal 20.
In the above embodiment, as shown in fig. 2, the switch control circuit 1 may further include a third P-type MOS transistor 13 and a transformer 14, and the switch control circuit provided in the embodiment of the present application may control the output of the voltage by changing the conduction degree of the P-type MOS transistor. According to the related art, the switch control circuit provided in the embodiments of the present application can also have other elements and structures, which the present application does not limit.
With the above-described configuration as shown in fig. 1 and 2, the selection circuit 2 can receive a switch control signal outputted from the switch control circuit 1, which can control the conduction of the selection circuit 2, and the output circuit 3 can receive a selection signal outputted from the selection circuit 2, and the output circuit 3 generates an output signal 102 based on the fusing signal 101 and the selection signal 26, the output signal 102 being used to determine the fuse to be fused.
FIG. 3 is a schematic diagram of a selection circuit 2 of a decoding circuit according to an embodiment of the present application; as shown in fig. 3, the selection circuit 2 includes: a first transistor 201 and a plurality of transistors 202 connected in series; the drain of the first transistor 201 is connected to the first terminal 10, thereby receiving the switch control signal outputted from the switch control circuit 1, the gate of the first transistor 201 is capable of receiving the enable control signal 21, the enable control signal 21 is capable of controlling the turn-on of the plurality of transistors 202, the source of the first transistor 201 is connected to the plurality of transistors 202 connected in series, the plurality of transistors 202 are capable of receiving the predetermined clock signals 22, 23, 24, 25, respectively, one end of the plurality of transistors 202 connected in series is connected to the first transistor 201, and one end not connected to the first transistor 201 is a ground.
Fig. 4 is a schematic diagram of the output circuit 3 in the decoding circuit of the embodiment of the present application; as shown in fig. 4, the output circuit 3 can receive the selection signal 26 and the fusing signal 101 output from the selection circuit 2, and generate an output signal 102 according to the fusing signal 101 and the selection signal 26, and the output signal 102 can control whether the fuse is fused.
In the above embodiment, the number of the plurality of transistors 202 is exemplified by 4, which means that the fuse to be cut is selected using 4 bits of data, and the 4 bits of data correspond to the input clock signals 22, 23, 24, 25, respectively, and therefore, the number of the plurality of transistors may be an integer of 2, 3, 4, or the like, which is 1 or more.
Note that in this application, as described above, when the decoding circuit uses 4 bits of data to select a fuse that needs to be cut, there are 16 fuse transistors, each connected to one decoding circuit. The clock signals 22, 23, 24, and 25 input to these decoding circuits are combined in such a manner that 16 kinds of these signals, 0000, 0001, 0010, 0011 … … 1110, and 1111, are input to each decoding circuit 100 in the trimming circuit, and the output signal of the decoding circuit connected to the fuse transistor is turned ON in accordance with the signals, so that the fuse is blown.
As shown in fig. 1 and 2, with the structure of the decoding circuit provided in the embodiment of the present application, 11 elements are used for the decoding circuit when one fuse is selected. In contrast, FIG. 6 is a schematic diagram of a prior art fuse-selected decoding circuit; FIG. 7 is a schematic diagram of the logic circuit components employed in the prior art decoding circuit; as shown in fig. 7, in the prior art, the fuses are controlled using a decoding circuit composed of 6 logic circuits, one of which has an internal configuration as shown in fig. 7, that is, in the prior art, 36 elements are used for the decoding circuit when one fuse is selected.
Therefore, by the structure of connecting the plurality of transistors 202 in series provided in the embodiment of the present application, the scale of the decoding circuit can be greatly reduced without affecting the accuracy thereof.
In the above embodiment, the plurality of transistors 202 are all N-type MOS transistors, which is not limited in this application.
With the above-described embodiments of the present application, by using a structure in which a plurality of transistors are connected in series in a decoding circuit, the number of elements used in the circuit can be greatly reduced without affecting the trimming accuracy of the trimming circuit, thereby reducing the size of the decoding circuit and further preventing an increase in the chip size of the semiconductor integrated circuit.
The embodiment of the present application provides a semiconductor device, in which the trimming circuit described in the above embodiment is provided.
Since the structure of the trimming circuit has been described in detail in the above embodiments, the contents thereof are incorporated herein and the description thereof is omitted.
In the present embodiment, the semiconductor element may be any semiconductor element provided with a trimming circuit, and may be, for example, a fuse or the like.
The present application has been described in connection with specific embodiments, but it should be apparent to those skilled in the art that these descriptions are intended to be illustrative and not limiting. Various modifications and alterations of this application may occur to those skilled in the art in light of the spirit and principles of this application, and are to be seen as within the scope of this application.
Preferred embodiments of the present application are described above with reference to the accompanying drawings. The many features and advantages of the embodiments are apparent from the detailed specification, and thus, it is intended by the appended claims to cover all such features and advantages of the embodiments which fall within the true spirit and scope thereof. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the embodiments of the present application to the exact construction and operation illustrated and described, and accordingly, all suitable modifications and equivalents may be resorted to, falling within the scope thereof.
Claims (8)
1. A trimming circuit, the trimming circuit comprising:
the decoding circuit generates an output signal according to the fusing signal and the selection signal, wherein the output signal is used for determining the fuse to be fused;
the decoding circuit includes:
a switch control circuit that outputs a switch control signal;
a selection circuit that generates the selection signal, the selection circuit being connected to the switch control circuit at a first terminal and receiving the switch control signal, the selection circuit outputting the generated selection signal through a second terminal; and
an output circuit that generates the output signal, the output circuit being connected to the selection circuit at the second terminal and receiving the selection signal; the output circuit further has a third terminal that receives the fusing signal, and a fourth terminal that outputs the generated output signal to the fuse;
the selection circuit is provided with a first transistor, a drain electrode of the first transistor is connected with the first terminal, a grid electrode of the first transistor receives an enabling control signal, a source electrode of the first transistor is connected with a plurality of transistors connected in series, and the plurality of transistors receive a preset clock signal.
2. The trimming circuit of claim 1, wherein the switch control circuit comprises two P-type MOS transistors, wherein sources of the two P-type MOS transistors are connected to a regulated power supply, a drain of one of the two P-type MOS transistors is connected to the first terminal, and another of the two P-type MOS transistors is connected to the second terminal.
3. The trimming circuit according to claim 1, wherein the switch control circuit comprises two resistors, wherein one end of the two resistors is connected to a regulated power supply, the other end of one of the two resistors is connected to the first terminal, and the other end of the other of the two resistors is connected to the second terminal.
4. The trimming circuit of claim 1, wherein the number of the plurality of transistors is N, wherein N is an integer greater than 1.
5. The trimming circuit of claim 1, wherein the plurality of transistors connected in series further have a ground terminal.
6. The trimming circuit of claim 1, wherein the plurality of transistors are N-type MOS transistors.
7. The trimming circuit according to anyone of claims 1-6, wherein the fuse is controlled to blow when the output signal is an ON signal, and wherein the fuse is controlled not to blow otherwise.
8. A semiconductor element, characterized in that the semiconductor element comprises a trimming circuit according to any one of claims 1 to 7.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322168984.1U CN220323802U (en) | 2023-08-11 | 2023-08-11 | Trimming circuit and semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322168984.1U CN220323802U (en) | 2023-08-11 | 2023-08-11 | Trimming circuit and semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN220323802U true CN220323802U (en) | 2024-01-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202322168984.1U Active CN220323802U (en) | 2023-08-11 | 2023-08-11 | Trimming circuit and semiconductor device |
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| CN (1) | CN220323802U (en) |
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- 2023-08-11 CN CN202322168984.1U patent/CN220323802U/en active Active
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