CN220306257U - Array substrate, display panel and display device - Google Patents
Array substrate, display panel and display device Download PDFInfo
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- CN220306257U CN220306257U CN202321477461.9U CN202321477461U CN220306257U CN 220306257 U CN220306257 U CN 220306257U CN 202321477461 U CN202321477461 U CN 202321477461U CN 220306257 U CN220306257 U CN 220306257U
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- 239000000758 substrate Substances 0.000 title claims abstract description 59
- 239000010410 layer Substances 0.000 claims description 267
- 239000002131 composite material Substances 0.000 claims description 7
- 239000002356 single layer Substances 0.000 claims description 4
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 3
- 230000000694 effects Effects 0.000 abstract description 6
- 229910000476 molybdenum oxide Inorganic materials 0.000 description 7
- 238000010586 diagram Methods 0.000 description 6
- 238000002161 passivation Methods 0.000 description 3
- 238000002310 reflectometry Methods 0.000 description 3
- 229910020286 SiOxNy Inorganic materials 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000008033 biological extinction Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000003475 lamination Methods 0.000 description 1
- 230000031700 light absorption Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- PQQKPALAQIIWST-UHFFFAOYSA-N oxomolybdenum Chemical compound [Mo]=O PQQKPALAQIIWST-UHFFFAOYSA-N 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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Abstract
The application discloses an array substrate, a display panel and a display device, wherein the array substrate comprises a grid layer, a grid insulating layer and a data line layer which are sequentially stacked from a light emitting surface of the array substrate; the light-emitting diode further comprises a first anti-reflection layer and a second anti-reflection layer which are stacked; in the orthographic projection of the light emitting surface, the grid pattern of the grid layer is positioned in the antireflection pattern of the first antireflection layer, and the data line pattern of the data line layer is positioned in the antireflection pattern of the second antireflection layer; the first anti-reflection layer is positioned on one side of the grid layer close to the light-emitting surface, and the second anti-reflection layer is positioned on one side of the data line layer close to the light-emitting surface. According to the scheme, the reflection of the array substrate to the ambient light is reduced, and the display effect is improved.
Description
Technical Field
The utility model relates to the technical field of display, in particular to an array substrate, a display panel and a display device.
Background
For the substrate of the array substrate as the light emitting surface of the display panel, as the metal layer in the thin film transistor on the array substrate is not covered by the shading layer, the reflectivity of the display panel to ambient light is obviously increased, and the display effect is deteriorated.
Disclosure of Invention
The application provides an array substrate, a display panel and a display device, which are at least used for reducing reflection of the array substrate to ambient light so as to improve display effect.
In a first aspect, the present utility model provides an array substrate, including a gate layer, a gate insulating layer, and a data line layer sequentially stacked from a light-emitting surface of the array substrate; the light-emitting diode further comprises a first anti-reflection layer and a second anti-reflection layer which are stacked;
in the orthographic projection of the light emitting surface, the grid pattern of the grid layer is positioned in the antireflection pattern of the first antireflection layer, and the data line pattern of the data line layer is positioned in the antireflection pattern of the second antireflection layer;
the first anti-reflection layer is positioned on one side of the grid layer close to the light-emitting surface, and the second anti-reflection layer is positioned on one side of the data line layer close to the light-emitting surface.
As an achievable, the second anti-reflection layer is located between the data line layer and the gate layer.
As an implementation manner, the first anti-reflection layer and the second anti-reflection layer are both located at one side of the gate layer, which is close to the light emitting surface.
As an achievable, the second anti-reflection layer is located between the first anti-reflection layer and the gate layer; or, the first anti-reflection layer is located between the second anti-reflection layer and the gate layer.
As an achievable form, the first antireflection layer and the second antireflection layer are each any one of a single-layer structure and a composite-layer structure.
As an achievable way, the composite layer structure comprises a first sub-layer and a second sub-layer which are stacked; the first sub-layer is at least any one of a MoOx layer, a MoNb layer and a MoNbOx layer; the second sub-layer is a SiN layer and SiO 2 At least any one of the layer and the SiOxNy layer.
As an achievable form, the gate layer is a Mo/Al/Mo layer or an Al/Mo layer.
As an implementation manner, the light emergent side of the array substrate is provided with an antireflection polarizer.
In a second aspect, the present utility model provides a display panel, including the above array substrate.
In a third aspect, the present utility model provides a display device, including the above array substrate or the above display panel.
According to the scheme, the first anti-reflection layer and the second anti-reflection layer are arranged; the first anti-reflection layer is positioned on one side of the grid layer, which is close to the light-emitting surface, and the second anti-reflection layer is positioned on one side of the data line layer, which is close to the light-emitting surface; that is, the first anti-reflection layer is used for shielding the gate layer, the second anti-reflection layer is used for shielding the data line layer, so that the ambient light cannot irradiate the gate layer and the data line layer and is reflected by the gate layer and the data line layer, and therefore, the reflection of the array substrate on the ambient light is reduced, namely, the interference of the ambient light reflection on display is reduced, and the display effect is improved.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:
fig. 1 is a schematic structural diagram of an array substrate according to an embodiment of the present utility model;
FIG. 2 is a schematic structural diagram of an array substrate according to another embodiment of the present utility model;
FIG. 3 is a schematic structural diagram of an array substrate according to another embodiment of the present utility model;
FIG. 4 is a schematic structural diagram of an array substrate according to another embodiment of the present utility model;
FIG. 5 is a schematic structural diagram of an array substrate according to another embodiment of the present utility model;
fig. 6 is a schematic structural diagram of an array substrate according to another embodiment of the present utility model.
Detailed Description
The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting of the utility model. It should be noted that, for convenience of description, only the portions related to the utility model are shown in the drawings.
It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
As known to those skilled in the art, the array substrate generally includes a substrate 2, a buffer layer, an active layer, a first gate insulating layer, a gate layer 6, a second gate insulating layer, and a data line layer 8, which are sequentially stacked. Further, the layers may be directly connected to each other, and other layers may be further provided between the adjacent layers.
The figures referred to in the embodiments herein below do not all show the entire layer structure of the array substrate, but only mainly show the layer structure directly related to the point of the present utility model, and other layer structures are not shown in the figures.
Referring to at least fig. 1, an array substrate according to an embodiment of the present utility model includes a gate layer 6, a gate insulating layer 4, and a data line layer 8 sequentially stacked from a light-emitting surface 1 of the array substrate; further comprising a first anti-reflection layer 3 and a second anti-reflection layer 7 arranged in a stack.
The light-emitting surface 1 is understood to be a surface facing a viewer, and the viewer can view a screen displayed on a display panel using the array substrate through the light-emitting surface 1.
The sequential stacking arrangement is used for illustrating that the layers are stacked in a certain sequence, and adjacent layers are not explicitly or implicitly connected; other layer structures may be provided between any two layers sequentially stacked as needed.
In the front projection of the light-emitting surface 1, the gate pattern of the gate layer 6 is located in the anti-reflection pattern of the first anti-reflection layer 3, and the data line pattern of the data line layer 8 is located in the anti-reflection pattern of the second anti-reflection layer 7. That is, the anti-reflection pattern of the first anti-reflection layer 3 is greater than or equal to the gate pattern, and the anti-reflection pattern of the second anti-reflection layer 7 is greater than or equal to the data line pattern, so as to fully shield the gate pattern and the data line pattern, and prevent the gate pattern and the data line pattern from reflecting ambient light.
Preferably, the anti-reflection pattern of the first anti-reflection layer 3 is slightly larger than the gate pattern, and the anti-reflection pattern of the second anti-reflection layer 7 is slightly larger than the data line pattern.
The first anti-reflection layer 3 and the gate layer 6 may be patterned using the same mask, and the second anti-reflection layer 7 and the data line layer 8 may be patterned using the same mask. The anti-reflection pattern of the first anti-reflection layer 3 is slightly larger than the grid pattern, and the anti-reflection pattern of the second anti-reflection layer 7 is slightly larger than the data line pattern through the technological parameters such as exposure, etching and the like in the patterning technology.
Disposing the first antireflection layer 3 on a side of the gate layer 6 near the light-emitting surface 1, and disposing the second antireflection layer 7 on a side of the data line layer 8 near the light-emitting surface 1; after entering the array substrate through the light emitting surface 1, the ambient light irradiates the first anti-reflection layer 3 and the second anti-reflection layer 7, and is blocked by the first anti-reflection layer 3 and the second anti-reflection layer 7, so that the ambient light cannot continue to propagate to the gate electrode layer 6 and the data line layer 8.
In general, the above-described scheme is implemented by providing the first antireflection layer 3 and the second antireflection layer 7; the first anti-reflection layer 3 is positioned on one side of the grid layer 6 close to the light-emitting surface 1, and the second anti-reflection layer 7 is positioned on one side of the data line layer 8 close to the light-emitting surface 1; that is, the first anti-reflection layer 3 is used for shielding the gate layer 6, the second anti-reflection layer 7 is used for shielding the data line layer 8, so that the ambient light cannot irradiate the gate layer 6 and the data line layer 8 and is reflected by the gate layer 6 and the data line layer 8, and therefore, the reflection of the array substrate to the ambient light is reduced, that is, the interference of the ambient light reflection to display is reduced, and the display effect is improved.
The first antireflection layer 3 is only required to be located on the side of the gate layer 6 near the light-emitting surface 1, and the second antireflection layer 7 is only required to be located on the side of the data line layer 8 near the light-emitting surface 1, and the specific layer of the first antireflection layer 3 and the second antireflection layer 7, and the lamination relationship between the first antireflection layer 3 and the second antireflection layer 7, may be determined according to practical situations, and the following specific examples of the setting positions of the first antireflection layer 3 and the second antireflection layer 7 are given below:
referring also to fig. 1, in this example, the array substrate exhibits a layer structure in which a first anti-reflection layer 3 is disposed on a substrate 2, a gate layer 6 is disposed on the first anti-reflection layer 3, a gate insulating layer 4 is disposed on the gate layer 6, a second anti-reflection layer 7 is disposed on the gate insulating layer 4, a data line layer 8 is disposed on the second anti-reflection layer 7, and a passivation layer 5 is disposed on the data line layer 8; that is, the second anti-reflection layer 7 is located between the data line layer 8 and the gate layer 6.
In fig. 1, the ambient light enters the array substrate from bottom to top.
With the above structure, the reflectance was reduced to 6.49% from 9% -10% when the first antireflection layer 3 and the second antireflection layer 7 were not made, as tested.
Referring also to fig. 2, in this example, the array substrate exhibits a layer structure in which a first anti-reflection layer 3 is provided on a substrate 2, a first gate insulating layer 41 is provided on the first anti-reflection layer 3, a second anti-reflection layer 7 is provided on the first gate insulating layer 41, a second gate insulating layer 42 is provided on the second anti-reflection layer 7, a gate layer 6 is provided on the second gate insulating layer 42, a third gate insulating layer 43 is provided on the gate layer 6, a data line layer 8 is provided on the third gate insulating layer 43, and a passivation layer 5 is provided on the data line layer 8; that is, the first anti-reflection layer 3 and the second anti-reflection layer 7 are both located on the side of the gate layer 6 close to the light-emitting surface 1.
In the above structure, the first gate insulating layer 41 and the second gate insulating layer 42 can achieve the effect of level separation, and the first antireflection layer 3 and the second antireflection layer 7 are correspondingly flattened, so that the flatness between levels is ensured.
With the above structure, the reflectance was reduced to 5.13% from 9% -10% when the first antireflection layer 3 and the second antireflection layer 7 were not made, as tested.
Referring also to fig. 3, in this example, the array substrate exhibits a layer structure in which the second anti-reflection layer 7 is disposed on the substrate 2, the first gate insulating layer 41 is disposed on the second anti-reflection layer 7, the first anti-reflection layer 3 is disposed on the first gate insulating layer 41, the second gate insulating layer 42 is disposed on the first anti-reflection layer 3, the gate layer 6 is disposed on the second gate insulating layer 42, the third gate insulating layer 43 is disposed on the gate layer 6, the data line layer 8 is disposed on the third gate insulating layer 43, and the passivation layer 5 is disposed on the data line layer 8; that is, the first anti-reflection layer 3 and the second anti-reflection layer 7 are both located on the side of the gate layer 6 close to the light-emitting surface 1.
As an achievable form, the first antireflection layer 3 and the second antireflection layer 7 are each any one of a single-layer structure and a composite-layer structure.
For example, but not limited to, the first antireflection layer 3 and the second antireflection layer 7 are respectively in a single-layer structure, and the materials used for the first antireflection layer 3 and the second antireflection layer 7 are all metal oxides, such as molybdenum oxide (MoOx), etc., so that the MoOx has low reflectivity, large absorption of light (such as large extinction coefficient) and can better play a role in antireflection.
As an achievable way, the composite layer structure comprises a first sub-layer and a second sub-layer which are stacked; the first sub-layer is at least any one of a MoOx layer, a MoNb layer and a MoNbOx layer; the second sub-layer is a SiN layer and SiO 2 At least any one of the layer and the SiOxNy layer.
For example, but not limited to, the first anti-reflection layer 3 and the second anti-reflection layer 7 which adopt the composite layer structure may be a four-layer composite layer structure of SiN layer/MoOx layer/SiN layer/MoOx layer, but of course, other layers and composite layer structures in other layer combinations are also possible in other examples.
As an achievable form, the gate layer 6 is a Mo/Al/Mo layer or an Al/Mo layer.
As an implementation manner, at least referring to any one of fig. 4 to 6, the light emitting side of the array substrate is provided with an antireflection polarizer 9.
That is, one side of the light emitting surface 1 of the array substrate is provided with the antireflection polarizer 9.
By simultaneously arranging the antireflection polarizer 9 and the first antireflection layer 3 and the second antireflection layer 7, the reflectivity is reduced to 1.65% from 9% -10% when the first antireflection layer 3 and the second antireflection layer 7 are not made, through testing.
In a second aspect, the present utility model provides a display panel, including the above array substrate.
For example, but not limited to, the display panel may be provided with a color film substrate on a side opposite to the light emitting surface 1 of the array substrate, and a liquid crystal layer is disposed between the color film substrate and the array substrate.
In a third aspect, the present utility model provides a display device, including the above array substrate or the above display panel.
The display device is, for example but not limited to, a desktop computer, a tablet computer, a notebook computer, a mobile phone, a PDA (PersoMal Digital AssistaMt; a palm top computer), a GPS (Global PositioMiMg System; global positioning system), a vehicle-mounted display, a projection display, a video camera, a digital camera, an electronic watch, a calculator, an electronic instrument, an instrument, a liquid crystal panel, a television, a display, a digital photo frame, a navigator, and any product or component having a display function, and can be applied to products or components of public display, phantom display, and the like.
It is to be understood that the above references to the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., are for convenience in describing the present utility model and simplifying the description only, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the present utility model. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present utility model, unless otherwise indicated, the meaning of "a plurality" is two or more.
The foregoing description is only of the preferred embodiments of the present application and is presented as a description of the principles of the technology being utilized. It will be appreciated by persons skilled in the art that the scope of the utility model referred to in this application is not limited to the specific combinations of features described above, but also covers other technical solutions which may be formed by any combination of the features described above or their equivalents without departing from the inventive concept. Such as the above-described features and technical features having similar functions (but not limited to) disclosed in the present application are replaced with each other.
Claims (10)
1. An array substrate comprises a grid layer, a grid insulating layer and a data line layer which are sequentially stacked from a light-emitting surface of the array substrate; the light-emitting diode is characterized by further comprising a first anti-reflection layer and a second anti-reflection layer which are stacked;
in the orthographic projection of the light emitting surface, the grid pattern of the grid layer is positioned in the antireflection pattern of the first antireflection layer, and the data line pattern of the data line layer is positioned in the antireflection pattern of the second antireflection layer;
the first anti-reflection layer is positioned on one side of the grid layer close to the light-emitting surface, and the second anti-reflection layer is positioned on one side of the data line layer close to the light-emitting surface.
2. The array substrate of claim 1, wherein the second anti-reflection layer is located between the data line layer and the gate layer.
3. The array substrate of claim 1, wherein the first anti-reflection layer and the second anti-reflection layer are both positioned on a side of the gate layer near the light-emitting surface.
4. The array substrate of claim 3, wherein the second anti-reflection layer is located between the first anti-reflection layer and the gate layer; or, the first anti-reflection layer is located between the second anti-reflection layer and the gate layer.
5. The array substrate of any one of claims 1 to 4, wherein the first and second anti-reflection layers are any one of a single layer structure and a composite layer structure, respectively.
6. The array substrate of claim 5, wherein the composite layer structure comprises a first sub-layer and a second sub-layer stacked; the first sublayer is MoO x Layer, monb layer and Monbo x At least any one of the layers; the second sub-layer is a SiN layer and SiO 2 Layer and SiO x N y At least any one of the layers.
7. The array substrate of claim 6, wherein the gate layer is a Mo/Al/Mo layer or an Al/Mo layer.
8. The array substrate according to any one of claims 1 to 4, wherein an antireflection polarizer is provided on a light-emitting side of the array substrate.
9. A display panel comprising the array substrate of any one of claims 1-8.
10. A display device comprising the array substrate of any one of claims 1 to 8 or the display panel of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321477461.9U CN220306257U (en) | 2023-06-09 | 2023-06-09 | Array substrate, display panel and display device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202321477461.9U CN220306257U (en) | 2023-06-09 | 2023-06-09 | Array substrate, display panel and display device |
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| CN220306257U true CN220306257U (en) | 2024-01-05 |
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| CN202321477461.9U Active CN220306257U (en) | 2023-06-09 | 2023-06-09 | Array substrate, display panel and display device |
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