CN220305704U

CN220305704U - Single-stage PFC circuit of varistor voltage regulating circuit and high-power quick charging charger

Info

Publication number: CN220305704U
Application number: CN202322138573.8U
Authority: CN
Inventors: 许锡亨
Original assignee: Shenzhen Yuhao Electronic Technology Co ltd
Current assignee: Shenzhen Yuhao Electronic Technology Co ltd
Priority date: 2023-08-09
Filing date: 2023-08-09
Publication date: 2024-01-05
Anticipated expiration: 2033-08-09

Abstract

The utility model relates to a variable resistance voltage-regulating circuit which comprises three parallel lower bias resistors, wherein one ends of the three lower bias resistors are connected with a signal output end, the other end of a first lower bias resistor is connected with a drain electrode of a first MOS tube, and a grid electrode of the first MOS tube is connected with a first charging capacitor and a power supply end; the other end of the second lower bias resistor is connected with the drain electrode of the second MOS tube, the grid electrode of the second MOS tube is connected with the second charging capacitor and the third charging capacitor, a voltage stabilizing diode is arranged between the second MOS tube and the third charging capacitor, and one end of the cathode of the voltage stabilizing diode is connected with the third charging capacitor. The variable-resistance voltage-regulating circuit can output three voltage signals comprising intermediate voltage signals according to the connection state between the charger and the load, and can stably regulate the output voltage when the charger is switched between an idle state and a load state, so that the larger voltage drop of the output voltage of the charger is avoided, and the loss to the charger and the electronic equipment is avoided.

Description

Single-stage PFC circuit of varistor voltage regulating circuit and high-power quick charging charger

Technical Field

The utility model relates to the field of charging circuits, in particular to a single-stage PFC circuit of a variable resistance voltage regulating circuit and a high-power quick charging charger.

Background

Power Factor Correction (PFC) technology has become a research hotspot in the field of power electronics. With the increasing strictness of power quality standards, PFC converters are increasingly used in switching power supplies, variable frequency governors, and fluorescent ac electronic ballasts. In recent years, PFC technology has been studied greatly with the development of related art and various level input strategies.

For a 100W high-power quick charging charger, a plurality of charging ports and a quick charging function can be provided for electronic equipment, but when the charger is in no-load or light-load, the plug end of the charger is kept at high-level voltage, so that the problem of high power consumption exists. In order to solve the problem of high power consumption, a voltage regulating circuit is added in a charger circuit, so that the voltage can be regulated down when the charger is in no-load or light-load state, and the voltage can be regulated up when the charger works. For example, when the charger is not connected with the electronic equipment or the electric quantity of the electronic equipment reaches more than 80%, and only low-voltage charging is needed, the output voltage is regulated to 13V; and when the fed electronic equipment is charged quickly, the output voltage is regulated to 26V.

However, in the process of executing the voltage regulation mode, the existing single-stage PFC topological circuit lacks a transition state, and has a larger drop when the voltage is reduced from 26V high voltage to 13V low voltage or increased from 13V low voltage to 26V high voltage, and the service life of the charger and the service life of electronic equipment are influenced.

Therefore, the 100W fast charge mainly uses a two-stage topology circuit of PFC+QR or PFC+LLC, and the two-stage topology circuits have better improvement in efficiency and stability compared with a single-stage PFC topology circuit. However, compared with a single-stage PFC topology, the cost of the two-stage topology circuit is not reduced.

Therefore, how to improve the single-stage PFC circuit structure with low cost, so that the single-stage PFC circuit structure can be suitable for the voltage regulation mode of a 100W high-power fast charging charger, and obtain the same power and performance as those of a two-stage PFC topology circuit, is a technical problem to be solved in the industry.

Disclosure of Invention

The utility model provides a single-stage PFC circuit of a varistor voltage regulating circuit and a high-power quick-charging charger, which aims to solve the problem that the existing single-stage PFC topological circuit has larger voltage difference in the voltage regulating process and causes harm to the charger and electronic equipment.

The technical scheme of the utility model is as follows:

the variable resistance voltage regulating circuit comprises a power supply end and a signal output end, wherein the power supply end is used for acquiring a sampling control signal of a monitoring chip of a charger; the signal output end is used for outputting different voltage signals to a feedback pin of a main control chip of the charger; the device further comprises a first lower bias resistor R27, a second lower bias resistor R40 and a third lower bias resistor R24 which are connected in parallel, wherein one ends of the three lower bias resistors are connected with the signal output end;

the other end of the first lower bias resistor R27 is connected with the drain electrode of the first MOS tube Q7, and the grid electrode of the first MOS tube Q7 is connected with the first charging capacitor C8 and the power supply end; the other end of the second lower bias resistor R40 is connected with the drain electrode of the second MOS tube Q8, the grid electrode of the second MOS tube Q8 is connected with the second charging capacitor C15 and the third charging capacitor C9, a zener diode Z3 is arranged between the second MOS tube Q8 and the third charging capacitor C9, and one end of the cathode of the zener diode is connected with the third charging capacitor C9.

By adopting the above technical scheme, after the first charging capacitor C8 is fully charged, the first MOS transistor Q7 is turned on, and the first lower bias resistor R27 on the communication link of the first MOS transistor Q7 is turned on; when the third charging capacitor C9 and the second charging capacitor C15 are fully charged in sequence, the second MOS transistor Q8 is turned on, and the second lower bias resistor R40 on the communication link of the second MOS transistor Q8 is turned on; when the voltage value of the third charging capacitor C9 is smaller than the conducting voltage of the zener diode Z3, the second charging capacitor C15 and the third charging capacitor C9 are sequentially discharged until the second MOS transistor Q8 is turned off.

According to the utility model of the above scheme, a first diode D10 and a first resistor R36 are connected in parallel between the first charging capacitor C8 and the power supply terminal, the cathode of the first diode D10 is connected to the first charging capacitor C8, the anode of the first diode D10 is connected to the power supply terminal, and a grounding resistor R35 is arranged between the first resistor R36 and the grounding terminal.

By adopting the above technical scheme, the power supply terminal charges the first charging capacitor C8 through the first diode D10, and the first charging capacitor C8 is grounded and discharged through the first resistor R36.

According to the utility model of the above scheme, a second diode D11 and a second resistor R33 are connected in parallel between the connection node of the zener diode Z3 and the third charging capacitor C9 and the power supply end, and the positive electrode of the second diode D11 is connected with the third charging capacitor C9, and the negative electrode of the second diode D11 is grounded through a resistor R35.

By adopting the above technical scheme, the power supply terminal charges the third charging capacitor C9 and the second charging capacitor C15 through the second resistor R33; the second charging capacitor C15 and the third charging capacitor C9 are discharged through the second diode D11.

According to the present utility model of the above scheme, the third lower bias resistor R24 is connected in parallel with the filter capacitor C7.

According to the above scheme, the third lower bias resistor R24, the source electrode of the first MOS transistor Q7, and the source electrode of the second MOS transistor Q8 are all grounded.

According to the present utility model of the above scheme, a third resistor R38 is further disposed between the zener diode Z3 and the second charging capacitor C15.

The utility model also provides a single-stage PFC circuit of the high-power quick-charging charger, which comprises an AC input end, an input rectifying and filtering circuit, a transformer, an output rectifying and filtering circuit and an output end, wherein a main control chip is arranged between the input rectifying and filtering circuit and the transformer, a monitoring chip is arranged at the output end and used for monitoring the connection state of the charger and a load, and the varistor voltage regulating circuit is arranged between the main control chip and the monitoring chip.

According to the utility model of the scheme, the power supply pin of the main control chip is connected with the power end of the variable resistance voltage regulating circuit, an optical coupler switch is arranged between the main control chip and the power end of the variable resistance voltage regulating circuit, and the driving end of the optical coupler switch is connected with the monitoring chip.

Further, a fourth resistor R18 is arranged between the optocoupler switch and the power supply pin of the main control chip.

Further, a fifth resistor R34 is arranged between the optocoupler switch and the monitoring chip.

The utility model according to the scheme has the beneficial effects that:

the variable-resistance voltage-regulating circuit can output three voltage signals comprising intermediate voltage signals according to the connection state between the charger and the load, so that the output voltage of the charger can be regulated stably when the main control chip is switched between the no-load state and the load state, and the variable-resistance voltage-regulating circuit is particularly characterized in that the output end of the charger can output the intermediate voltage value serving as a transitional state between high and low voltages, thereby avoiding the existence of larger voltage drop of the output voltage of the charger and avoiding loss to the charger and electronic equipment.

Drawings

FIG. 1 is a schematic diagram of a varistor voltage regulator circuit according to the present utility model;

FIG. 2 is a schematic diagram of a voltage regulating circuit of a main control chip in a charger circuit;

fig. 3 is a block diagram of a single-stage PFC circuit of a high-power fast-charging charger according to the present utility model;

fig. 4 is a schematic diagram of a charger output Vout;

fig. 5 is a schematic diagram of a single-stage PFC circuit of a high-power fast-charge charger;

FIG. 6 is an enlarged circuit diagram of portion A of FIG. 5;

FIG. 7 is an enlarged circuit diagram of portion B of FIG. 5;

fig. 8 is an enlarged circuit diagram of the portion C in fig. 5.

Detailed Description

For a better understanding of the objects, technical solutions and technical effects of the present utility model, the present utility model will be further explained below with reference to the drawings and examples. It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures. Meanwhile, it is stated that the embodiments described below are only for explaining the present utility model and are not intended to limit the present utility model.

It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or intervening elements may also be present, and when an element is referred to as being "connected" to the other element, it may be directly connected to the other element or intervening elements may also be present.

The direction orientation or positional relationship is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship which is commonly put when the product of the application is used, or the orientation or positional relationship which is commonly understood by those skilled in the art, or the orientation or positional relationship which is commonly put when the product of the application is used, only for convenience of description of the application and simplification of description, and is not intended to indicate or imply that the device or element to be referred must have a specific orientation, be configured and operated in a specific orientation, and therefore should not be construed as limiting the application. The terms "first," "second," "third," and "fourth" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features.

Example 1

As shown in fig. 1, a varistor voltage regulating circuit includes:

and the power supply end is used for acquiring a sampling control signal of the monitoring chip MCU-1 of the charger. The monitoring chip MCU-1 comprises a sampling end and is used for collecting voltage and current information of a plug connector of the charger; the photoelectric conversion device also comprises an optical coupler switch U3. Specifically, the power end is connected with an optocoupler switch U3, and the optocoupler switch U3 is connected with a monitoring chip MCU-1 and a power supply pin LDO-10V of a main control chip, so that 10V voltage can be obtained. According to different states (no load or load) of the plugging end of the charger, which are monitored by the monitoring chip MCU-1, when different levels are output-high level, the optical coupler switch U3 is conducted, and the LDO-10V end inputs 10V voltage to the power end of the voltage regulating circuit; at low level, the opto-coupler switch U3 is turned off, and the voltage is not obtained at the voltage regulating circuit power supply terminal. Depending on whether the connection state of the charger plug terminal outputs the high level or the low level, it is only necessary to understand that: the power supply end of the voltage regulating circuit has a voltage input state when the optocoupler switch is on, and has no power input state when the optocoupler switch is off. In an alternative embodiment, the model of the monitor chip may be selected to be P3712.

The signal output end (Vsen end) is connected with a FeedBack pin (FB, feedBack) of a main control chip of the charger, and outputs different voltage signals to the FeedBack pin (FB pin) of a main control chip (IW 3627) of the high-power quick-charging charger, so that the main control chip can control the voltage change of the output voltage (Vout) of the charger. It should be noted that IW3627 is a conventional single-stage AC/DC Constant Voltage (CV) level input device with high power factor correction function, and is applied to a charger circuit to change an output voltage (Vout), and the voltage regulating principle circuit is as shown in fig. 2, where the output voltage formula is:

vout= (Vsen terminal/R2) × (r2+r1) × (Ns/Na),

the Vsen terminal is a voltage value obtained by the FB pin, ns is the number of turns on the output side of the transformer, na is the number of turns on the input side of the transformer, and thus, the output voltage can be changed by adjusting the resistor R2. The final resistance value of the variable resistance voltage regulating circuit is used as a resistor R2 in a voltage regulating principle circuit.

In this embodiment, the branch where the first lower bias resistor R27, the first charging capacitor C8 and the first MOS transistor Q7 are located is regarded as the first branch of the varistor voltage-regulating circuit; the second lower bias resistor R40, the second charging capacitor C15, the third charging capacitor C9 and the second MOS transistor Q8 are regarded as a second branch of the varistor voltage-regulating circuit. Therefore, the first branch circuit and the second branch circuit are controlled to be conducted, so that the voltage regulating circuit outputs a first voltage value; controlling the first branch to be conducted and the second branch to be closed slowly, so that the voltage regulating circuit outputs a second voltage value; and controlling the first branch and the second branch to be closed, so that the voltage regulating circuit outputs a third voltage value, and the first voltage value, the second voltage value and the third voltage value are sequentially reduced.

In the first branch, a first charging capacitor C8 is disposed at the driving end of the first MOS transistor Q7, and a first lower bias resistor R27 is disposed at the communication link of the first MOS transistor Q7. The concrete connection is as follows: one end of the first lower bias resistor R27 is connected with the signal output end (Vsen end), the other end of the first lower bias resistor R27 is connected with the drain electrode of the first MOS tube Q7, the source electrode of the first MOS tube Q7 is grounded, and the grid electrode of the first MOS tube Q7 is connected with the first charging capacitor C8. The grid of the first MOS tube Q7 and the connection node of the first charging capacitor C8 are also connected with a first diode D10 and a first resistor R36 which are connected in parallel, the cathode of the first diode D10 is connected with the first charging capacitor C8, the anode of the first diode D10 is connected with one side of the output of the opto-coupler switch of the power supply end, and the anode of the first diode D10 is grounded through a grounding resistor R35.

In the second branch, a second lower bias resistor R40, a second charging capacitor C15, a third charging capacitor C9 and a second MOS transistor Q8 are disposed on the driving end of the second MOS transistor Q8, and the second lower bias resistor R40 is disposed on the communication link of the second MOS transistor Q8. The concrete connection is as follows: one end of the second lower bias resistor R40 is connected with the signal output end (Vsen end), the other end of the second lower bias resistor R40 is connected with the drain electrode of the second MOS tube Q8, the source electrode of the second MOS tube Q8 is grounded, the grid electrode of the second MOS tube Q8 is connected with the second charging capacitor C15, the connection node between the grid electrode of the second charging capacitor C15 and the second charging capacitor C15 is also connected with a third resistor R38 and a voltage stabilizing diode Z3, the anode of the voltage stabilizing diode Z3 is connected with the third resistor R38, the cathode of the voltage stabilizing diode Z3 is connected with the third charging capacitor C9, and the other end of the third charging capacitor C9 is grounded. The cathode of the voltage stabilizing diode Z3 is connected with a second diode D11 and a second resistor R33 which are connected in parallel through a connecting node of the third charging capacitor C9, the anode of the second diode D11 is connected with the third charging capacitor C9, the cathode of the second diode D11 is connected with one output side of an opto-coupler switch of a power end, and the cathode of the second diode D11 is grounded through a grounding resistor R35.

In this embodiment, in order to increase the minimum output resistance of the voltage regulating circuit, a third lower bias resistor R24 is provided, and the third lower bias resistor R24 is connected in parallel with the first branch and the second branch. The concrete connection is as follows: one end of the third lower bias resistor R24 is simultaneously connected with the Vsen end and one end of the second lower bias resistor R40, and the other end of the third lower bias resistor R24 is simultaneously connected with the drain electrode of the second MOS tube Q8 and the ground end. The third lower bias resistor is also connected in parallel with a filter capacitor C7 for filtering direct current or low frequency signals at the position.

The varistor voltage regulating circuit structure of the embodiment is as above, and the principle of the varistor voltage regulating circuit structure according to the change resistance value of the plugging state of the charger monitored by the monitoring chip MCU-1 is as follows:

1. when the MCU-1 monitors that the charger is in full load, namely the charger is connected with the electronic equipment in a plugging mode and needs to charge the electronic equipment, the MCU-1 outputs a high level, the optocoupler switch U3 is conducted, and the state of the first branch is: the output voltage end LDO-10V of the main control chip charges the first charging capacitor C8 through the first diode D10 until the driving end of the first MOS tube Q7 reaches the conducting voltage so that the first MOS tube Q7 is conducted, and the first lower bias resistor R27 is connected.

And the state of the second branch at this time is: the LDO-10V charges the third charging capacitor C9 through the second resistor R33 until the cathode end of the zener diode Z3 reaches the conducting voltage, and charges the second charging capacitor C15 through the second resistor R33, the zener diode Z3 and the third resistor R38 until the second MOS tube Q8 is conducted, and the second lower bias resistor R40 is connected.

At this time, the lower bias resistor at the Vsen terminal is the resistor value after the parallel connection of R24, R40 and R27, and at this time, the resistor value is minimum and the voltage at the Vsen terminal is maximum. The pressure regulating schematic diagram can be seen from the following: the Vout output voltage is at a maximum.

2. When the monitoring chip MCU-1 monitors that the charger is pulled out of the electronic equipment, a PWM signal is output, and the optocoupler switch U3 works in a PWM mode. The state of the first branch at this time is: when PWM is high level, the optocoupler switch is conducted, and the LDO-10V charges the first charging capacitor C8 through the first diode D10; when PWM is low level, the photo-coupling switch is turned off, the first charging capacitor C8 discharges through the first resistor R36→R35→the grounding end, the PWM duty ratio is controlled to enable the charging ratio of the first charging capacitor C8 to be more than that of the first charging capacitor C8, the driving end of the first MOS tube Q7 is high level, the first MOS tube Q7 is conducted, and the first lower bias resistor R27 is connected.

And the state of the second branch at this time is: the photocoupler switch U3 is conducted when the PWM is in a high level, the second resistor R33 charges the third charging capacitor C9 by LDO-10V, the photocoupler switch U3 is cut off when the PWM is in a low level, the third charging capacitor C9 discharges through the second diode D11-the grounding resistor R35-the grounding terminal, the PWM duty ratio is controlled, and the charging and discharging parameters of the second resistor R33, the third charging capacitor C9 and the second diode D11 are adjusted, so that the third charging capacitor C9 is more charged than the third charging capacitor C9, the voltage of the third charging capacitor C9 is smaller than the conducting voltage (for example, 5.1V) of the voltage stabilizing diode Z3, and the voltage stabilizing diode Z3 is not conducted; the second charging capacitor C15 discharges slowly, the driving end of the second MOS transistor Q8 is at a low level, and the second MOS transistor Q8 is not turned on.

At this time, the lower bias resistor at the Vsen terminal is the resistor value after the parallel connection of R24 and R27, and the resistor value is centered at this time, and the voltage at the Vsen terminal is centered. The pressure regulating schematic diagram can be seen from the following: the Vout output voltage is an intermediate value.

3. When the MCU-1 monitors that the plugging end of the charger is in no-load or light-load, the MCU-1 outputs low level, and the optocoupler switch U3 is turned off. The state of the first branch at this time is: the first charging capacitor C8 discharges through the first resistor R36, the driving end of the first MOS transistor Q7 is at a low level, and the first MOS transistor Q7 is not turned on.

And the state of the second branch at this time is: the second charging capacitor C15 and the third charging capacitor C9 are both discharged, the driving end of the second MOS tube Q8 is at a low level, and the second MOS tube Q8 is not conducted.

At this time, the lower bias resistor at the Vsen terminal is R24, and at this time, the resistance is maximum and the voltage at the Vsen terminal is minimum. The pressure regulating schematic diagram can be seen from the following: the Vout output voltage is at a minimum.

It should be noted that, no-load means that the charger is not connected to the electronic device, and the charger operates in a low voltage (e.g., 13V) state; the light load refers to that the electric quantity of the electronic equipment is more than 80%, and the charger can work in a low-voltage state to continuously charge the electronic equipment.

The above-mentioned change process is that the resistance value of the voltage regulating circuit changes when the charger outputs high voltage to low voltage. When the charger outputs low voltage to high voltage, the resistance change of the voltage regulating circuit is opposite to the above process, but the circuit principle is the same and will not be described here.

Example two

As shown in fig. 3, a single-stage PFC circuit of a high-power fast-charging charger includes an AC input terminal, an input rectifying and filtering circuit, a transformer, an output rectifying and filtering circuit, and an output terminal, and a main control chip (IW 3627) is disposed between the input side of the transformer and the input rectifying and filtering circuit; a monitoring chip (P3712) is provided at the output terminal and is used for monitoring the connection state of the charger and the load (electronic device). The system also comprises a main control chip (IW 3627), a monitoring chip (P3712) and a variable resistance voltage regulating circuit of the scheme.

The power supply pin Vcc (i.e., LDO-10V) of the main control chip (IW 3627) is connected with the power supply end of the variable resistance voltage regulating circuit and provides 10V voltage for the variable resistance voltage regulating circuit. The power supply link is connected with an optocoupler switch U3, and the driving end of the optocoupler switch U3 is connected with the output end of the monitoring chip MCU-1; the on-off of the optocoupler switch U3 is according to different states of the charger plug-in end monitored by the monitoring chip MCU-1, as described above, and will not be described herein.

A fourth resistor R18 is arranged between the power supply pin of the main control chip and the optocoupler switch, and a fifth resistor R34 is arranged between the optocoupler switch and the output end of the monitoring chip.

By adopting the technical scheme of the embodiment, the varistor voltage regulating circuit adjusts the output voltage signal to the feedback pin of the main control chip (IW 3627) according to the sampling control signal of the monitoring chip (P3712) so that the main control chip (IW 3627) changes the output voltage Vout, and can output an intermediate voltage value as a transitional state when the high voltage and the low voltage are switched, for example, a transitional voltage between 26V and 13V is between 17V and 18V, as shown by a curve Vout in the graph of FIG. 4.

It should be noted that, the input rectifying and filtering circuit, the transformer and the output rectifying and filtering circuit in the single-stage PFC circuit of the high-power fast-charging charger are all of the existing circuit structures, as shown in fig. 5 to 8, and the specific working principle and connection relationship are not repeated.

The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The foregoing examples illustrate only a few embodiments of the utility model, which are described in detail and are not to be construed as limiting the scope of the utility model. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the utility model, which are all within the scope of the utility model. Accordingly, the scope of protection of the present utility model is to be determined by the appended claims.

Claims

1. A varistor voltage regulating circuit, comprising:

the power supply end is used for acquiring a sampling control signal of a monitoring chip of the charger;

the signal output end is used for outputting different voltage signals to a feedback pin of a main control chip of the charger;

the device also comprises a first lower bias resistor, a second lower bias resistor and a third lower bias resistor which are connected in parallel, wherein one ends of the three lower bias resistors are connected with the signal output end;

the other end of the first lower bias resistor is connected with the drain electrode of the first MOS tube, and the grid electrode of the first MOS tube is connected with the first charging capacitor and the power supply end;

the other end of the second lower bias resistor is connected with the drain electrode of the second MOS tube, the grid electrode of the second MOS tube is connected with the second charging capacitor and the third charging capacitor, a zener diode is arranged between the second MOS tube and the third charging capacitor, and one end of the cathode of the zener diode is connected with the third charging capacitor.

2. The variable-resistance voltage regulating circuit of claim 1, wherein a first diode and a first resistor are arranged in parallel between the first charging capacitor and the power supply terminal, the cathode of the first diode is connected with the first charging capacitor, the anode of the first diode is connected with the power supply terminal, and a grounding resistor is arranged between the first resistor and the grounding terminal.

3. The variable-resistance voltage regulating circuit according to claim 1, wherein a second diode and a second resistor are connected in parallel between the connection node of the zener diode and the third charging capacitor and the power supply terminal, and the positive electrode of the second diode is connected with the third charging capacitor, and the negative electrode of the second diode is grounded through a grounding resistor.

4. The varistor voltage regulating circuit of claim 1, wherein the third lower bias resistor is connected in parallel with a filter capacitor.

5. The variable resistance voltage regulator circuit of claim 1, wherein the third lower bias resistor, the source of the first MOS transistor, and the source of the second MOS transistor are all grounded.

6. The variable resistance voltage regulator circuit of claim 1, wherein a third resistor is further disposed between the zener diode and the second charging capacitor.

7. The utility model provides a high-power quick charger's single-stage PFC circuit, includes AC input, input rectification filter circuit, transformer, output rectification filter circuit and output, input rectification filter circuit with be equipped with main control chip between the transformer, output department is equipped with the monitoring chip, the monitoring chip is used for monitoring the connection state of charger and load, its characterized in that, main control chip with be equipped with the varistor voltage regulating circuit of any one of claims 1 to 6 between the monitoring chip.

8. The single-stage PFC circuit of claim 7, wherein a power supply pin of the main control chip is connected to a power supply terminal of the varistor voltage-regulating circuit, an optocoupler switch is disposed between the main control chip and the power supply terminal of the varistor voltage-regulating circuit, and a driving terminal of the optocoupler switch is connected to the monitoring chip.

9. The single-stage PFC circuit of the high-power fast charge charger of claim 8, wherein a fourth resistor is disposed between the optocoupler switch and a power supply pin of the main control chip.

10. The single-stage PFC circuit of claim 8 wherein a fifth resistor is disposed between the optocoupler switch and the monitor chip.