CN220233195U

CN220233195U - Display substrate and display device

Info

Publication number: CN220233195U
Application number: CN202321220774.6U
Authority: CN
Inventors: 杜瑞芳; 马小叶
Original assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei Xinsheng Optoelectronics Technology Co Ltd
Priority date: 2023-05-17
Filing date: 2023-05-17
Publication date: 2023-12-22
Anticipated expiration: 2033-05-17

Abstract

The application discloses display substrate and display device, including substrate, thin film transistor and switching structure, one of source and drain electrode is connected through switching structure electricity with the grid, and switching structure includes grid switching pad and source drain electrode switching pad, and grid switching pad is connected with the grid with the layer and through first metal wire electricity, and source drain electrode switching pad is connected with source drain electrode with the layer and through second metal wire electricity, is connected between grid switching pad and the source drain electrode switching pad electricity, is equipped with the interval between grid switching pad and the source drain electrode switching pad all and the thin film transistor. According to the technical scheme provided by the embodiment of the application, through the fact that the through holes for connecting the grid electrode layer and the source electrode and drain electrode layer are arranged at a certain interval with the position of the TFT in the thin film transistor area, the through holes are far away from the position of the TFT, and the source electrode and drain electrode metal layer on the source electrode and drain electrode metal layer of the TFT and the source electrode and drain electrode metal layer on the through holes do not overlap and overlap, so that the conductive layer structure in the through holes does not have any influence on the characteristics of the TFT.

Description

Display substrate and display device

Technical Field

The present utility model relates generally to the field of display technologies, and in particular, to a display substrate and a display device.

Background

In the prior art, in order to save cost and module productivity, the product is basically GOA product, GOA is Gate Driven on Array for short, and is the meaning of gate driving integration on the array substrate, so that the progressive scanning driving function of the liquid crystal panel can be realized. In a conventional active matrix liquid crystal display, a row scanning signal is realized by an external integrated circuit, and a GOA driving is adopted, namely, a row scanning driving circuit is manufactured by adopting the same process as a Thin Film Transistor (TFT) on the basis that the external circuit only provides a plurality of control signals, so that a progressive scanning driving function is realized. Therefore, by adopting GOA driving, integrated circuits related to scanning driving are saved, and the manufacturing cost of the liquid crystal display is reduced.

The GOA unit is generally composed of a TFT tube and a capacitor, and there are many cases where the Gate is made of Gate layer metal and the source/drain is made of SD layer metal in the TFT process, and the connection needs via transfer, especially for a TFT tube where the Gate and the source (or drain) are connected together, the via used for transfer is often very close to the TFT tube, so as to save space, but in the existing product test, the location of the via and the TFT tube is found to affect the characteristics (Vth drift) of the TFT tube.

Disclosure of Invention

In view of the foregoing drawbacks or shortcomings of the prior art, it is desirable to provide a display substrate and a display device.

In a first aspect, there is provided a display substrate comprising a substrate, a thin film transistor and a transit structure, the thin film transistor comprising a gate electrode, a source electrode and a drain electrode, one of the source electrode and the drain electrode being electrically connected to the gate electrode through the transit structure,

the transfer structure comprises a gate transfer pad and a source/drain transfer pad, wherein the gate transfer pad and the gate are in the same layer and are electrically connected through a first metal wire, the source/drain transfer pad and the source/drain are in the same layer and are electrically connected through a second metal wire, the gate transfer pad and the source/drain transfer pad are electrically connected,

the gate transfer pad and the source drain electrode transfer pad are provided with a gate insulating layer therebetween, a passivation layer is arranged on one side of the source drain electrode transfer pad away from the gate transfer pad, the gate insulating layer and/or the passivation layer is provided with a via hole, an electric connection layer is arranged in the via hole and used for connecting the gate layer and the source drain electrode layer, and a gap is arranged between the gate transfer pad and the source drain electrode transfer pad and between the gate transfer pad and the thin film transistor.

As an achievable mode, the via hole is formed on the gate insulating layer, and a metal layer is arranged in the via hole and used for connecting the gate transfer pad and the source drain transfer pad.

As an achievable mode, the gate insulating layer and the passivation layer are provided with the via hole, and the via hole is internally provided with an ITO film layer for connecting the gate transfer pad and the source drain transfer pad.

As a realizable manner, the source electrode and the drain electrode are arranged in an interdigital manner and located in the same extending direction.

As an achievable manner, the orthographic projection of the gate pad on the substrate covers the orthographic projection of the source-drain pad on the substrate.

As an achievable way, the orthographic projection of the source-drain pad on the substrate covers the orthographic projection of the gate pad on the substrate.

As an achievable manner, the orthographic projection of the source-drain electrode pad on the substrate is overlapped with the orthographic projection of the gate electrode pad on the substrate, and exceeds the orthographic projection of the gate electrode pad.

As an achievable manner, the distance between the orthographic projection edge of the gate pad on the substrate and the orthographic projection edge of the source/drain pad on the substrate is 1-3 μm.

As an achievable manner, the edges of the gate transfer pad and the source drain transfer pad are slopes, and the slopes of the slopes intersect the substrate to have a slope angle, and the slope angle is smaller than 45 °.

In a second aspect, a display device is provided, including the display substrate described above.

According to the technical scheme provided by the embodiment of the application, through arranging the via holes for connecting the gate electrode layer and the source electrode layer at a certain interval with the thin film transistor region (the position of the TFT), the transfer hole is far away from the position of the TFT, and the source electrode and drain electrode metal layer on the TFT source electrode and drain electrode metal layer and the transfer layer do not overlap and overlap any repeated place, so that the conductive layer structure in the via holes does not have any influence on the characteristics of the TFT.

Drawings

Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the following drawings, in which:

FIG. 1 is a partial layout of a display substrate according to the present embodiment;

FIG. 2 is a schematic cross-sectional view of a substrate according to an embodiment;

FIG. 3 is a top view of the gate layer and the source drain layer of FIG. 2;

FIG. 4 is a schematic cross-sectional view of another embodiment of a display substrate;

FIG. 5 is a top view of the gate layer and the source drain layer of FIG. 4;

FIG. 6 is a schematic cross-sectional view of a display substrate according to another embodiment;

FIG. 7 is a top view of the gate layer and the source drain layer of FIG. 6;

FIG. 8 is a schematic cross-sectional view of a substrate according to another embodiment;

fig. 9 is a top view of the gate layer and the source drain layer of fig. 8.

Detailed Description

The present application is described in further detail below with reference to the drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the utility model and are not limiting of the utility model. It should be noted that, for convenience of description, only the portions related to the utility model are shown in the drawings.

It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other. The present application will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Referring to fig. 1, the present embodiment provides a display substrate, which includes a substrate 1, a thin film transistor and a transfer structure, wherein the thin film transistor includes a gate electrode, a source electrode and a drain electrode, one of the source electrode and the drain electrode is electrically connected with the gate electrode through the transfer structure,

the transfer structure comprises a gate transfer pad 2 and a source drain transfer pad 4, wherein the gate transfer pad 2 is in the same layer as the gate 23 and is electrically connected with the source drain 24 and the drain 25 through a first metal wire 20, the source drain transfer pad 4 is in the same layer as the source drain 25 and is electrically connected with the source drain transfer pad 4 through a second metal wire 21, the gate transfer pad 2 and the source drain transfer pad 4 are electrically connected with each other,

the gate transfer pad 2 and the source drain electrode transfer pad 4 are provided with a gate insulating layer 3 and a passivation layer arranged on one side of the source drain electrode transfer pad 4 far away from the gate transfer pad 2, the gate insulating layer 3 and/or the passivation layer is provided with a via hole, an electric connection layer is arranged in the via hole and used for connecting the gate layer and the source drain electrode layer, and an interval is arranged between the gate transfer pad 2 and the source drain electrode transfer pad 4 and the thin film transistor.

In the display substrate provided in this embodiment, the via hole for connecting the gate layer and the source drain layer is disposed at a certain interval with the thin film transistor region (where the TFT is located), so that the via hole is far away from the location where the thin film transistor is located.

In a typical pixel circuit, the gate 23 and the source 24 or the drain 25 are connected through a via, that is, a via is connected, and by arranging the via far from the TFT, as shown in fig. 1, a TFT with one gate 23 and drain 25 connected is arranged, wherein a certain distance is set between the via and the TFT (in which the region 22 is a via region, the region 33 is a TFT region, the region above the region 33 is a source drain layer 4, and the region below the region is a gate layer 2 pattern), and the gate or the source drain of the corresponding TFT is connected with an electrical connection layer in the via through a metal wire, specifically, the gate layer is connected with the gate pad 2 through a metal wire, the gate pad 2 is arranged with the gate 23, mainly used for transferring a signal of the gate 23 to other places, for example, a place far from the thin film transistor above is connected with the source drain pad 4 through a metal wire, the source 24 drain signal is connected with one of the source or the drain, for transferring a source signal to other places, for example, a place far from the thin film transistor above is not connected with the corresponding place through a via pad, and the corresponding place in the TFT can be connected to the TFT through a clear place through a via.

Optionally, the via hole 10 is disposed on the gate insulating layer 3, and a metal layer is disposed in the via hole 10 for connecting the gate pad and the source/drain pad.

The embodiments described above provide different arrangements, for example, as shown in fig. 2 and fig. 4, in which the via hole is disposed on the gate insulating layer 3, and the via hole is connected to the gate pad 2 and the source drain pad 4 through the metal layer, and only one arrangement in which the gate pad 2 and the source drain pad 4 are connected is shown in fig. 2 and fig. 4, and the specific position of the via hole needs to be set according to the embodiments described above, and is far away from the TFT so as to avoid the influence on the TFT.

Optionally, the via hole 11 is disposed on the gate insulating layer 3 and the passivation layer, and the ITO film layer 8 is disposed in the via hole 11 to connect the gate pad 2 and the source/drain pad 4.

In this embodiment, as shown in fig. 6 and 8, two vias are provided to connect the gate pad 2 and the source/drain pad 4, and bridging is performed through the two vias, and an ITO (indium tin oxide) film layer is generally disposed in the via for electrical connection. Only one way of connecting the gate landing pad 2 and the source drain landing pad 4 is shown in fig. 6 and 8, and the specific location of the via needs to be set according to the above embodiment, away from the TFT to avoid the influence on it.

Further, the source electrode 24 and the drain electrode 25 are arranged in an interdigital manner and located in the same extending direction.

As shown in fig. 1, the source and drain patterns in this embodiment are alternately arranged in the same extending direction, and the gate pad and the source connection line or the drain connection line (the source connection line or the drain connection line connecting the alternately arranged source regions or drain regions) are also in the same extending direction.

Further, the orthographic projection of the gate pad 2 on the substrate 1 covers the orthographic projection of the source/drain pad 4 on the substrate 1.

In order to avoid the influence of the via hole on the TFT, this embodiment also provides a way to cover the structure of the source/drain electrode transfer pad 4 disposed on the gate transfer pad 2, and a certain distance exists between the two orthographic projections, so as to ensure that the gate insulating layer 3 on the gate transfer pad 2 covers the gate transfer pad 2 more fully, and reduce the influence of the via hole on the TFT. In addition, the TFT manufacturing processes of different products are slightly different, and the corresponding via designs are also different, and in the structure shown in fig. 2 and 3 provided in this embodiment, the range of the gate transfer pad 2 is larger than the range of the source drain transfer pad 4, and the orthographic projection of the gate transfer pad 2 on the substrate 1 covers the orthographic projection of the source drain transfer pad 4 on the substrate 1, so that a certain distance exists between the edge of the gate transfer pad 2 and the projection of the edge of the source drain transfer pad 4 on the substrate 1. The substrate may be, for example, a glass substrate.

In addition, in the display substrate structure shown in fig. 6 and 7, the connection between the gate pad 2 and the source/drain pad 4 is bridged by a via hole, compared with the above structure, the adopted TFT process is different, wherein a first passivation layer 5 is disposed on one side of the source/drain pad 4 far away from the gate pad 2, a second passivation layer 7 is disposed on the first passivation layer 5, an ORG layer 6 is disposed between the first passivation layer 5 and the second passivation layer 7, in order to realize the connection between the gate pad 2 and the source/drain pad 4, a via hole 11 is disposed on the gate insulating layer 3 and the first passivation layer 5 and the second passivation layer 7, the electrical connection between the ITO layer in the via hole and the gate pad 2 is realized, the corresponding via hole is disposed on the first passivation layer 5 and the second passivation layer 7, the electrical connection between the ITO layer in the via hole and the source/drain pad 4 is realized, and the ORG layer 6 has a larger via hole exposing the whole via hole. In this structure, the gate pad 2 is disposed in a larger range, and the gate pad 2 covers the entire orthographic projection of the source/drain pad 4, resulting in the situation shown in fig. 7, in which a certain distance exists between the gate pad 2 and the edge of the source/drain pad 4 in fig. 7.

Further, the orthographic projection of the source-drain pad 4 on the substrate 1 covers the orthographic projection of the gate pad 2 on the substrate 1.

In another arrangement mode of the gate pad 2 and the source drain pad 4, as shown in fig. 4 and 5, the position of the source drain pad 4 is larger than the range of the gate pad 2, the orthographic projection of the source drain pad 4 on the substrate 1 covers the orthographic projection of the gate pad 2 on the substrate 1, wherein the range and the size of the gate pad 2 and the source drain pad 4 are not different in principle, and according to the arrangement space of a specific pixel circuit, if the space of the gate layer is tense, the range of the gate pad 2 is set smaller, and the orthographic projection of the source drain pad 4 covers the gate pad 2, otherwise, the orthographic projection of the gate pad 2 can be selected to cover the mode of the source drain pad 4.

Optionally, the orthographic projection of the source-drain pad 4 on the substrate 1 is overlapped with the orthographic projection of the gate pad 2 on the substrate 1, and exceeds the orthographic projection of the gate pad 2.

In another arrangement mode of the gate pad 2 and the source drain pad 4, as shown in fig. 8 and 9, the connection between the gate pad 2 and the source drain pad 4 is performed through a via hole, wherein a first passivation layer 5 is disposed on one side of the source drain pad 4 away from the gate pad 2, a second passivation layer 7 is disposed on the first passivation layer 5, an ORG layer 6 is disposed between the first passivation layer 5 and the second passivation layer 7, in order to achieve connection between the gate pad 2 and the source drain pad, via holes 11 are disposed on the gate insulating layer 3 and the first passivation layer 5, and on the second passivation layer 7, electrical connection between the ITO layer in the via hole and the gate pad 2 is achieved, corresponding via holes are disposed on the first passivation layer 5 and the second passivation layer 7, electrical connection between the ITO layer in the via hole and the source drain pad 4 is achieved, and the ORG layer 6 has a larger via hole exposing the whole position of the via hole. In this structure, the range of the source-drain transfer pad 4 is slightly larger, the orthographic projection of the source-drain transfer pad 4 on the substrate 1 coincides with the portion of the gate transfer pad 2, forming the situation shown in fig. 9, in which fig. 9, the source-drain transfer pad 4 covers the upper portion of the gate transfer pad 2 and exceeds the gate transfer pad 2, and there is a certain distance between the edge and the edge of the gate transfer pad 2.

Further, the distance between the front projection edge of the gate pad 2 on the substrate 1 and the front projection edge of the source/drain pad 4 on the substrate 1 is 1-3 μm.

Considering the alignment problem and CD fluctuation in the preparation process of each layer structure, the good wrapping effect of the gate insulation layer 3 on the gate transfer pad 2 is ensured, the good wrapping effect of the first passivation layer 5 on the source drain transfer pad 4 is also ensured, and the spacing between the orthographic projection edges of the gate transfer pad 2 and the source drain transfer pad 4 is set at 1-3 mu m.

Further, the edges of the gate transfer pad 2 and the source drain transfer pad 4 are slopes, and the slopes of the slopes intersect the substrate 1 to form a slope angle, and the slope angle is smaller than 45 degrees.

In the actual manufacturing process, in order to ensure that the insulating layer deposited on the back of the corresponding metal layer can achieve a good wrapping effect on the metal layer, the metal edges of the control gate transfer pad 2 and the source drain transfer pad 4 are of slope structures, for example, as shown in the drawings, the wrapping effect of the insulating layer on the metal layer is good, the product reliability is good, the product yield is high, the control slope angle is smaller than 45 degrees, the slope gradient is smaller, and the coverage of the insulating layer on the metal layer is more detailed.

The number of the through holes in the embodiment is selected according to practical situations, and is not limited by the drawings and description.

The embodiment also comprises a display panel, which comprises the display substrate. The display substrate according to the above embodiment may be, for example, an array substrate.

The embodiment also includes a display device including the display substrate.

In a specific implementation process, the display device provided in this embodiment may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, and a navigator. Other essential components of the display device will be understood by those skilled in the art, and are not described herein in detail, nor should they be considered as limiting the utility model.

It is to be understood that the above references to the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., are for convenience in describing the present utility model and simplifying the description only, and do not indicate or imply that the apparatus or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the present utility model; the orientation word "inner and outer" refers to inner and outer relative to the contour of the respective component itself. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature.

Spatially relative terms, such as "above … …," "above … …," "upper surface at … …," "above," and the like, may be used herein for ease of description to describe one device or feature's spatial location relative to another device or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "above" or "over" other devices or structures would then be oriented "below" or "beneath" the other devices or structures. Thus, the exemplary term "above … …" may include both orientations of "above … …" and "below … …". The device may also be oriented 90 degrees or at other orientations and the spatially relative descriptors used herein interpreted accordingly.

The foregoing description is only of the preferred embodiments of the present application and is presented as a description of the principles of the technology being utilized. It will be appreciated by persons skilled in the art that the scope of the utility model referred to in this application is not limited to the specific combinations of features described above, but it is intended to cover other embodiments in which any combination of features described above or equivalents thereof is possible without departing from the spirit of the utility model. Such as the above-described features and technical features having similar functions (but not limited to) disclosed in the present application are replaced with each other.

Claims

1. A display substrate is characterized by comprising a substrate, a thin film transistor and a transfer structure, wherein the thin film transistor comprises a grid electrode, a source electrode and a drain electrode, one of the source electrode and the drain electrode is electrically connected with the grid electrode through the transfer structure,

2. The display substrate of claim 1, wherein the via is provided on the gate insulating layer, and a metal layer is provided in the via for connecting the gate pad and the source/drain pad.

3. The display substrate according to claim 1, wherein the via hole is formed on the gate insulating layer and the passivation layer, and an ITO film layer is disposed in the via hole for connecting the gate pad and the source/drain pad.

4. A display substrate according to any one of claims 1-3, wherein the source and the drain are interdigitated in the same direction of extension.

5. The display substrate of claim 4, wherein an orthographic projection of the gate pad on the substrate covers an orthographic projection of the source drain pad on the substrate.

6. The display substrate of claim 4, wherein an orthographic projection of the source-drain landing pad on the substrate covers an orthographic projection of the gate landing pad on the substrate.

7. The display substrate of claim 4, wherein the orthographic projection of the source-drain landing pad on the substrate coincides with the orthographic projection of the gate landing pad on the substrate and is disposed beyond the orthographic projection of the gate landing pad.

8. The display substrate of claim 7, wherein a spacing between an orthographic projection edge of the gate landing pad on the substrate and an orthographic projection edge of the source drain landing pad on the substrate is 1-3 μm.

9. The display substrate of claim 8, wherein the gate landing pad and the source drain landing pad edges are sloped, the sloped surface of the sloped intersecting the substrate has a slope angle, the slope angle being less than 45 °.

10. A display device comprising the display substrate according to any one of claims 1 to 9.