CN220232433U - Random number acquisition and test system - Google Patents
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- CN220232433U CN220232433U CN202321964165.1U CN202321964165U CN220232433U CN 220232433 U CN220232433 U CN 220232433U CN 202321964165 U CN202321964165 U CN 202321964165U CN 220232433 U CN220232433 U CN 220232433U
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Abstract
The utility model discloses a random number acquisition and test system, which comprises: at least one random number forwarding device, a server and at least one hardware accelerator card; the random number forwarding device is used for collecting random numbers to be tested and forwarding the random numbers to be tested to the server; the server is connected with the random number forwarding device and the hardware acceleration card, and is used for forwarding the random number to be tested to the hardware acceleration card in real time, receiving a processing result of the hardware acceleration card and forwarding the processing result to the corresponding random number forwarding device; the hardware acceleration card comprises at least one FPGA chip, each FPGA chip comprises a randomness test module, and the randomness test module is used for simultaneously carrying out parallel test on a plurality of random numbers to be tested. The utility model can improve the efficiency of random number detection.
Description
Technical Field
The utility model relates to the technical field of random number testing, in particular to a random number acquisition and testing system.
Background
Random numbers are very widely used in scientific research, engineering techniques, etc., and special tests are often required to ensure that random numbers generated by random number devices are truly random numbers.
However, in the related art, the random number test system generally collects the random number, then stores the random number, copies the file to the random number detection host, and loads the file by the random number detection host and performs the approach test. According to the detection method, the acquisition process and the detection process are carried out in separate equipment locks, detection cannot be carried out, and the detection efficiency is low.
Disclosure of Invention
The utility model provides a random number acquisition and test system for improving the efficiency of random number detection.
According to an aspect of the present utility model, there is provided a random number acquisition and test system including: at least one random number forwarding device, a server and at least one hardware accelerator card; the random number forwarding device is used for collecting random numbers to be tested and forwarding the random numbers to be tested to the server; the server is connected with the random number forwarding device and the hardware acceleration card, and is used for forwarding the random number to be tested to the hardware acceleration card in real time, receiving a processing result of the hardware acceleration card and forwarding the processing result to the corresponding random number forwarding device; the hardware acceleration card comprises at least one FPGA chip, each FPGA chip comprises a randomness test module, and the randomness test module is used for simultaneously carrying out parallel test on a plurality of random numbers to be tested.
Optionally, the FPGA chip further includes the random number acquisition module, where the random number acquisition module is in communication connection with the randomness test module, and the random number acquisition module is configured to convert serial random numbers to be tested into parallel data.
Optionally, the FPGA chip further includes a test result statistics module, where the test result statistics module is in communication connection with the randomness test module, and the test result statistics module is configured to record a test result of the random number to be tested.
Optionally, the FPGA chip further includes: the cache module is in communication connection with the test result statistics module and is used for storing random numbers to be tested, which pass through the randomness test.
Optionally, the FPGA chip further includes:
the communication protocol processing module is in communication connection with the server, the cache module and the random number acquisition module, and the communication protocol processing module is used for carrying out communication protocol matching with the server.
Optionally, the random number forwarding device includes: at least one input interface for inputting the random number to be tested;
the processing chip is in communication connection with the input interface and is used for converting the random number to be tested into the random number to be tested in a preset transmission mode;
the output interface is in communication connection with the processing chip and is used for transmitting the random number to be tested in the preset transmission mode to the server.
Optionally, the input interface is of the type: SPI type, UART type or USB type.
Optionally, the output interface is a network cable interface or a wireless signal transmitter.
Optionally, the server is a cloud server.
The technical scheme of the embodiment of the utility model adopts a random number acquisition and test system which comprises the following steps: at least one random number forwarding device, a server and at least one hardware accelerator card; the random number forwarding device is used for collecting the random number to be tested and forwarding the random number to be tested to the server; the server is in communication connection with the random number forwarding device and the hardware acceleration card, and is used for forwarding the random number to be tested to the hardware acceleration card in real time, receiving a processing result of the hardware acceleration card and forwarding the processing result to the corresponding random number forwarding device; the hardware acceleration card comprises at least one FPGA chip, each FPGA chip comprises a randomness test module, and the randomness test module is used for simultaneously carrying out parallel test on a plurality of random numbers to be tested. The random number acquisition and test system can acquire the random number to be tested, and can forward and detect the randomness of the random number in real time, namely, the acquisition and detection functions are integrated, so that the detection efficiency can be improved, and the detection time can be saved. The hardware acceleration card can improve the detection speed in a hardware acceleration mode, and simultaneously, the randomness test module is used for detecting a plurality of random numbers to be tested in parallel, so that the random numbers to be tested can be detected at the same time, and the detection efficiency can be further improved.
It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the utility model or to delineate the scope of the utility model. Other features of the present utility model will become apparent from the description that follows.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a system for collecting and testing random numbers according to an embodiment of the present utility model;
FIG. 2 is a schematic diagram of a system for collecting and testing random numbers and a generator for random numbers to be tested according to an embodiment of the present utility model;
FIG. 3 is a schematic diagram of a hardware accelerator card according to an embodiment of the present utility model;
fig. 4 is a schematic process diagram of an FPGA chip according to an embodiment of the present disclosure;
fig. 5 is a schematic structural diagram of another random number acquisition and testing system according to an embodiment of the present utility model.
Detailed Description
In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Fig. 1 is a schematic structural diagram of a random number collection and testing system according to an embodiment of the present utility model, and fig. 2 is a schematic structural diagram of an electrical connection between a random number collection and testing system and a random number generator to be tested according to an embodiment of the present utility model, and referring to fig. 1 and fig. 2, the random number collection and testing system includes: at least one random number forwarding device 11, a server 12 and at least one hardware accelerator card 13; the random number forwarding device 11 is configured to collect a random number to be tested and forward the random number to be tested to the server 12; the server 12 is in communication connection with the random number forwarding device 11 and the hardware acceleration card 13, and the server 12 is used for forwarding the random number to be tested to the hardware acceleration card 13 in real time, receiving a processing result of the hardware acceleration card 13, and forwarding the processing result to the corresponding random number forwarding device 11; the hardware accelerator card 13 includes at least one FPGA (Field Programmable Gate Array, field programmable array) chip, each of which includes a randomness test module for simultaneously testing a plurality of random numbers to be tested in parallel.
Specifically, each random number forwarding device 11 may be connected to a random number generator 20 to be tested, and the random number generator 20 to be tested is used for generating random numbers to be tested. After the random numbers to be tested generated by the random number generator 20 to be tested are collected and forwarded by the corresponding random number forwarding device 11, the random numbers to be tested are sent to the server 12, the server 12 forwards the received random numbers to be tested to the hardware acceleration card 13 in real time, the FPGA chip in the hardware acceleration card 13 performs randomness detection on the random numbers to be tested, specifically, the randomness test module is utilized to perform parallel test on the random numbers to be tested, namely, the randomness of the random numbers to be tested can be tested simultaneously. From the above analysis, in this embodiment, the random number collection and test system can collect the random number to be tested, and forward and detect the randomness of the random number in real time, that is, integrate the collection and detection functions, so as to improve the detection efficiency and save the detection time. In addition, the hardware acceleration card can improve the detection speed in a hardware acceleration mode, and simultaneously, the randomness test module is used for detecting a plurality of random numbers to be tested in parallel, so that the random numbers to be tested can be detected at the same time, and the detection efficiency can be further improved.
According to the technical scheme of the embodiment, the adopted random number acquisition and test system comprises: at least one random number forwarding device, a server and at least one hardware accelerator card; the random number forwarding device is used for collecting the random number to be tested and forwarding the random number to be tested to the server; the server is in communication connection with the random number forwarding device and the hardware acceleration card, and is used for forwarding the random number to be tested to the hardware acceleration card in real time, receiving a processing result of the hardware acceleration card and forwarding the processing result to the corresponding random number forwarding device; the hardware acceleration card comprises at least one FPGA chip, each FPGA chip comprises a randomness test module, and the randomness test module is used for simultaneously carrying out parallel test on a plurality of random numbers to be tested. The random number acquisition and test system can acquire the random number to be tested, and can forward and detect the randomness of the random number in real time, namely, the acquisition and detection functions are integrated, so that the detection efficiency can be improved, and the detection time can be saved. The hardware acceleration card can improve the detection speed in a hardware acceleration mode, and simultaneously, the randomness test module is used for detecting a plurality of random numbers to be tested in parallel, so that the random numbers to be tested can be detected at the same time, and the detection efficiency can be further improved.
Alternatively, after the hardware accelerator 13 detects the randomness of the random number to be tested, the processing result may be sent to the server 12, and forwarded by the server 12 to the corresponding random number forwarding device 11, and forwarded to the corresponding random number 20 to be tested via the random number forwarding device 11, where the random number generator 20 to be tested can execute a next operation according to the processing result, for example, if the processing result is that the randomness is not qualified, the state of the random number generator is adjusted, and the generated random number to be tested is changed.
Alternatively, the random number to be tested may be tested using national standards or NIST standards. The randomness test may include frequency, sequence, playing card, run, autocorrelation and other tests, and if any test result is failed, the randomness test of the random number to be tested is failed.
Optionally, fig. 3 is a schematic structural diagram of a hardware accelerator card 13 according to an embodiment of the present utility model, referring to fig. 3, the hardware accelerator card 13 includes an FPGA chip 131, the FPGA chip 131 further includes a random number acquisition module 1311, the random number acquisition module 1311 is communicatively connected to the randomness test module 1312, and the random number acquisition module 1311 is configured to convert serial random numbers to be tested into parallel data.
Specifically, the random number collection module 1311 is configured to collect the random numbers to be tested forwarded by the server 12, where the random numbers to be tested forwarded by the server 12 are serial bit stream data, the random number collection module 1311 converts the serial data into parallel data with bytes as units, and the parallel data is buffered and sent to the randomness test module 1312, so that the randomness test module 1312 can process multiple random numbers to be tested in parallel. The random number to be tested is cached, so that the effect of collecting and testing the random number to be tested can be achieved.
Optionally, with continued reference to fig. 3, the fpga chip 131 further includes a test result statistics module 1313, where the test result statistics module 1313 is communicatively connected to the randomness test module 1312, and the test result statistics module 1313 is configured to record a test result of the random number to be tested.
Specifically, in this embodiment, the test result statistics module 1313 may count performance test results of the random number to be tested, i.e. the number of test success and failure, collected from the random number generator to be tested since the random number collection and test system is started. By analyzing the number of success and failure of the test, the characteristics of the random number to be tested can be dynamically detected, so that the quality of the random number to be tested can be monitored for a long time.
Optionally, with continued reference to fig. 3, the fpga chip 131 further includes a buffer module 1314, where the buffer module 1314 is communicatively connected to the test result statistics module 1313, and the buffer module 1314 is configured to store the random number to be tested that passes the randomness test.
Specifically, the buffer module 1314 may be a memory chip, such as DDR3 or DDR 4. The buffer module 1314 stores the random number to be tested for use by the server 12. Optionally, the random number to be tested, which is tested by the randomness testing module 1312, may be stored in the buffer module 1314 in real time, and if the buffer module 1314 has insufficient storage space, the random number collection and testing system is controlled to suspend the collection and testing of the random number to be tested; when the server 12 or other main control unit takes the data from the buffer module 1314, it controls the random number acquisition and test system to continue the acquisition and test of the random number to be tested.
Optionally, with continued reference to fig. 3, the fpga chip 131 further includes: the communication protocol processing module 1315, the communication protocol processing module 1315 is in communication connection with the server 12 and the cache module 1314 level random number acquisition module 1311, and the communication protocol processing module 1315 is used for performing communication protocol matching with the server 12.
Specifically, the hardware accelerator card 13 and the server 12 may be connected through a PCIE interface. The communication protocol processing module 1315 may be a communication protocol processing module that implements a PCI-E standard communication protocol or other custom protocol with the server 12. After the data sent by the server 12 is processed by the communication protocol processing module 1315, the data is matched with the random number acquisition module 1311, so that the random number acquisition module 1311 can process the data. And the data in the buffer module 1314 can be matched with the server 12 after being processed by the communication protocol processing module 1315, so as to perform data interaction with the server 12.
Optionally, with continued reference to fig. 3, the hardware accelerator card 13 further includes a power supply 132 and a clock 133; the power supply 132 is electrically connected with the FPGA chip 131 and is used for supplying power to the FPGA chip 131; the clock 133 is electrically connected to the FPGA chip 131 and is used to provide a clock signal to the FPGA chip 131.
For example, fig. 4 is a schematic process diagram of an FPGA chip provided in an embodiment of the present utility model, where the randomness test module includes a plurality of randomness test units 1315 that can be processed in parallel, and when the hardware accelerator card includes an FPGA chip, for different tests of the random number to be tested, the tests may be performed in different randomness test units, for example, one randomness test unit is used for frequency test, one randomness test unit is used for sequence test, one randomness test unit is used for run test, and one randomness test unit is used for autocorrelation test. Each randomness test unit 1315 may perform parallel detection on random numbers from a plurality of random number generators under test, as a1, a2, a3 in the figure represent one randomness test unit 1315 performing detection on three random numbers simultaneously. Similarly, b1, b2, b3 represent the detection of the "sequence test" item by one random test unit 1315 simultaneously for three random numbers, c1, c2, c3 represent the detection of the "run test" item by one random test unit 1315 simultaneously for three random numbers, and d1, d2, d3 represent the detection of the "auto-correlation test" item by one random test unit 1315 simultaneously for three random numbers. When multiple FPGA chips are included in the hardware accelerator card, different tests may be placed in different FPGA chips. The random number acquisition and test system can also test other test items, and when the test resources of the random number to be tested remain, the random number to be tested can be processed in parallel with other test items, so that the waste of the operation resources of the random number acquisition and test system is avoided.
Optionally, fig. 5 is a schematic structural diagram of still another system for collecting and testing random numbers according to an embodiment of the present utility model, and referring to fig. 5, the random number forwarding device 11 includes: at least one input interface 111, the input interface 111 is used for inputting the random number to be tested; the processing chip 112, the processing chip 112 is connected with the input interface 111 in a communication way, and the processing chip 112 is used for converting the random number to be tested into the random number to be tested with a preset transmission mode; the output interface 113, the output interface 113 is connected with the processing chip 112 in a communication way, and the output interface 113 is used for transmitting the random number to be tested in the preset transmission mode to the server.
Specifically, the input interface 111 may be an SPI type, UART type, or USB type interface, and when the random number forwarding device 11 includes a plurality of input interfaces 111, the types of different input interfaces 111 may be different, thereby enabling the random number forwarding device 11 to be compatible with random number generators to be detected of a plurality of interface types. In some embodiments, the random number forwarding device 11 may further include a memory (not shown) for temporarily storing the random number to be tested input by the input interface 111. The processing chip 112 can convert the mode of the random number to be tested into a signal mode that can be transmitted by the output interface 113, that is, the preset transmission mode is a signal mode that can be transmitted by the output interface 113. The output interface 113 may be a network cable interface or a wireless signal transmitter. In other embodiments, the processing chip 112 may also perform pre-run settings of the transmission process, such as selection of an acquisition interface (input interface), acquisition rate settings, acquisition time settings, etc., and the processing chip 112 may also perform process control. The output interface 113 can adopt a wireless signal transmitter, and a plurality of random number generators 20 to be tested can be detected simultaneously in a wireless networking mode without using complex wiring.
Optionally, the server 12 is a cloud server, which may include a processor, a memory, and a PCIE interface. The processor is mainly used for forwarding the random number to be tested to the hardware acceleration card in real time, receiving the processing result of the hardware acceleration card and forwarding the processing result to the corresponding random number forwarding equipment; the memory is mainly used for temporary storage of data. The PCIE interface is mainly used for communication between the cloud server and the hardware accelerator card.
It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present utility model may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present utility model are achieved, and the present utility model is not limited herein.
The above embodiments do not limit the scope of the present utility model. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included in the scope of the present utility model.
Claims (9)
1. A random number acquisition and testing system, comprising: at least one random number forwarding device, a server and at least one hardware accelerator card; the random number forwarding device is used for collecting random numbers to be tested and forwarding the random numbers to be tested to the server; the server is connected with the random number forwarding device and the hardware acceleration card, and is used for forwarding the random number to be tested to the hardware acceleration card in real time, receiving a processing result of the hardware acceleration card and forwarding the processing result to the corresponding random number forwarding device; the hardware acceleration card comprises at least one FPGA chip, each FPGA chip comprises a randomness test module, and the randomness test module is used for simultaneously carrying out parallel test on a plurality of random numbers to be tested.
2. The system of claim 1, wherein the FPGA chip further comprises a random number acquisition module communicatively coupled to the randomness test module, the random number acquisition module configured to convert serial random numbers to be tested into parallel data.
3. The system according to claim 2, wherein the FPGA chip further comprises a test result statistics module, the test result statistics module is communicatively connected to the randomness test module, and the test result statistics module is configured to record a test result of the random number to be tested.
4. The random number acquisition and testing system of claim 3, wherein the FPGA chip further comprises: the cache module is in communication connection with the test result statistics module and is used for storing random numbers to be tested, which pass through the randomness test.
5. The system of claim 4, wherein the FPGA chip further comprises:
the communication protocol processing module is in communication connection with the server, the cache module and the random number acquisition module, and the communication protocol processing module is used for carrying out communication protocol matching with the server.
6. The system for random number acquisition and testing according to claim 1, wherein said random number forwarding device comprises: at least one input interface for inputting the random number to be tested;
the processing chip is in communication connection with the input interface and is used for converting the random number to be tested into the random number to be tested in a preset transmission mode;
the output interface is in communication connection with the processing chip and is used for transmitting the random number to be tested in the preset transmission mode to the server.
7. The system for random number acquisition and testing according to claim 6, wherein the input interface is of the type: SPI type, UART type or USB type.
8. The system of claim 6, wherein the output interface is a network cable interface or a wireless signal transmitter.
9. The system of claim 1, wherein the server is a cloud server.
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| CN202321964165.1U CN220232433U (en) | 2023-07-24 | 2023-07-24 | Random number acquisition and test system |
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| CN202321964165.1U CN220232433U (en) | 2023-07-24 | 2023-07-24 | Random number acquisition and test system |
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