CN220210450U - Calibration circuit and calibration system - Google Patents

Abstract

The utility model discloses a calibration circuit and a calibration system. The calibration circuit is in communication connection with the upper computer and is used for completing the self calibration and external calibration of the calibration circuit, and the calibration circuit comprises: the signal transmitting end is used for outputting an IQ signal; the phase amplitude acquisition unit is connected with the signal transmitting end through a switch array and is used for carrying out phase information acquisition or amplitude information acquisition on the IQ signal output by the signal transmitting end so as to calibrate the signal transmitting link by the upper computer; the signal receiving end is connected with the signal transmitting end through a switch array and is used for outputting an IQ signal so as to enable the upper computer to calibrate the signal receiving link. The utility model solves the problems of low calibration efficiency and low precision when the tester is calibrated in the related technology.

Description

Calibration circuit and calibration system

Technical Field

The utility model relates to the technical field of equipment calibration, in particular to a calibration circuit and a calibration system.

Background

In the field of wireless communication technology, IQ modulation belongs to standard configuration (in-MAG refers to in-phase, quadrature refers to quadrature), and is often applied to signal modulation and demodulation links of a communication system. Because the application of IQ modulation simplifies the hardware structure of the communication device, improves the utilization efficiency of spectrum resources, improves the stability of signal transmission, and more DUT (Device under test, calibrated device) chips based on IQ architecture design, the vector signal tester bears the emphasis of ensuring the yield of the DUT.

A qualified vector signal tester needs to ensure that the IQ signals input or output to the DUT are equal-amplitude quadrature, i.e., identical in amplitude and 90 DEG out of phase. However, because of individual differences of devices used by the board card patch of the tester, the PCB layout of each IQ channel cannot be controlled to be completely equal in length, so that the input and output channels of the tester cannot meet the same phase delay and channel gain, and the performance of the tester is affected by factors such as temperature, aging and the like along with the continuous extension of the service time. Thus, it is necessary to calibrate the tester so that it meets the channel gains of the quadrature phase and constant amplitude.

In the related art, a vector signal of a tester is calibrated by an instrument, fig. 1 is a schematic diagram of a radio frequency signal transmitting path of the tester calibrated in the related art, as shown in fig. 1, when the radio frequency signal transmitting path is calibrated, a radio frequency signal transmitting port of the tester and an input port of a vector signal analyzer are connected through a radio frequency cable, and then an i+, q+ or I-, Q-, of a TX link module (radio frequency signal transmitting link module) of the tester is excited at the same time, and at the moment, IQ amplitude differences and phase differences displayed on the analyzer are caused by differences among radio frequency signal transmitting paths of the tester. And recording the differences, and adjusting the emission amplitude and the emission delay at the source end of the tester until the IQ signal on the analyzer is orthogonal to the same amplitude, thereby completing the calibration of the radio frequency signal emission path of the tester.

Fig. 2 is a schematic diagram of a radio frequency signal receiving path of a calibration testing machine in the related art, as shown in fig. 2, when the radio frequency signal receiving path is calibrated by using a vector signal source, the radio frequency signal receiving port of the testing machine and the output port of the vector signal source are connected through a radio frequency cable, and then i+, q+ or I-, Q-, of the vector signal source are excited simultaneously, and at this time, an IQ amplitude difference and a phase difference obtained by SOC (System on chip) analysis are caused by the difference between the radio frequency signal receiving paths of the testing machine. And recording the differences, and adjusting the receiving amplitude and the receiving delay at the host end of the testing machine until the IQ signals obtained by analysis are orthogonal and have the same amplitude, thereby completing the calibration of the radio frequency signal receiving path of the testing machine.

The current vector signal testing machine is developed to a multi-channel mode, such as 16 channels, 302 channels and 64 channels, however, by means of an external instrument, whether the TX link module (radio frequency signal transmitting link module) or the RX link module (radio frequency signal receiving link module) of the testing machine is calibrated, all ports of the testing machine need to be calibrated manually one by one, and each time the calibration of one channel is completed, the calibration channels need to be manually switched and reconnected, the vector signal analyzer and the ports are plugged and unplugged one by one for N times (N is the number of channels), so that the calibration mode not only limits the calibration efficiency, wastes a large amount of labor cost, but also causes more errors in the connection condition, external cable loss uncertainty, and the radio frequency adapter and the like, and reduces the test precision.

Aiming at the problems of low calibration efficiency and low precision when the tester is calibrated in the related technology, no effective solution is proposed at present.

Disclosure of Invention

The utility model provides a calibration circuit and a calibration system, which are used for solving the problems of low calibration efficiency and low precision when a tester is calibrated in the related art.

According to one aspect of the utility model, a calibration circuit is provided. The calibration circuit includes: the signal transmitting end is used for outputting an IQ signal; the phase amplitude acquisition unit is connected with the signal transmitting end through a switch array and is used for carrying out phase information acquisition or amplitude information acquisition on the IQ signal output by the signal transmitting end so as to calibrate the signal transmitting link by the upper computer; the signal receiving end is connected with the signal transmitting end through a switch array and is used for outputting an IQ signal so as to enable the upper computer to calibrate the signal receiving link; the signal transmitting link refers to a link formed by devices from a signal transmitting end to a phase amplitude acquisition unit, and the signal receiving link refers to a link formed by devices from a signal transmitting end to a signal receiving end.

Optionally, the phase amplitude acquisition unit includes: the phase detector is connected with the signal transmitting end and used for detecting the phase difference value between the IQ signals; and the amplitude detector is connected with the signal transmitting end and is used for respectively detecting the amplitude of the IQ signal.

Optionally, the phase amplitude acquisition unit includes: the data acquisition device is electrically connected with the phase detector and the amplitude detector, and is used for receiving the phase information acquired by the phase detector and the amplitude information acquired by the amplitude detector, uploading the amplitude information and the phase information to the upper computer, and storing the phase information and the amplitude information sent by the upper computer.

Optionally, the phase detector includes a first input end and a second input end, the signal emission end includes two positive signal input ends and two negative signal input ends, and the switch array is used for communicating the two positive signal input ends with the first input end and the second input end respectively, or communicating the two negative signal input ends with the first input end and the second input end respectively; or the switch array is used for gating the signal transmitting end and the amplitude detector so that the two positive signal input ends and the two negative signal input ends are respectively communicated with the amplitude detector

Optionally, the switch array includes a first switch unit, a second switch unit, where the first switch unit includes a first input end, a first output end and a second output end, the second switch unit includes a second input end, a third output end and a fourth output end, the first input end of the first switch unit is connected with two positive signal input ends and two negative signal input ends, the first output end of the first switch unit is connected with a signal receiving end and is used for conducting a signal receiving link, and the second output end of the first switch unit is connected with the second input end of the second switch unit and is used for conducting a signal transmitting link; the third output end of the second switch unit is connected with the phase detector, the fourth output end of the second switch unit is connected with the amplitude detector, and the second switch is used for gating the second input end, the third output end and the fourth output end, and then conducting the signal transmitting link.

Optionally, the first switch unit includes a plurality of single-pole double-throw switches, the input end of the single-pole double-throw switch is a first input end, and the output ends of the single-pole double-throw switch are a first output end and a second output end respectively; the second switch unit comprises a plurality of single-pole double-throw switch groups, each single-pole double-throw switch group consists of two single-pole double-throw switches, the fixed contacts of the two single-pole double-throw switches are connected, and the movable contacts of the two single-pole double-throw switches are respectively a second input end, a third output end and a fourth output end of the second switch unit.

Optionally, the switch array further includes a third switch unit, where the third switch unit is a single-pole double-throw switch, an output end of the single-pole double-throw switch is connected to the amplitude detector, and an input end of the single-pole double-throw switch is connected to the fourth output end.

Optionally, the calibration circuit further includes an attenuation network, disposed between the signal transmitting end and the phase amplitude acquisition unit, for performing signal attenuation on the IQ signal output by the signal transmitting end.

According to another aspect of the present utility model, a calibration system is provided. The calibration system includes: a calibration circuit; the upper computer is in communication connection with the calibration circuit and is used for completing the self calibration and external calibration of the calibration circuit.

Optionally, the calibration system further comprises a calibrated device, wherein the calibrated device comprises an amplitude modulation unit and a delay unit, the amplitude modulation unit is used for adjusting the amplitude of the IQ signal received by the calibrated device when the upper computer performs external calibration, and the delay unit is used for adjusting the phase of the IQ signal received by the calibrated device when the upper computer performs external calibration.

The calibration circuit of the utility model is in communication connection with an upper computer and is used for completing the self calibration and external calibration of the calibration circuit, and comprises: the signal transmitting end is used for outputting an IQ signal; the phase amplitude acquisition unit is connected with the signal transmitting end through a switch array and is used for carrying out phase information acquisition or amplitude information acquisition on the IQ signal output by the signal transmitting end so as to calibrate the signal transmitting link by the upper computer; the signal receiving end is connected with the signal transmitting end through a switch array and is used for outputting an IQ signal so as to enable the upper computer to calibrate the signal receiving link; the signal transmitting link refers to a link from the signal transmitting end to the phase amplitude collecting unit, the signal receiving link refers to a link from the signal transmitting end to the signal receiving end, and the problems of low calibration efficiency and low precision in calibrating the testing machine in the related technology are solved. According to the utility model, the connection relation between the signal transmitting end, the phase amplitude acquisition unit and the signal receiving end is switched by the switch array, so that the self calibration and external calibration of the calibration circuit are completed, and the effects of improving the calibration efficiency and the calibration precision are further achieved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the utility model. In the drawings:

FIG. 1 is a schematic diagram of a radio frequency transmit path of a calibration test machine in the related art;

FIG. 2 is a schematic diagram of a radio frequency receive path of a calibration test machine in the related art;

FIG. 3 is a schematic diagram of a calibration circuit provided in accordance with an embodiment of the present utility model;

FIG. 4 is a schematic diagram of a calibration system provided in accordance with an embodiment of the present utility model;

FIG. 5 is a schematic diagram of amplitude calibration of a signal transmission link of a calibration circuit according to an embodiment of the present utility model;

FIG. 6 is a schematic diagram of phase calibration of a signal transmission link of a calibration circuit according to an embodiment of the present utility model;

fig. 7 is a schematic diagram of amplitude calibration and phase calibration of a signal receiving chain of a calibration circuit in an embodiment of the utility model.

Detailed Description

It should be noted that, without conflict, the embodiments of the present utility model and features of the embodiments may be combined with each other. The utility model will be described in detail below with reference to the drawings in connection with embodiments.

In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe the embodiments of the utility model herein.

According to the embodiment of the utility model, a calibration circuit is provided, which is in communication connection with an upper computer and is used for completing the self calibration and external calibration of the calibration circuit, wherein the external calibration refers to the calibration of calibrated equipment externally connected with the calibration circuit.

Fig. 3 is a schematic diagram of a calibration circuit according to an embodiment of the utility model. As shown in fig. 3, the calibration circuit includes:

and the signal transmitting end is used for outputting an IQ signal. Specifically, the signal transmitting end is an IQ signal transmitting port and is arranged on a circuit board, wherein the circuit board can be a PCB board (Printed Circuit Board ). Because the IQ signal includes an i+ signal, a q+ signal, an I-signal, and a Q-signal, the signal transmitting terminal may include two positive signal input ports and two negative signal input ports for transmitting the i+ signal, the q+ signal, the I-signal, and the Q-signal, respectively.

The signal transmission link is a link formed by devices, and comprises a signal transmission link of a calibration circuit and a signal transmission link of calibrated equipment.

The signal transmitting link of the calibration circuit is a link formed by devices from signals sent by a vector signal source to the phase amplitude acquisition unit; the signal transmitting link of the calibrated equipment is a link formed by devices from the signal sent by the calibrated equipment to the phase amplitude acquisition unit; the amplitude error calibration or the phase error calibration of the signal transmitting link is realized by switching the switches in the switch array between the signal transmitting end and the phase amplitude acquisition unit. The switch array may be a switch of SP8T, SP4T, SP T or the like, and the embodiment is not limited to the type of switch.

Optionally, in the calibration circuit provided in the embodiment of the present utility model, the phase amplitude acquisition unit includes: the phase detector is connected with the signal transmitting end and used for detecting the phase difference value between the IQ signals; and the amplitude detector is connected with the signal transmitting end and is used for respectively detecting the amplitude of the IQ signal. The phase detector and the amplitude detector are arranged on the circuit board.

The phase detector is used for carrying out phase detection on the IQ signal pair and outputting a voltage value representing the phase difference of the IQ signal, specifically, carrying out phase detection on the I+ signal and the Q+ signal to obtain a voltage value representing the phase difference of the I+ signal and the Q+ signal, or carrying out phase detection on the I-signal and the Q-signal to obtain a voltage value representing the phase difference of the I-signal and the Q-signal.

The amplitude detector is used for carrying out power detection on the IQ signal and outputting a voltage value representing the power of the signal, specifically, carrying out power detection on the I+ signal, the Q+ signal, the I-signal and the Q-signal respectively to obtain the voltage value corresponding to the power.

Specifically, if the switches in the switch array are switched, the output port of the signal transmitting end is connected with the input end of the phase detector in the phase amplitude acquisition unit, the phase error of the signal transmitting link of the calibration circuit can be calibrated under the condition of accessing the vector signal source, and the phase error of the signal transmitting link of the calibrated device can be calibrated under the condition of accessing the calibrated device.

If the switches in the switch array are switched, the output port of the signal transmitting end is connected with the input end of the amplitude detector in the phase amplitude acquisition unit, the amplitude error transmitted by the signal transmitting link of the calibration circuit can be calibrated under the condition of accessing the vector signal source, and the amplitude error of the signal transmitting link of the calibrated equipment can be calibrated under the condition of accessing the calibrated equipment.

The signal receiving end is connected with the signal transmitting end through a switch array and is used for outputting an IQ signal so as to enable the upper computer to calibrate a signal receiving link, wherein the signal receiving link refers to a link formed by devices from signal sending to signal receiving. The signal receiving link comprises the signal receiving link of the calibration circuit itself and the signal receiving link of the device to be calibrated.

The signal receiving link of the calibration circuit is a link formed by devices from the signal sent by the vector signal source to the signal receiving end;

the signal receiving link of the calibrated equipment is a link formed by a device from a signal sent by the calibrated equipment to a signal received by the calibrated equipment;

specifically, the signal receiving end is a receiving port of an IQ signal and is arranged on the circuit board, and the IQ signal comprises an i+ signal, a q+ signal, an I-signal and a Q-signal, and the signal receiving end can comprise two positive signal receiving ends and two negative signal receiving ends, which are respectively used for receiving the i+ signal, the q+ signal, the I-signal and the Q-signal.

The amplitude error calibration or the phase error calibration of the signal receiving link is realized by switching the switches in the switch array between the signal transmitting end and the signal receiving end. Specifically, if the switches in the switch array are switched, so that the output port of the signal transmitting end is connected with the input port of the signal receiving end, under the condition of accessing the signal detector, if the phase error and the amplitude error of the signal transmitting link of the calibration circuit are already calibrated, the phase error and the amplitude error of the signal receiving link of the calibration circuit can be calibrated. In the case of accessing the calibrated device, if the phase error and the amplitude error of the signal transmitting link of the calibrated device have already been calibrated, the phase error and the amplitude error of the signal receiving link of the calibrated device can be calibrated.

In order to achieve data interaction between the phase amplitude acquisition unit and the upper computer, optionally, in the calibration circuit provided by the embodiment of the utility model, the phase amplitude acquisition unit includes: the data acquisition device is electrically connected with the phase detector and the amplitude detector, and is used for receiving the phase information acquired by the phase detector and the amplitude information acquired by the amplitude detector, uploading the amplitude information and the phase information to the upper computer, and storing the phase information and the amplitude information sent by the upper computer.

The data collector may be an Analog-to-Digital conversion module, where an input end of the Analog-to-Digital conversion module is connected to an output end of the phase detector and an output end of the amplitude detector, and the Analog-to-Digital conversion module is used for converting amplitude information and phase information output by the phase detector and the amplitude detector into Digital signals respectively and uploading the Digital signals to the host computer. It should be noted that, the higher the accuracy of the analog-to-digital conversion module is, the more accurate the converted information is.

The storage unit may be a nonvolatile storage medium, and receives the amplitude information and the phase information output by the data collector forwarded by the upper computer, where when calibrating the phase errors and the amplitude errors of the signal transmitting link and the signal receiving link of the calibration circuit, the data collector converts the received amplitude information and the phase information into digital signals, and simultaneously acquires the amplitude information and the phase information of the signals sent by the vector signal source, stores the phase received by the data collector and the phase of the signals sent by the stored vector signal source as phase calibration information in the storage unit, and stores the amplitude received by the data collector and the amplitude of the signals sent by the stored vector signal source as amplitude calibration information in the storage unit, so as to be used when calibrating the calibrated equipment. Of course, those skilled in the art will recognize that the storage unit is not limited to a nonvolatile memory, such as a volatile memory, as long as it is capable of storing the relevant data, i.e., the amplitude information and the phase information.

Further, when the phase error and the amplitude error of the signal transmitting link and the signal receiving link of the calibrated equipment are calibrated, the data collector converts the received amplitude information and the received phase information into digital signals and transmits the digital signals to the upper computer, and meanwhile, the upper computer calls the amplitude calibration information and the phase calibration information stored by the storage unit so as to calibrate the calibrated equipment.

Optionally, in the calibration circuit provided in the embodiment of the present utility model, the phase detector includes a first input end and a second input end, the signal transmitting end includes two positive signal input ports and two negative signal input ports, and the switch array is configured to communicate the two positive signal input ports with the first input end and the second input end respectively, or communicate the two negative signal input ports with the first input end and the second input end respectively; or, the switch array is used for gating the signal transmitting end and the amplitude detector so that the two positive signal input ports and the two negative signal input ports are respectively communicated with the amplitude detector.

The signal transmitting terminal includes two positive signal input ports tx_i+, tx_q+ and two negative signal input ports tx_i-, tx_q-, wherein tx_i+, tx_q+, tx_i-, tx_q-, are used for transmitting i+ signal, q+ signal, I-signal, Q-signal, respectively.

Specifically, two forward signal input ports tx_i+ and tx_q+ in the signal transmitting end are respectively communicated with a first input end and a second input end of the phase detector by switching the switch array, so that the phase difference of the i+ signal and the q+ signal is detected. Or the two negative signal input ports TX_I-, TX_Q-in the signal transmitting end are communicated with the first input end and the second input end of the phase detector through the change-over switch array, so that the phase difference of the I-signal and the Q-signal is detected.

Or the forward signal input port TX_I+ in the signal transmitting end is connected with the input end of the amplitude detector through the change-over switch array, so as to detect the amplitude of the I+ signal; or the forward signal input port TX_Q+ in the signal transmitting end is connected with the input end of the amplitude detector through the change-over switch array, so as to detect the amplitude of the Q+ signal; or the switch array is switched to enable a negative signal input port TX_I-in the signal transmitting end to be connected with the input end of the amplitude detector, so that the amplitude of the I-signal is detected; or the switch array is switched to enable a negative signal input port TX_Q-in the signal transmitting end to be connected with the input end of the amplitude detector, so that the amplitude of the Q-signal is detected.

Optionally, in the calibration circuit provided by the embodiment of the utility model, the switch array includes a first switch unit and a second switch unit, the first switch unit includes a first input end, a first output end and a second output end, the second switch unit includes a second input end, a third output end and a fourth output end, the first input end of the first switch unit is connected with two positive signal input ends and two negative signal input ends, the first output end of the first switch unit is connected with a signal receiving end for conducting a signal receiving link, and the second output end of the first switch unit is connected with the second input end of the second switch unit for conducting a signal transmitting link; the third output end of the second switch unit is connected with the phase detector, the fourth output end of the second switch unit is connected with the amplitude detector, and the second switch is used for gating the second input end, the third output end and the fourth output end, and then conducting the signal transmitting link.

Specifically, when the first input end of the first switch unit is connected to the two positive signal input ends and the two negative signal input ends, the second output end of the first switch unit is connected to the second input end of the second switch unit, and the third output end of the second switch unit is connected to the phase detector, the signal transmitting link may be turned on to calibrate the phase error of the transmitting link. Under the condition that the signal transmitting end is connected with a vector signal source, the phase error of the transmitting link of the calibration circuit can be calibrated, and under the condition that the signal transmitting end is connected with the calibrated equipment, the phase error of the transmitting link of the calibrated equipment can be calibrated.

The signal transmitting link may be turned on to calibrate an amplitude error of the transmitting link under the condition that the first input terminal of the first switching unit is connected with the two positive signal input terminals, the two negative signal input terminals, the second output terminal of the first switching unit is connected with the second input terminal of the second switching unit, and the fourth output terminal of the second switching unit is connected with the amplitude detector. Under the condition that the signal transmitting end is connected with a vector signal source, the amplitude error of the transmitting link of the calibration circuit can be calibrated, and under the condition that the signal transmitting end is connected with calibrated equipment, the amplitude error of the transmitting link of the calibrated equipment can be calibrated.

Under the conditions that the first input end of the first switch unit is connected with the two positive signal input ends and the two negative signal input ends and the first output end of the first switch unit is connected with the signal receiving end, if the signal transmitting end is connected with the vector signal source and the signal receiving end is connected with the vector signal analyzer, the signal receiving link of the calibration circuit can be calibrated, and if the transmitting link and the receiving link of the calibration circuit are calibrated, the signal transmitting end is connected with the signal transmitting end and the signal receiving end is connected with the signal receiving end of the calibrated equipment, and the signal receiving link of the calibrated equipment can be calibrated.

Optionally, in the calibration circuit provided by the embodiment of the present utility model, the first switch unit includes a plurality of single-pole double-throw switches, an input end of each single-pole double-throw switch is a first input end, and output ends of each single-pole double-throw switch are a first output end and a second output end respectively; the second switch unit comprises a plurality of single-pole double-throw switch groups, each single-pole double-throw switch group consists of two single-pole double-throw switches, the fixed contacts of the two single-pole double-throw switches are connected, and the movable contacts of the two single-pole double-throw switches are respectively a second input end, a third output end and a fourth output end of the second switch unit.

Specifically, as shown in fig. 3, the first switching unit may include four single pole double throw switches sp2t_0, sp2t_1, sp2t_2, and sp2t_3, a first input terminal of the first switching unit is composed of a stationary contact of each of the sp2t_0, sp2t_1, sp2t_2, and SP2t_3, a first output terminal is composed of one movable contact of each of the sp2t_0, sp2t_1, sp2t_2, and SP2t_3, and a second output terminal is composed of another movable contact of each of the sp2t_0, sp2t_1, sp2t_2, and SP2 t_3.

The second switch unit may include two single pole double throw switch groups, one single pole double throw switch group is composed of SP2t_4, SP2t_6, the other single pole double throw switch group is composed of SP2t_5, SP2t_7, the fixed contacts of SP2t_4, SP2t_6 are connected, the fixed contacts of SP2t_5, SP2t_7 are connected, the movable contacts of SP2t_4, SP2t_5 are the second input terminal of the second switch unit, the movable contact of SP2t_6 is the third output terminal of the second switch unit, and the movable contact of SP2t_7 is the fourth output terminal of the second switch unit.

Optionally, in the calibration circuit provided by the embodiment of the present utility model, the switch array further includes a third switch unit, where the third switch unit is a single-pole double-throw switch, an input end of the single-pole double-throw switch is connected to the amplitude detector, and an output end of the single-pole double-throw switch is connected to the fourth output end.

Specifically, as shown in fig. 3, the third switch unit is SP2t_8, the movable contact of SP2t_8 is an input terminal, and is connected to the fourth output terminal of the second switch unit, that is, to the movable contacts of SP2t_6 and SP2t_7, and the stationary contact of SP2t_8 is an output terminal, and is connected to the amplitude detector.

In order to facilitate the detection of the calibrated device with high power output and increase the dynamic range of the detection signal, optionally, in the calibration circuit provided by the embodiment of the present utility model, the calibration circuit further includes an attenuation network, which is disposed between the signal transmitting end and the phase amplitude acquisition unit, and is used for performing signal attenuation on the IQ signal output by the signal transmitting end. It should be noted that, in the signal transmitting link, both the phase detector and the amplitude detector have a limitation requirement on the power of the input signal, so the signal to be detected needs to be attenuated by the attenuation network first, and then detected after the signal power reaches the requirement of the detector.

In particular, in case one phase detector and one amplitude detector are provided in the calibration circuit, three attenuation networks may be provided, wherein the first attenuation network is provided between the first input of the phase detector and the second switching unit, the second attenuation network is provided between the second input of the phase detector and the second switching unit, and the third attenuation network is provided between the amplitude detector and the second switching unit.

It should be noted that, to implement the self-calibration of the calibration circuit, the calibration system may further include a vector signal source and a vector signal analyzer.

The vector signal source is connected with an input port of a signal transmitting end of the calibration circuit and is used for providing an IQ signal for the calibration circuit;

the vector signal analyzer is connected with an output port of a signal receiving end of the calibration circuit and is used for acquiring phase information acquisition and amplitude information acquisition of a signal receiving link of the calibration circuit. So that the upper computer stores the phase and amplitude information related to the signal receiving link of the calibration circuit.

Fig. 4 is a schematic diagram of a calibration system according to an embodiment of the utility model. As shown in fig. 4, the system includes:

the calibration circuit in the above embodiment;

The upper computer is in communication connection with the calibration circuit and is used for completing the self calibration and external calibration of the calibration circuit. The external calibration means to calibrate the calibrated equipment externally connected with the calibration circuit.

It should be noted that, the upper computer mainly realizes issuing and obtaining of the waveform file, and interacts with the data of the calibration circuit, after completing the self calibration of the calibration circuit, the external calibration of the calibrated device is completed, the waveform file may be a square wave or a sine wave, and the embodiment does not limit the waveform form.

Optionally, in the calibration system provided by the embodiment of the present utility model, the calibration system further includes a calibrated device, where the calibrated device includes an amplitude modulation unit and a delay unit, the amplitude modulation unit is used to adjust an amplitude of an IQ signal received by the calibrated device when the host computer performs external calibration, and the delay unit is used to adjust a phase of the IQ signal received by the calibrated device when the host computer performs external calibration.

Specifically, after calibration of the calibration circuit is completed, the calibrated device is calibrated through the calibration circuit, a signal transmitting end of the calibration circuit is connected with a signal transmitting end of the calibrated device, and a signal receiving end of the calibration circuit is connected with a signal receiving end of the calibrated device. In fig. 4, the signal transmitting terminal and the signal receiving terminal of the calibrated device are denoted by TRX terminals, and when the calibrated device is calibrated, the TRX terminal of the calibrated device may be connected to the signal transmitting terminal and the signal receiving terminal of the calibration circuit through a radio frequency cable.

Further, after the calibrated device is connected to the calibration circuit through the radio frequency cable, calibration of the signal transmission link of the calibrated device is performed:

the upper computer switches the switch array in the calibration circuit, so that the output port of the signal transmitting end of the calibration circuit is connected with the input end of the PHASE detector, and if the PHASE calibration information of the signal transmitting link stored in the calibration circuit contains AWG_PHASE1, namely, the PHASE difference information output by the data acquisition device under the condition that the calibration circuit inputs the orthogonal constant amplitude signals, the device to be calibrated is controlled to adjust the PHASE difference of the received signals, so that the PHASE difference information output by the data acquisition device is adjusted from AWG_PHASE2 to AWG_PHASE1, and the PHASE calibration of the signal transmitting link of the device to be calibrated is completed.

The upper computer switches the switch array in the calibration circuit to enable the output port of the signal transmitting end of the calibration circuit to be connected with the input end of the amplitude detector, if the amplitude calibration information of the signal transmitting link stored in the calibration circuit contains AWG_MAG1, namely, the amplitude information output by the data acquisition device under the condition that the calibration circuit inputs orthogonal constant amplitude signals, the amplitude of the received signals is controlled to be adjusted by the calibration device, so that the amplitude information output by the data acquisition device is adjusted from AWG_MAG2 to AWG_MAG1, and the amplitude calibration of the signal transmitting link of the calibrated device is completed.

Through the embodiment, IQ signals are sent to the signal transmitting end of the calibration circuit after passing through the signal transmitting link and the radio frequency cable of the calibrated equipment, the switch array is adjusted to enable the signals of the calibrated equipment to be sent to the PHASE detector and the amplitude detector respectively, the calibrated equipment is adjusted to enable the awg_mag2 and the awg_phase2 acquired by the data acquisition unit to be continuously approaching to the awg_mag1 and the awg_phase1 until the signals are equal, the signals sent to the signal transmitting end of the calibration circuit are enabled to be in equal quadrature, and the equal quadrature of the signals output by the signal transmitting link of the calibrated equipment is guaranteed, so that the PHASE calibration and the amplitude calibration of the signal transmitting link of the calibrated equipment are completed.

After the phase calibration and the amplitude calibration of the signal transmitting link of the calibrated device are completed, the calibration of the signal receiving link of the calibrated device is performed:

the upper computer switches the switch array, so that the output ports of the signal transmitting end of the calibration circuit are respectively connected with the input ends of the PHASE detector and the amplitude detector, if the PHASE calibration information of the signal receiving link stored in the calibration circuit comprises DIG_PHASE1 (the PHASE information detected by the PHASE detector when the vector signal analyzer inputs the orthogonal equal-amplitude signal) and DIG_MAG1 (the amplitude information detected by the amplitude detector when the vector signal analyzer inputs the orthogonal equal-amplitude signal), the first amplitude modulation unit and the first delay unit of the calibrated equipment are adjusted, so that the amplitude PHASE information DIG_MAG2 and DIG_PHASE2 acquired by the data acquisition unit are respectively consistent with DIG_1 and DIG_PHASE1, and at the moment, the signal of the signal receiving end of the calibration circuit can be guaranteed to be equal-amplitude orthogonal, and the signal received by the signal receiving link of the calibrated equipment is guaranteed to be equal-amplitude orthogonal. And then the upper computer switches the switch array so that the output port of the signal transmitting end of the calibration circuit is connected with the input port of the signal receiving end of the calibration circuit.

It should be noted that, the signals with equal amplitude are sent to the upper computer through the signal receiving link of the calibrated device, because the influence of the signal receiving link of the calibrated device is introduced, the data obtained by the analysis of the upper computer is not equal amplitude any more, and finally the second amplitude modulation unit and the second delay unit of the calibrated device are adjusted, so that the data obtained by the analysis of the upper computer are equal amplitude and orthogonal.

Through the embodiment, IQ signals are sent to the signal transmitting end of the calibration circuit after passing through the signal transmitting link and the radio frequency cable of the calibrated equipment, the switch array is adjusted to enable the signals of the calibrated equipment to be sent to the PHASE detector and the amplitude detector respectively, firstly, the calibrated equipment is adjusted to enable the DIG_MAG2 and DIG_PHAS2 of data acquisition to be close to the DIG_MAG1 and the DIG_PHAS1 until the signals are equal, the fact that the signals received by the signal receiving link of the calibrated equipment are equal in amplitude orthogonality is guaranteed, further, the calibrated equipment is adjusted again, and the upper computer is enabled to finally analyze the obtained data to be equal in amplitude orthogonality, so that the calibration of the receiving link of the calibrated equipment is completed.

It should be noted that, the amplitude calibration and the phase calibration are implemented by an amplitude modulation unit and a delay unit in the calibrated device, where the amplitude modulation unit may include a first amplitude modulation unit and a second amplitude modulation unit, and the delay unit may include a first delay unit and a second delay unit, where the first amplitude modulation unit is used to adjust the amplitude of the IQ signal to be sent by the calibrated device, the second amplitude modulation unit is used to adjust the amplitude of the received IQ signal of the calibrated device, the first delay unit is used to adjust the phase of the IQ signal to be sent by the calibrated device, and the second delay unit is used to adjust the phase of the received IQ signal.

It should be noted that the calibrated device further includes: the digital module is used for converting the waveform file issued by the upper computer into a corresponding waveform code value, transmitting the waveform code value to the analog module and converting the waveform code value sent by the analog module into the waveform code value, wherein the first amplitude modulation unit, the second amplitude modulation unit, the first delay unit and the second delay unit are arranged on the digital module, the first amplitude modulation unit and the first delay unit are used for transmitting the waveform code value to the analog module after being regulated, and the second amplitude modulation unit and the second delay unit are used for transmitting the waveform code to the upper computer after being regulated; the analog module is connected with the digital module and is used for converting the waveform code value sent by the digital module into an analog signal and sending the analog signal through the signal transmitting end, and is also used for converting the analog signal received by the signal receiving end into the waveform code value and sending the waveform code value to the digital module.

Specifically, the digital module functions as follows: receiving a waveform file issued by an upper computer, converting the waveform file into a corresponding waveform code value, and transmitting the waveform code value to an analog module; and receiving the waveform code value transmitted by the analog module, converting the waveform code value into the waveform code value, and transmitting the waveform code value to the upper computer. The analog module mainly realizes the conversion of digital signals and analog signals, completes the transmission of the analog signals in the calibrated equipment, and transmits the analog signals at the signal transmitting end and receives the analog signals at the signal receiving end.

The digital module controls the first amplitude modulation unit and the first delay unit to sequentially adjust amplitude information and delay information of an output waveform code value according to amplitude-phase mismatch information fed back by a data acquisition unit on a calibration circuit when the signal transmission link of calibrated equipment is calibrated, so that IQ signals output by a signal transmitting end keep equal-amplitude orthogonality. When the signal receiving link of the calibrated equipment is calibrated, the digital module controls the second amplitude modulation unit and the second delay unit to sequentially adjust amplitude information and delay information of waveform code values input into the upper computer according to amplitude-phase mismatch information fed back by the data acquisition unit on the calibration circuit, so that IQ signals acquired by the upper computer keep equal-amplitude orthogonality.

Next, taking as an example the calibration for a 1T1R device to be calibrated (i.e., the device to be calibrated is connected to a vector signal tester including a signal transmitting end and a signal receiving end), the entire calibration process of calibrating the device to be calibrated by a calibration circuit (i.e., a vector signal calibration circuit) is described.

Since the signal transmitting link and the signal receiving link of the calibration circuit themselves also introduce phase errors and amplitude errors into the transmission signal, the vector signal source and the vector signal analyzer are connected to the calibration circuit to calibrate the calibration circuit before the device to be calibrated is connected to the calibration circuit.

FIG. 5 is a schematic diagram of amplitude calibration of a signal transmitting link of a calibration circuit in an embodiment of the utility model, as shown in FIG. 5, an upper computer is respectively connected with a vector signal source, a vector signal analyzer and the calibration circuit through control lines; the differential IQ output port of the vector signal source is connected with the signal transmitting end of the calibration circuit; the differential IQ input port of the vector signal analyzer is connected with the signal receiving end of the calibration circuit.

When the amplitude calibration of the signal transmitting link of the calibration circuit is carried out, the upper computer is used for controlling the vector signal source to output constant-amplitude orthogonal differential IQ signals, namely an I+ signal, a Q+ signal, an I-signal and a Q-signal, and simultaneously, the upper computer is used for controlling the switch on the calibration circuit to enable the output signals of the vector signal source to be sequentially and respectively sent into the amplitude detector. The amplitude detector sends the detected amplitude information to the data collector, the data collector converts the input signal of the amplitude into a digital signal and transmits the digital signal to the upper computer, the upper computer records the output signal amplitude of the vector signal source and the output amplitude information (AWG_MAG1) of the data collector, and the information is stored as amplitude calibration information of the signal transmitting link to the storage unit.

Fig. 6 is a schematic diagram of phase calibration of a signal transmitting link of a calibration circuit in an embodiment of the present utility model, as shown in fig. 6, when phase calibration of the transmitting link of the calibration circuit is performed, an upper computer is used to control a vector signal source, so that the vector signal source outputs equal-amplitude orthogonal differential IQ signals, i.e., an i+ signal, a q+ signal, an I-signal, and a Q-signal, and simultaneously, a switch on the calibration circuit is controlled by the upper computer to enable output IQ signal pairs of the vector signal source to be respectively sent to a phase detector in sequence, where the output IQ signal pairs are i+ signals, q+ signals, or I-signals, Q-signals. The phase detector sends the detected phase information into the data collector, wherein the phase information is a phase difference signal of an output IQ signal pair, and finally the data collector converts the phase difference signal into a digital signal and transmits the digital signal to the upper computer. The upper computer records the PHASE difference of the output signals of the vector signal source and the PHASE information (AWG_PHASE 1) output by the data collector ADC, and saves the information to the storage unit as the PHASE calibration of the signal transmitting link.

Fig. 7 is a schematic diagram of amplitude calibration and phase calibration of a signal receiving link of a calibration circuit in an embodiment of the present utility model, as shown in fig. 7, when calibration of the signal receiving link of the calibration circuit is performed, an upper computer is used to control a vector signal source, so that the vector signal source outputs equal-amplitude orthogonal differential IQ signals, and simultaneously, an upper computer is used to control a switch on the calibration circuit, so that output IQ signal pairs of the vector signal source are sequentially sent to a vector signal analyzer respectively. The output signal amplitude and the PHASE difference information of the vector signal source and the PHASE difference and the signal amplitude (DIG_PHASE 1 and DIG_MAG1) obtained by the vector signal analyzer are stored in a storage unit as amplitude calibration information and PHASE calibration information of a signal receiving link.

The calibration of the calibration circuit itself is completed through the above steps, and the calibrated device is calibrated by means of the calibrated calibration circuit.

As shown in fig. 4, the port of the signal transmitting end of the device to be calibrated and the port of the signal transmitting end of the calibration circuit are connected by a cable, and the signal receiving end of the device to be calibrated and the signal receiving end of the calibration circuit are connected.

When the signal transmitting link of the calibrated equipment is calibrated, firstly, the upper computer controls the calibrated equipment so that the calibrated equipment outputs IQ signals with orthogonal constant amplitude. Then, the upper computer controls the switch array on the calibration circuit to sequentially detect the amplitude and phase information of the IQ signal output by the calibrated equipment. Because of differences of internal devices, PCB layout and the like of the calibrated equipment, IQ signals of the signal transmitting end of the calibrated equipment are not in orthogonal constant amplitude, and at the moment, PHASE information and amplitude information obtained by the data acquisition device are AWG_PHASED2 and AWG_MAG2 respectively. Finally, a first amplitude modulation unit, namely a first amplitude modulation Block, and a first delay unit, namely a first delay Block, in the calibrated equipment are adjusted through the upper computer until amplitude information and PHASE information obtained by a data collector ADC in a calibration circuit are respectively consistent with AWG_MAG1 and AWG_PHAS1, and then calibration of a signal transmitting link of the calibrated equipment is completed.

When the signal receiving link of the calibrated equipment is calibrated, firstly, the upper computer adjusts the first amplitude modulation Block and the first delay Block of the calibrated equipment by calling DIG_PHAS1 and DIG_MAG1 information of a storage unit of the calibration circuit, so that amplitude and PHASE information DIG_MAG2 and DIG_PHAS2 acquired by the data device are respectively consistent with DIG_MAG1 and DIG_PHAS1, and IQ signals input into the signal receiving link of the calibrated equipment are ensured to be in orthogonal constant amplitude. Then, the upper computer controls the switch array of the calibration circuit again, so that the output signal of the calibrated equipment loops back to enter the signal receiving link of the calibrated equipment. Although the IQ signals input to the signal receiving link of the calibrated device are of equal amplitude quadrature, because of the influence of the signal receiving link of the calibrated device (differences in internal components of the calibrated device, PCB layout, etc.) introduced, the IQ signals actually received by the upper computer are no longer of equal amplitude quadrature. And adjusting a second amplitude modulation unit, namely a second amplitude modulation Block, and a second delay unit, namely a second delay Block, of the calibrated equipment, so that the IQ signal of the calibrated equipment finally presents orthogonal equal amplitude, namely, the data obtained by the upper computer analysis are orthogonal in equal amplitude, and the signal receiving link calibration of the calibrated equipment is completed.

After the internal calibration of the calibration circuit is completed through the vector signal source and the vector signal analyzer, the calibration is performed on the calibrated equipment which is already in use, on the one hand, even if the client cannot provide the vector signal source and the vector signal analyzer, the phase calibration information and the amplitude calibration information stored during the calibration before the calibration circuit can be called to complete the calibration of the calibrated equipment. On the other hand, when the calibration circuit is used for calibrating the calibrated equipment, the automatic test of the calibrated equipment can be realized through the upper computer only by correctly connecting the TRX end of the calibrated equipment with the signal transmitting end and the signal receiving end of the calibration circuit, the port calibration does not need to be manually switched, the calibration efficiency is improved, meanwhile, the uncertainty error caused by repeated connection or plugging is avoided, and the calibration precision is improved.

The foregoing is merely exemplary of the present utility model and is not intended to limit the present utility model. Various modifications and variations of the present utility model will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the utility model are to be included in the scope of the claims of the present utility model.

Claims (10)

1. A calibration circuit in communication with a host computer for performing self calibration and external calibration of the calibration circuit, comprising:

the signal transmitting end is used for outputting an IQ signal;

the phase amplitude acquisition unit is connected with the signal transmitting end through a switch array and is used for carrying out phase information acquisition or amplitude information acquisition on the IQ signal output by the signal transmitting end so as to calibrate the signal transmitting link by the upper computer;

the signal receiving end is connected with the signal transmitting end through the switch array and is used for outputting an IQ signal so as to enable the upper computer to calibrate a signal receiving link;

the signal transmitting link refers to a link formed by devices from the signal transmitting end to the phase amplitude acquisition unit, and the signal receiving link refers to a link formed by devices from the signal transmitting end to the signal receiving end.

2. The calibration circuit of claim 1, wherein the phase amplitude acquisition unit comprises:

the phase detector is connected with the signal transmitting end and is used for detecting the phase difference value between IQ signals;

and the amplitude detector is connected with the signal transmitting end and is used for respectively detecting the amplitude of the IQ signal.

3. The calibration circuit of claim 2, wherein the phase amplitude acquisition unit comprises: the data acquisition device is electrically connected with the phase detector and the amplitude detector, and is used for receiving the phase information acquired by the phase detector and the amplitude information acquired by the amplitude detector, uploading the amplitude information and the phase information to the upper computer, and storing the phase information and the amplitude information sent by the upper computer.

4. The calibration circuit of claim 2, wherein the phase detector comprises a first input and a second input, the signal emitting terminal comprises two positive signal inputs and two negative signal inputs, the switch array is configured to communicate the two positive signal inputs with the first input and the second input, respectively, or to communicate the two negative signal inputs with the first input and the second input, respectively; or alternatively, the first and second heat exchangers may be,

the switch array is used for gating the signal transmitting end and the amplitude detector so that the two positive signal input ends and the two negative signal input ends are respectively communicated with the amplitude detector.

5. The calibration circuit of claim 4, wherein the switch array comprises a first switch unit comprising a first input, a first output, and a second output, a second switch unit comprising a second input, a third output, and a fourth output;

the first input end of the first switch unit is connected with the two positive signal input ends and the two negative signal input ends, the first output end of the first switch unit is connected with the signal receiving end and is used for conducting a signal receiving link, and the second output end of the first switch unit is connected with the second input end of the second switch unit and is used for conducting the signal transmitting link;

the third output end of the second switch unit is connected with the phase detector, the fourth output end of the second switch unit is connected with the amplitude detector, and the second switch is used for gating the second input end, the third output end and the fourth output end, and then conducting the signal transmitting link.

6. The calibration circuit of claim 5, wherein the first switch unit comprises a plurality of single pole double throw switches, the input of the single pole double throw switch being the first input, the output of the single pole double throw switch being the first output, the second output, respectively;

The second switch unit comprises a plurality of single-pole double-throw switch groups, the single-pole double-throw switch groups are composed of two single-pole double-throw switches, the fixed contacts of the two single-pole double-throw switches are connected, and the movable contacts of the two single-pole double-throw switches are the second input end, the third output end and the fourth output end of the second switch unit respectively.

7. The calibration circuit of claim 5 or 6, wherein the switch array further comprises a third switch unit, the third switch unit being a single pole double throw switch, an output of the single pole double throw switch being connected to the amplitude detector, an input of the single pole double throw switch being connected to the fourth output.

8. The calibration circuit of any one of claims 1-6, further comprising an attenuation network disposed between the signal transmitting terminal and the phase amplitude acquisition unit for signal attenuation of IQ signals output by the signal transmitting terminal.

9. A calibration system, comprising:

the calibration circuit of any one of claims 1 to 8;

the upper computer is in communication connection with the calibration circuit and is used for completing self calibration and external calibration of the calibration circuit.

10. The system of claim 9, further comprising a calibrated device, wherein the calibrated device comprises an amplitude modulation unit for adjusting an amplitude of an IQ signal received by the calibrated device when the host computer performs external calibration, and a delay unit for adjusting a phase of the IQ signal received by the calibrated device when the host computer performs external calibration.