CN220172100U - Packaging box, packaging assembly and quantum computer - Google Patents

Abstract

The utility model discloses a packaging box, a packaging assembly and a quantum computer, and belongs to the field of quantum chip manufacturing. The package box includes a box body, a base pad integrated into the box body, and an adapter. Wherein the case is capable of configuring a chip and the chip is connected to the base pad through the adapter. The packaging box can avoid the problem that the length of a signal line is too large caused by direct connection between the chip and the packaging box, thereby inhibiting the signal loss introduced by a connecting line.

Description

Packaging box, packaging assembly and quantum computer

Technical Field

The utility model belongs to the field of quantum information, in particular to the technical field of quantum computing, and particularly relates to a packaging box, a packaging assembly and a quantum computer.

Background

Quantum computers are physical devices that perform quantum computation based on quantum mechanics laws. As an important component of a quantum computer, a quantum chip is a relatively fragile component, and thus is extremely susceptible to various noises, thereby resulting in signal transmission in the quantum chip and performance being affected. Therefore, the quantum chip is packaged based on practical use considerations.

Due to limitations of practical manufacturing processes, equipment and the like, when packaging a quantum chip, there is a serious problem of insertion loss of signal lines between the chip and a package box.

Disclosure of Invention

Examples of the present utility model provide an enclosure, an enclosure assembly, and a quantum computer. The scheme can avoid the direct connection of the chip and the packaging box, so that the insertion loss introduced by the connection circuit between the chip and the packaging box can be reduced through a relatively shorter signal connection circuit.

The exemplary embodiment of the present utility model is implemented as follows.

In a first aspect, an example of the present utility model proposes a packaging box.

The package box includes:

a case having a mounting groove configured to mount a chip;

a base pad and an adapter integrated to the case, the adapter having a first transfer pad and a second transfer pad connected to each other and electrically conductive and configured in pairs;

the adapter is positioned between the mounting slot and the base pad such that the first adapter pad is proximate the mounting slot and the second adapter pad is proximate the base pad.

By disposing the adapter in the package box, the direct connection between the chip disposed to the box and the base pad can be changed to be mediated by the adapter. Therefore, when the length of the direct connection line between the chip and the base pad is greater than the length of the connection line between the chip and the first transfer pad of the adapter, and at the same time, the length of the connection line between the second transfer pad of the adapter and the base pad of the box body is greater.

Therefore, by avoiding direct line connection (such as direct connection) of the signal port of the chip and the base pad of the box body, indirect line connection of the signal port of the chip and the base pad of the box body is realized by selecting the adapter as a 'springboard', thereby realizing the insertion loss of the connection line between the signal port and the base pad.

According to some examples of the utility model, the case is of metal;

and/or the box body is made of superconductor materials which are in a superconducting state below a preset critical point temperature;

and/or the number of the basic bonding pads is equal to the number of the first transfer bonding pads;

and/or the base bonding pad is positioned at the edge of the box body;

and/or the mounting groove is a through groove penetrating along the thickness direction of the box body;

and/or the adapter is a printed circuit board;

and/or the basic bonding pads are provided with a plurality of bonding pads and form a first bonding pad group, the bonding pads in the first bonding pad group are arranged in a one-dimensional linear manner, and the first transfer bonding pads are provided with a plurality of bonding pads and are sequentially arranged along the arrangement direction of the bonding pads in the first bonding pad group.

According to some examples of the utility model, the mounting groove has a depth, and the depth depends on the thickness of the chip.

According to some examples of the utility model, the mounting slot is configured to: the mounting groove depth is consistent with the chip thickness so that the top surface is flush with the top surface of the case when the chip is placed in the mounting groove.

In a second aspect, an example of the present utility model provides a package assembly. It comprises the following steps:

the aforementioned package box; and

the chip is configured in the mounting groove, the signal contact of the chip is electrically connected to the first transfer bonding pad, and the second transfer bonding pad is electrically connected to the base bonding pad.

In a third aspect, an example of the present utility model proposes a packaging box comprising:

the box body is provided with a placement hole for configuring the chip;

a conductor pad and a base fixedly connected to the case; and

a middleware coupled to the base, the middleware configured with electrically conductive and paired first and second pads;

wherein the first bonding pad is close to the placement hole, and the second bonding pad is close to the conductor pad.

According to some examples of the utility model, the placement hole is a through hole in a thickness direction of the case;

and/or, the middleware is detachably connected with the base;

and/or the number of conductor pads is greater than the number of first pads;

and/or the intermediate piece is a printed circuit board;

and/or the box body is provided with a rectangular outline projected in the thickness direction, the conductor pads are provided with a plurality of four sides which are distributed to the rectangular outline, the bases and the middle piece are provided with the same number and four, and the four bases are distributed in one-to-one correspondence to the four sides of the rectangular outline.

In a fourth aspect, an example of the present utility model proposes a package assembly comprising:

the above-mentioned packaging box; and

the chip is configured in the placement hole, the signal port of the chip is electrically connected to the first bonding pad, and the second bonding pad is electrically connected to the conductor pad.

In a fifth aspect, an example of the present utility model proposes a package assembly comprising:

an enclosure defining a first region, a second region surrounding the first region, and a third region surrounding the second region;

the first bonding pad and the second bonding pad are configured in the second area, and the third bonding pad is configured in the third area;

a chip disposed in the first region; and

the signal port of the chip is connected to the first lead of the first pad and the second pad is connected to the second lead of the third pad.

In a sixth aspect, examples of the utility model provide a quantum computer comprising the enclosure, or package, of the foregoing items.

The scheme of the utility model has at least the following effects:

when the quantum chip is packaged by the package box, various signals for realizing the operation of the quantum bit (control and reading) are transmitted by the package box. Therefore, the chip and the package box are connected through the signal line. If the difference between the chip size and the package size is large, the signal line between the two is relatively long, thus exhibiting large insertion loss. Thus, in the exemplary embodiment of the utility model, the direct connection of the chip and the package is adjusted to be an intermediate connection. Namely, the chip is connected with a component, and then is connected with the packaging box through the component, so that the excessively high insertion loss introduced during the signal connection of the chip and the packaging box is reduced.

Drawings

For a clearer description, the drawings that are required to be used in the description will be briefly introduced below.

Fig. 1 is a schematic structural diagram of a chip and a package box in the related art directly connected through a long wire;

FIG. 2 is a schematic view of the structure of a case in the package according to the example of the present utility model;

FIG. 3 is a schematic structural view of a package assembly based on the case of FIG. 2 in an example of the present utility model;

FIG. 4 is a schematic structural view of another package assembly based on the case of FIG. 2 according to an example of the present utility model;

fig. 5 shows a schematic diagram of the distribution of different areas of the enclosure in an example of the utility model.

Reference numerals illustrate: 100-packaging the assembly; 200-packaging the box; 101-a box body; 102-a mounting groove; 103-an adapter; 1031-a second transfer pad; 1032—a first transfer pad; 104-a first set of pads; 1041-base pads; 1051-first line; 1053-third line; 201-an inner layer; 202-an intermediate layer; 203-an outer layer; 301-chip.

Detailed Description

When a multi-bit quantum chip is packaged, since the number of quantum bits in the chip is large, control lines, measurement lines, signal input/output ports, and the like arranged in accordance with the number of quantum bits are also large. Also, a corresponding number of ports are required in the package structure. In order to derive or introduce signals from the quantum chip, it is necessary to connect the ports of the quantum chip and the ports of the package structure. Therefore, the signal of reading and controlling the quantum bit and the output signal of the quantum chip after quantum computation can be transmitted through other external devices connected with the packaging structure.

However, since the package structure of the quantum chip has a size significantly larger than that of the quantum chip, it is understood that there are significant differences and differences in the arrangement position and the structural size of the ports in the quantum chip and the ports of the package structure. Therefore, when packaging the quantum chip, it is necessary to use a long line, signal line, transmission line, or the like to connect the ports of the quantum chip and the quantum chip.

The inventors have found that the use of longer wires may be cumbersome to handle during the connection process. Such as line collapse, may make undesirable contact with other components. Alternatively, the wiring is liable to break, or a plurality of wirings are in contact with each other, or the like.

Furthermore, it is more important that the use of too long a line may also result in the introduction of severe insertion loss. Which may lead to problems of distortion or errors, loss, etc. of the signal operating on the qubit.

In order to overcome or weaken the above-described problems, the inventors consider that the following may be adopted: for example, making the chip size larger, but increasing the quantum chip size can be difficult; such as the fabrication of large-sized quantum chips, may exceed the capabilities of existing processes (e.g., exceed the field of view of the lithography machine), and generally the larger the quantum chip size, the lower the yield. In addition, the size of the package structure is shortened or reduced, however, the size thereof is generally predetermined or is not easily adjusted and modified.

Thus, in view of such realistic constraints, in the present example, the inventors have chosen to "zero out" the longer line from the chip port to the package structure port. That is, the longer line is configured in a multi-stage structure by the intermediate structure; thus, in such a modification, there is no longer line, but rather there are a plurality of shorter lines. Thus, the exemplary approach presented by the inventors enables controlling excessive insertion loss of the line introduction between the package structure and the ports of the chip.

It will be appreciated that in an example, then, the inventors propose an intermediate structure. With this intermediate structure, the chip port can be connected to the intermediate structure, while the package structure port can also be connected to the intermediate structure. I.e. the wires are led out from the chip port and the package structure port, respectively, and then connected to the intermediate structure. The continuous long line is cut off by the intermediate structure, and the switching is realized. In other words, the connection scheme between the chip port and the package structure port is optimized in the scheme of the embodiment of the present utility model, so that the continuous long line used for realizing direct connection in the connection line routing is changed into a plurality of discontinuous short lines.

For ease of understanding, an example is given of connecting a chip port and a package structure port using a long line for implementing direct connection, please refer to fig. 1.

In view of the above, the inventor adopts the intermediary structure to transfer as described above, so as to solve the related problems such as large insertion loss partially or completely. The solution in the examples will be described in detail below with reference to the accompanying drawings.

In some examples, the inventors propose a packaging box 200 for packaging a chip 301.

The package 200 includes a case 101, base pads 1041 and an adapter 103 (which may be implemented, for example, as a printed circuit board/PCB) integrated to the case 101. Generally, the cassette 101 is used to configure the chip 301 (e.g., quantum chip 301, which may be various types of superconducting quantum chips 301, or semiconductor chips 301). The base pads 1041 may serve as ports for the package 200. The adapter 103 may be used as an intermediary structure. Both the chip 301 and the package 200 may be connected to the adapter 103.

Wherein the cassette 101 has a substantially block-like structure, such as a rectangular parallelepiped. The cartridge 101 has a mounting slot 102 configured to receive a chip 301. The mounting groove 102 may be a blind hole or a through hole provided in the thickness direction of the case 101 (or may be described as a through groove in which the mounting groove 102 penetrates in the thickness direction of the case 101). Also, the mounting groove 102 is shaped to be able to accommodate, or at least partially accommodate, the chip 301. Thus, in general, the shape of the mounting groove 102 is selected to conform to the shape of the chip 301. For example, from the perspective of the chip 301, the chip 301 has a substantially rectangular or square shape. Therefore, the mounting groove 102 also has a rectangular or square shape measured in the thickness direction of the case 101.

The case 101 may alternatively be configured in a unitary structure, or the case 101 may alternatively be configured in a split structure. For example, the case 101 is designed in multiple layers, and different layers may be designed in different structures or materials, sizes, etc. according to different functions or needs.

For example, as an example of a case 101 of a split design, the case 101 may have a bolted base and cover (the cover may be provided in other structures of a quantum processor quantum computer, but is not necessary in the enclosure 200). A recess is provided in the base for receiving the chip 301. The cover plate may then be connected to the base. The cover plate is located at the upper part of the groove and covers the chip 301 to isolate it from damage. It will thus be appreciated that the base and cover plate are in mating engagement, and a sealed cavity may be formed at the location of the recess to accommodate the chip 301. Further, the bottom plate is provided with an interaction and transmission structure with external equipment and a signal source; for example, a structure that mates with a coaxial cable.

Based on the application in the superconducting quantum chip 301, the case 101 may be a superconductor material in a superconducting state below a preset critical point temperature. The preset critical point temperature is mainly the temperature when the critical structure of the superconducting quantum chip 301, which is based on qubits of the josephson junction, is in a superconducting state.

Thus, as an example, the case 101 may employ a material having a superconducting state below mK (milli-kelvin) temperature. The material of the case 101 may be aluminum, niobium, indium, tantalum, tin, vanadium, or the like. The box 101 can effectively isolate the superconducting quantum chip 301 from the external environment through the superconducting characteristic at low temperature, and shield the noise of the external environment and reduce the energy loss, so that the coherence of the quantum bit in the superconducting quantum chip 301 is better maintained, and the unwanted decoherence is avoided.

In other examples, the case 101 may be selected from a metal material such as copper (gold-plated red copper), an alloy such as aluminum alloy 6061, and the like. Alternatively, in still other examples, the case 101 may be made of a non-metal material, such as an organic material, and include, but not limited to, resin.

In fig. 2, a case 101 having a substantially rectangular planar structure is exemplified, which has a mounting groove 102 located near the intersection of its middle/two diagonals. The mounting groove 102 has a shape substantially conforming to the case 101; in this example, the mounting slot 102 is a blind hole structure having a bottom wall. In other examples, the mounting slot 102 may also be configured as a through-hole structure without a bottom wall.

Typically, the mounting groove 102 has a depth, and the depth is dependent on the thickness of the chip 301. For example, the depth is greater than the thickness of the chip 301, and thus, the chip 301 may sink into the mounting groove 102; i.e. the top of the chip 301 may be below the top surface of the later mentioned cartridge 101. As such, when the port of the chip 301 is connected to the adapter 103, excessive bending of the line may occur; and thus may be detrimental to the configuration, life of the line. In view of this, in some examples, the depth of the mounting groove 102 is intentionally selected such that the mounting groove 102 is of a depth consistent with the thickness of the chip 301, and thus such that the top surface is flush with the top surface of the case 101 when the chip 301 is placed in the mounting groove 102. This avoids excessive bending of the wires in the vicinity of the port away from the chip 301.

In the example, the case 101 has a top surface and a bottom surface in the thickness direction, and thus the mounting groove 102 is a structure recessed from the top surface to the inside of the case 101 to a partial thickness. On this basis, the case 101 integrates a base pad 1041 and an adapter 103. In some examples, both base pad 1041 and interposer 103 may alternatively be configured to a top surface, for example, or to a bottom surface. Or in yet other examples, the mounting slot 102 is on one surface and the base pad 1041 and the adapter 103 are on the other surface; i.e. the out-of-plane scheme. In a heterofacial scheme, it may be desirable to use different structures of connections such as vias and wires to make the heterofacial.

In addition, the adaptor 103 in the package can 200 has a first transfer pad 1032 and a second transfer pad 1031 existing in pairs; thus, it can be appreciated that the number of first transfer pads 1032 is the same as the number of second transfer pads 1031. The first transfer pad 1032 and the second transfer pad 1031 are also connected to each other, and electrical conduction is achieved.

As can be seen from the above description, the base pad 1041 is bonded to the case 101. The base pad 1041 may be provided to various suitable positions of the cartridge as needed, and the present utility model is not particularly limited thereto. In general, the base pad 1041 may alternatively be located at an edge of the case 101. Of course, other locations may alternatively be provided, for example, relatively closer to the mounting slot 102/away from the edges of the cassette 101, as desired.

In addition, in this package case 200, the connection position of the adapter 103 and the case 101 is selected. Thus, the adapter 103 is positioned and is positioned between the mounting slot 102 and the base pad 1041 in such a way that the first transfer pad 1032 is proximate to the mounting slot 102 and the second transfer pad 1031 is proximate to the base pad 1041.

Thus, if it is desired to connect a port of the chip 301 with a port of the cartridge 101 (base pad 1041 in the example), the port of the chip 301 may be connected (capable of transmitting signals, electrical signals, microwave signals, etc.) with the first transfer pad 1032 of the adapter 103; meanwhile, the second transfer pad 1031 may be connected (capable of transmitting a signal, an electrical signal, a microwave signal, etc.) to the base pad 1041. Thus, the first transfer pad 1032 and the second transfer pad 1031 are disposed to the adapter 103, and are connected to the case 101 and the chip 301 through the adapter 103, respectively, thereby indirectly bonding the chip 301 and the case 101.

On the premise of the above scheme, the long line that would exist when the port of the chip 301 and the port of the case 101 are directly connected may be replaced by three relatively shorter lines. The three-section line includes, for example: a line/first line 1051 between the port of the chip 301 and the first transfer pad 1032 of the adapter 103; a line/second line between the first transfer pad 1032 and the second transfer pad 1031; a line/third line 1053 between the second transfer pad 1031 and the base pad 1041. Wherein the first line 1051 and the third line 1053 may be selected to be explicitly exposed in the enclosure 200, while the second line may be implicitly incorporated into the enclosure 200 by being configured by the switch 103.

In addition, in the case where the chip 301 port and the case 101 port are mated, the number of pads may be selected according to the manner of mating the two. For example, one chip 301 port is designed to correspond to one cartridge 101 port. Then, in some examples, the number of the base pads 1041 may be designed to be equal to the number of the first transfer pads 1032. In yet other examples, the number of base pads 1041 may be greater than the number of first transfer pads 1032. Alternatively, for functional or other purposes, the number of base pads 1041 may be selected to be less than the number of first transfer pads 1032; in these examples there may be multiplexing of some ports and accordingly the signals transmitted by the ports may also be designed to be multiplexed and subsequently, if desired, to separate two or more different signals from the multiplexed signal.

In the case of having a plurality of base pads 1041, these base pads 1041 may be grouped to constitute the first pad group 104. Further, the pads in the first pad group 104 are arranged in a one-dimensional line. Meanwhile, correspondingly, the first transfer pads 1032 may be provided in plurality and sequentially arranged along the arrangement direction with the respective pads in the first pad group 104. Similarly, a corresponding plurality of first transfer pads 1032 may alternatively be arranged in order along the arrangement direction of the pads in the first pad group 104.

As an application example of the package can 200 in the above example, the present utility model also discloses a package assembly 100. Package assembly 100 includes package box 200 and chip 301. Wherein the chip 301 is disposed in the mounting slot 102 of the package can 200. And the signal contacts of the chip 301 are electrically connected (e.g., soldered) to the first transfer pads 1032, and the second transfer pads 1031 are electrically connected (e.g., soldered) to the base pads 1041; please refer to fig. 3.

In another example of the present utility model, another enclosure 200 is disclosed that includes a box 101, an intermediate piece, and a conductor pad and base fixedly connected to the box 101. The structure and function of which may be understood in conjunction with the foregoing enclosure 200 and, in part, will be more clearly set forth in the following description.

Wherein, the case 101 is provided with a placement hole for configuring the chip 301. The shape of the case 101 may have a structure and shape compatible with the chip 301. For example, for the semiconductor chip 301, the case 101 may be of a configuration having a printed circuit board; for example, for superconducting quantum chip 301, the cassette 101 may have a substantially block-like structure.

As an alternative example, the case 101 may be a structure having a rectangular cross-sectional shape. Therefore, the case 101 of this shape has a rectangular outline projected in the thickness direction. The configuration may be selected such that the number of conductor pads of the case 101 is plural in consideration of the numerous ports the chip 301 has, and these conductor pads are distributed to four sides of the rectangular outline of the case 101. Suitably, the base and the intermediate member are of the same number and are four; the four bases are distributed in one-to-one correspondence with the four sides of the rectangular outline.

In addition, the intermediate piece is coupled (e.g., detachably coupled such as by plugging, suction, adhesive, etc., or fixedly coupled) to the base. And the middleware is configured with electrically conductive and paired first and second pads. Of the pads, a first pad is close to the placement hole, and a second pad is close to the conductor pad. The base and the intermediate member may be a plug and a socket constituting a connector. Alternatively, the intermediate member may be the aforementioned printed circuit board.

The placement hole therein may be a through hole of the case 101 in the thickness direction. Wherein the number of conductor pads may be greater than the number of first pads; thus, for chips 301 having different numbers of ports and appropriate numbers of ports, the enclosure 200 may provide sufficiently matched port connection points through the conductor pads.

As an example of application of the package 200 described above, another package assembly is disclosed. The package assembly includes: the package 200 and the chip 301 are packaged. The chip 301 is disposed in the placement hole of the case 101, and the signal port of the chip 301 is electrically connected to the first pad, and the second pad is electrically connected to the conductive pad. Taking as an example two bases and two corresponding middleware, the structure of the package assembly is exemplarily depicted in fig. 4. It is appreciated that in other examples, if the chip 301 also has more ports, the package box 200 may be configured with more pads, conductor pads, middleware, pedestals, etc.

As can be seen from the foregoing analysis, in order to provide a reduced insertion loss of the package of the chip 301, which is introduced by the connection (e.g., bonding wire) of different components, the inventors propose a package assembly. The package assembly includes the package case 200 and other components (not shown), namely, a first pad, a second pad, a chip 301, a first lead, and a second lead.

To facilitate positioning of other components relative to the enclosure 200, a first region, a second region, and a third region may be defined in the enclosure 200 (e.g., a top surface). Wherein the second region surrounds the first region and the third region surrounds the second region; as shown in fig. 5. Thus, the first region may be described simply as the inner layer 201, the second region as the intermediate layer 202, and the third region as the outer layer 203.

In the assembly of the package assembly, the first and second pads are fixed to the second region, for example, by constructing the package can 200 in the form of a circuit board, and the pads may be metal bumps or bumps on the surface of the circuit board. The first and second pads may be electrically conductive through a printed circuit in the package box 200; alternatively, the first and second pads may be signal conductive through wires fabricated in the package can 200 using micro-sodium processing techniques such as deposition, etching, stripping, etc. Meanwhile, the third bonding pad is configured in the third area.

Based on the above structure, the chip 301 is fixed to the first region. While a first wire connects the signal port of the chip 301 to the first pad and a second wire connects the second pad to the third pad.

Since superconducting quantum chip 301 is very sensitive to noise within various environments or systems, such as thermal noise, electromagnetic noise, etc., the noise may result in quantum computation failure or error if not well controlled. In addition, various off-targets of signals operating on, and controlling, the qubits also affect or degrade the quantum computing performance of the quantum chip 301 to a significant extent. Where the insertion loss introduced by the lines of the input or output signals of the signal ports of the chip 301 can similarly have a negative impact.

Thus, in an example, a quantum computer may be implemented based on the foregoing schemes, which may have the foregoing enclosure 200, as well as other quantum chip 301 cooling systems, maintenance systems, control and read operating systems, and so forth. The enclosure 200 in these examples may optionally be used in a manner different from that in the enclosure components and integrated into the corresponding system or function/structural module of the computer. Alternatively, in other examples, the quantum computer may also have the aforementioned packaging components.

In general, the exemplary embodiment may employ a chip 301 processing technology, and a two-level package of a switching device for bonding is disposed between the chip 301 and the package box 200, so that the chip 301 and the package box 200 are indirectly connected, rather than directly connected, by relatively shorter (possibly more) wires without extending the size of the chip 301, to implement microwave communication and electrical conduction, so that the insertion loss represented by these wires is smaller. In addition, the connection/bonding operation of the circuit can be more convenient, the difficulty of packaging the chip 301 is reduced, and the success rate and the yield of packaging the chip 301 are improved.

The embodiments described above by referring to the drawings are exemplary only for explaining the present utility model and are not to be construed as limiting the present utility model.

For purposes of clarity, technical solutions, and advantages of embodiments of the present utility model, one or more embodiments have been described above with reference to the accompanying drawings. Wherein like reference numerals are used to refer to like elements throughout. In the description above, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of one or more embodiments. It may be evident, however, that one or more embodiments may be practiced without these specific details, and that such embodiments may be incorporated by reference herein without departing from the scope of the claims.

It should be noted that the terms "first," "second," "third," and the like in the description and the claims of the present utility model and in the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

While the foregoing is directed to embodiments of the present utility model, other and further embodiments of the utility model may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims (10)

1. A packaging box, characterized by comprising:

a case having a mounting groove configured to mount a chip;

a base pad and an adapter integrated to the case, the adapter having a first transfer pad and a second transfer pad connected to each other and electrically conductive and configured in pairs;

the adapter is positioned between the mounting slot and the base pad such that the first adapter pad is proximate the mounting slot and the second adapter pad is proximate the base pad.

2. The enclosure of claim 1, wherein the housing is metallic;

and/or the box body is made of superconductor materials which are in a superconducting state below a preset critical point temperature;

and/or the number of the basic bonding pads is equal to the number of the first transfer bonding pads;

and/or the base bonding pad is positioned at the edge of the box body;

and/or the mounting groove is a through groove penetrating along the thickness direction of the box body;

and/or the adapter is a printed circuit board;

and/or the basic bonding pads are provided with a plurality of bonding pads and form a first bonding pad group, each bonding pad in the first bonding pad group is arranged in a one-dimensional linear manner, and the first transfer bonding pads are provided with a plurality of bonding pads and are sequentially arranged along the arrangement direction of each bonding pad in the first bonding pad group.

3. The package of claim 1, wherein the mounting groove has a depth, and wherein the depth is dependent on a thickness of the chip.

4. A package according to claim 3, wherein the mounting slot is configured to: the mounting groove depth is consistent with the chip thickness so that the top surface is flush with the top surface of the case when the chip is placed in the mounting groove.

5. A package assembly, comprising:

a package according to any one of claims 1 to 4; and

the chip is configured in the mounting groove, the signal contact of the chip is electrically connected to the first transfer bonding pad, and the second transfer bonding pad is electrically connected to the base bonding pad.

6. A packaging box, characterized by comprising:

the box body is provided with a placement hole for configuring the chip;

a conductor pad and a base fixedly connected to the case; and

a middleware coupled to the base, the middleware configured with electrically conductive and paired first and second pads;

wherein the first bonding pad is close to the placement hole, and the second bonding pad is close to the conductor pad.

7. The package according to claim 6, wherein the placement hole is a through hole in a thickness direction of the case;

and/or, the middleware is detachably connected with the base;

and/or the number of conductor pads is greater than the number of first pads;

and/or the intermediate piece is a printed circuit board;

and/or the box body is provided with a rectangular outline projected in the thickness direction, the conductor pads are provided with a plurality of four sides which are distributed to the rectangular outline, the bases and the middle piece are provided with the same number and four, and the four bases are distributed in one-to-one correspondence to the four sides of the rectangular outline.

8. A package assembly, comprising:

the packaging box according to claim 6 or 7; and

the chip is configured in the placement hole, the signal port of the chip is electrically connected to the first bonding pad, and the second bonding pad is electrically connected to the conductor pad.

9. A package assembly, comprising:

an enclosure defining a first region, a second region surrounding the first region, and a third region surrounding the second region;

the first bonding pad and the second bonding pad are configured in the second area and are electrically conducted, and the third bonding pad is configured in the third area;

a chip disposed in the first region; and

the signal port of the chip is connected to the first lead of the first pad and the second pad is connected to the second lead of the third pad.

10. A quantum computer comprising an enclosure according to any one of claims 1 to 4, or an enclosure according to claim 6 or 7, or an enclosure assembly according to claim 5 or 8 or 9.