CN220122648U - Depth fusion on-column circuit breaker capacitor electricity-taking power supply device - Google Patents

Abstract

The utility model discloses a deep fusion on-pole breaker capacitor electricity taking power supply device, which is characterized in that a traditional capacitor electricity taking power supply device is only subjected to single-way input and cannot charge a super capacitor, and once a backup lithium battery fails, the capacity of outputting energy in the moment of switching on and off of a switch cannot be met by the energy obtained by the electricity taking of an input source capacitor. The device management unit is provided with power supply self-adaptive energy-taking CPT power, can simultaneously meet the output power of an external core unit, battery charging power and super capacity charging power, and is preferentially provided for the external core unit, and when the power of the core unit exceeds the output power limit value of the power supply module, the excess part is provided by a battery or super capacity, such as a switching-on/switching-off and energy storage stage and a 5G module communication stage; once overcurrent or short-circuit protection occurs on the battery, the battery is disconnected, and the battery is recovered through a battery starting key; when CPT is supplied, the battery is automatically restored.

Description

Depth fusion on-column circuit breaker capacitor electricity-taking power supply device

Technical Field

The utility model relates to the technical field of electronic information, in particular to a deep fusion on-column circuit breaker capacitor electricity taking power supply device.

Background

Along with the implementation of national energy conservation, environmental protection and supporting policies, a large number of distributed power supplies at the energy supply side are connected into a power distribution network, and a serious challenge is provided for the aspects of safety, management, scheduling and the like of the power distribution network, and the importance of the power supply device is self-evident when the power supply device is used as a power supply device for switching on and off the network by deeply fusing a circuit breaker capacitor on a column. Because the power that the circuit breaker electric capacity got on the degree of depth fuses the post is low, can't satisfy the high-power supply requirement of switch divide-shut brake, so the stability and the life-span of reserve electric capacity are important very much, traditional power supply unit can only charge for the lithium cell, once the lithium cell life-span expires on the post circuit breaker will unable divide-shut brake, bring the potential safety hazard for power line, so we have developed a degree of depth fuses circuit breaker electric capacity and gets electric power supply unit on the post, the device both can charge for the lithium cell, built-in super capacitor module again, can solve single reserve life short problem.

The traditional capacitor power supply device has short power supply time after power failure, and a large amount of energy is lost due to pressure difference. Meanwhile, the battery power display is not provided, and the battery power situation is inconvenient to grasp.

Disclosure of Invention

The utility model aims at overcoming the technical defects in the prior art and discloses a capacitor electricity-taking power supply device of a circuit breaker on a deep fusion column.

In order to achieve the purpose of the utility model, the technical scheme adopted by the utility model is as follows:

the deep fusion on-column circuit breaker capacitor electricity taking power supply device comprises a double-circuit electricity taking power supply CPT, wherein the double-circuit electricity taking power supply CPT is electrically connected with a management unit, a CPU is arranged in the management unit, the CPU is electrically connected with a storage battery control circuit, the storage battery control circuit is electrically connected with an overvoltage protection circuit, the overvoltage protection circuit is electrically connected with the management unit, an output voltage conversion circuit and a threshold detection module, the threshold detection module is electrically connected with a super capacitor module, the output voltage conversion circuit is electrically connected with the management unit, the model of the CPU is stm32f103VCT6,

the storage battery control circuit comprises a storage battery circuit, a first control circuit and a second control circuit, wherein the storage battery circuit comprises eight storage batteries with the same specification and seven relays with the same model, the storage batteries are connected with the relays in a staggered way, a first pin of each relay is electrically connected with a fourth input voltage, an eighth pin of each relay is grounded, the storage batteries comprise a first storage battery and an eighth storage battery, each relay comprises a first relay and a seventh relay, a negative electrode of each first storage battery is electrically connected with a second pin of each first relay, a positive electrode of each first storage battery is electrically connected with a sixth pin of each first relay, a negative electrode of each eighth storage battery is electrically connected with a second pin of each seventh relay, a positive electrode of each eighth storage battery is electrically connected with a seventh pin of each seventh relay, negative electrodes of other storage batteries are electrically connected with a second pin of the previous relay and a third pin of the subsequent relay, the other storage battery anode is electrically connected with a fourth pin of a previous relay, a first gas pin of the previous relay and a sixth pin of the next relay, a first diode is electrically connected between a first pin of the first relay and an eighth pin of the first relay, a seventh first pin of the relay is also electrically connected with a source electrode of a first MOS tube, a drain electrode of the first MOS tube is electrically connected with a fifth input voltage, a grid electrode of the first MOS tube is electrically connected with one end of a first resistor and a collector electrode of a second triode, the other end of the first resistor is electrically connected with a fifth input voltage, a base electrode of the second triode is electrically connected with one end of a second resistor and one end of a first capacitor, the other end of the second resistor is electrically connected with one end of a third resistor and a YK_BL pin of a CPU, and the other end of the third resistor is electrically connected with the other end of the first capacitor, an emitter electrode of the second triode and a ground signal;

the first control circuit comprises a ninth relay, a first pin of the ninth relay is electrically connected with a fifth input voltage and a cathode of a second diode, a second pin of the ninth relay is electrically connected with a sixth input voltage and a second pin of a first wiring terminal, a third pin of the ninth relay is electrically connected with a positive electrode of a first storage battery, a sixth pin of the ninth relay is electrically connected with a negative electrode of an eighth storage battery, a seventh pin of the ninth relay is electrically connected with a seventh input voltage and the first pin of the first wiring terminal, an eighth pin of the ninth relay is electrically connected with an anode of a second diode and a collector of a third triode, a base of the third triode is electrically connected with one end of a fourth resistor and one end of a second capacitor, the other end of the fourth resistor is electrically connected with a YK_DCTC pin of a CPU and one end of the sixth resistor, and the other end of the sixth resistor is electrically connected with the other end of the second capacitor, a ground signal and a third triode emitter;

the second control circuit comprises an eighth relay, a first pin of the eighth relay is electrically connected with a fifth input voltage and a cathode of a third diode, a third pin of the eighth relay is electrically connected with a cathode of an eighth storage battery, a fourth pin of the eighth relay is electrically connected with a seventh input voltage and a second pin of a second wiring terminal, a fifth pin of the eighth relay is electrically connected with the eighth input voltage and the first pin of the second wiring terminal, a sixth pin of the eighth relay is electrically connected with a positive electrode of the first storage battery, an eighth pin of the eighth relay is electrically connected with an anode of a third diode and a collector of a fourth triode, a base of the fourth triode is electrically connected with one end of a fifth resistor and one end of a third capacitor, the other end of the fifth resistor is electrically connected with a YK_KC pin of the CPU and one end of the seventh resistor, and the other end of the seventh resistor is electrically connected with the other end of the third capacitor, a ground signal and a fourth triode emitter.

Further, the power supply device comprises a bottom plate, wherein a wiring terminal, a management unit board and a super capacitor module are arranged on the bottom plate, the management unit board is electrically connected with a power display board, the power display board is electrically connected with a plurality of power display lamps, a cover plate is arranged on the bottom plate, and a plurality of through holes for the power display lamps to pass through are formed in the cover plate; the two-way power supply CPT, the management unit and the storage battery control circuit are all arranged on the management unit board.

Compared with the prior art, the utility model has the advantages that:

the batteries are managed in series and parallel through the relay, and the power consumption is reduced through low-voltage difference voltage, so that the power supply time of the equipment after power failure is improved.

And the device can visually observe the electric quantity display, and can better grasp the electric quantity condition of the battery in real time.

Drawings

FIG. 1 is a circuit flow diagram of the scheme;

FIG. 2 is a circuit diagram of the scheme;

FIG. 3 is a system block diagram of the present solution;

FIG. 4 is a block diagram of the device according to the present embodiment;

FIG. 5 is a circuit diagram of the battery according to the present embodiment;

FIG. 6 is a diagram of a battery control circuit according to the present embodiment;

FIG. 7 is a block diagram of the operating system of the present solution.

Detailed Description

The utility model is described in further detail below with reference to the drawings and the specific examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.

Example 1

Referring to fig. 3, 5 and 6, a capacitor power supply device of a circuit breaker on a deep fusion column comprises a double-circuit power supply CPT13, wherein the double-circuit power supply CPT13 is electrically connected with a management unit 14, a CPU (central processing unit) is arranged in the management unit 14, the CPU is electrically connected with a storage battery control circuit 15, the storage battery control circuit 15 is electrically connected with an overvoltage protection circuit 8, the overvoltage protection circuit 8 is electrically connected with the management unit 14, an output voltage conversion circuit 7 and a threshold detection module 16, the threshold detection module 16 is electrically connected with a super capacitor module 17, and the output voltage conversion circuit 7 is electrically connected with the management unit 14;

the battery control circuit 15 includes a battery circuit including eight batteries of the same specification and seven relays of the same model, the batteries are connected with the relays in a staggered manner, the first pins of the relays are electrically connected with the fourth input voltage VDD5, the eighth pins of the relays are grounded, the batteries include a first battery and an eighth battery, the relays include a first relay and a seventh relay, the first battery anode B1-is electrically connected with the second pin of the first relay K1, the first battery anode b1+ is electrically connected with the sixth pin of the first relay K1, the eighth battery anode B8-is electrically connected with the second pin of the seventh relay K7, the eighth battery anode b8+ is electrically connected with the seventh pin of the seventh relay K7, the rest battery anodes are electrically connected with the second pin of the previous relay and the third pin of the next relay, the other storage battery anodes are electrically connected with a fourth pin of a previous relay, a first gas pin of the previous relay and a sixth pin of the next relay, a first diode D1 is electrically connected between a first pin of a first relay K1 and an eighth pin of the first relay K1, a first pin of a seventh relay K7 is also electrically connected with a source electrode of a first MOS tube V1, a drain electrode of the first MOS tube V1 is electrically connected with a fifth input voltage V5P0, a grid electrode of the first MOS tube V1 is electrically connected with one end of a first resistor R1 and a collector electrode of a second triode V2, the other end of the first resistor R1 is electrically connected with the fifth input voltage V5P0, a base electrode of the second triode V2 is electrically connected with one end of a second resistor R2 and one end of a first capacitor C1, the other end of the second resistor R2 is electrically connected with one end of a third resistor R3 and a YK_BL pin of a CPU, and the other end of the third resistor R3 is electrically connected with the other end of the first capacitor C1, A second triode V2 emitter and ground signal;

the first control circuit comprises a ninth relay K9, a first pin of the ninth relay K9 is electrically connected with a fifth input voltage V5P0 and a cathode of a second diode D2, a second pin of the ninth relay K9 is electrically connected with a sixth input voltage VBL+ and a second pin of an X1, a third pin of the ninth relay K9 is electrically connected with a positive pole B1+ of a first storage battery, a sixth pin of the ninth relay K9 is electrically connected with a negative pole B8-of the eighth storage battery, a seventh pin of the ninth relay K9 is electrically connected with a seventh input voltage VBL-and a first pin of the X1, an eighth pin of the ninth relay K9 is electrically connected with an anode of a second diode D2 and a collector of a third triode V3, a base of the third triode V3 is electrically connected with one end of a fourth resistor R4 and one end of a second capacitor C2, the other end of the fourth resistor R4 is electrically connected with a YK_DCTC pin of the CPU and one end of a sixth resistor R6, and the other end of the sixth resistor R6 is electrically connected with the other end of the second capacitor C2, a ground signal and a third triode V3;

the second control circuit comprises an eighth relay K8, a first pin of the eighth relay K8 is electrically connected with a fifth input voltage V5P0 and a cathode of a third diode D3, a third pin of the eighth relay K8 is electrically connected with an eighth storage battery cathode B8-, a fourth pin of the eighth relay K8 is electrically connected with a seventh input voltage D24 V_OUT-and an X2 second pin, a fifth pin of the eighth relay K8 is electrically connected with a first pin of the eighth input voltage D24V_OUT+ and an X2, a sixth pin of the eighth relay K8 is electrically connected with a positive electrode B1+ of the first storage battery, an eighth pin of the eighth relay K8 is electrically connected with an anode of a third diode D3 and a collector of a fourth triode V4, a base of the fourth triode V4 is electrically connected with one end of a fifth resistor R5 and one end of a third capacitor C3, the other end of the fifth resistor R5 is electrically connected with one end of a YK_KC pin of a CPU and one end of a seventh resistor R7, and the other end of the seventh resistor R7 is electrically connected with the other end of the third capacitor C3, a ground signal and a fourth triode V4 emitter of the fourth triode V4. When the rated voltage of a single lithium iron phosphate battery is 3.2V, the floating voltage is 3.65V, the capacity is 5Ah, the output voltage is just met when the system works, when the switching-on and switching-off operation of a circuit breaker is needed, 8 lithium iron phosphate batteries are connected in series through relays K1-K7, the rated voltage is 25.6V after the series connection, the voltage needed during the switching-on and switching-off operation is met, the circuit ingeniously utilizes the relays to carry out series-parallel management on the batteries, the power consumption is reduced through low-voltage difference voltage, and the power supply time after power failure of equipment is prolonged.

Referring to fig. 1 and 2, the two-way power supply CPT13 includes a first power supply CPT electrically connected to the a line and a second power supply CPT electrically connected to the C line, the management unit 14 includes a first surge voltage clamp protection circuit 1 electrically connected to the first power supply CPT, the surge voltage clamp protection circuit 1 is electrically connected to an EMI filter circuit 2, the EMI filter circuit 2 is electrically connected to a full-wave rectification circuit 3, the full-wave rectification circuit 3 is electrically connected to a power supply 4, the power supply 4 is electrically connected to a PWM control circuit 5 and a full-wave rectification circuit 10, the PWM control circuit 5 is electrically connected to a conversion switch circuit 6, the conversion switch circuit 6 is electrically connected to an output voltage conversion circuit 7, the output voltage conversion circuit 7 is electrically connected to an overvoltage protection circuit 8, the overvoltage protection circuit 8 is electrically connected to an output voltage feedback closed-loop control circuit 9, the full-wave rectification circuit 10 is electrically connected to an EMI filter circuit 11, the EMI filter circuit 11 is electrically connected to a second surge voltage clamp protection circuit 12, and the second surge voltage clamp protection circuit 12 is electrically connected to the second power supply CPT.

The first surge voltage clamp protection circuit 1 comprises a second gas discharge tube M2, one end of the second gas discharge tube M2 is grounded, the other end of the second gas discharge tube M2 is electrically connected with one end of a fifth MOV varistor MOV5 and one end of a sixth MOV varistor MOV6, the other end of the sixth MOV varistor MOV6 is electrically connected with a second input voltage CP1-, one end of an eighth MOV varistor MOV8, one end of a seventh MOV varistor MOV7, one end of a second X capacitor X2 and a first EMI filter circuit 2, the other end of the fifth MOV varistor MOV5 is electrically connected with one end of a fourth fuse F4, one end of a ninety-ninth varistor R99 and one end of a second fuse N2, the other end of the second fuse N2 is electrically connected with the other end of the eighth MOV varistor MOV8 and the other end of the seventh MOV varistor MOV7, the other end of the fourth fuse F4 is electrically connected with the other end of the first input voltage CP1+, the other end of the ninety-ninth varistor R99 and the first EMI filter circuit 2, and the second surge voltage clamp protection circuit 12 is consistent with the first surge voltage clamp protection circuit 1; the first EMI filter circuit 2 comprises a second common-mode inductor ET2, a first pin of the second common-mode inductor ET2 is electrically connected with the other end of the second X capacitor X2, a second pin of the second common-mode inductor ET2 is electrically connected with one end of a fourth Y capacitor Y4 and the first full-wave rectifying circuit 3, a third pin of the second common-mode inductor ET2 is electrically connected with one end of a fifth Y capacitor Y5, a fourth pin of the second common-mode inductor ET2 is electrically connected with one end of the second X capacitor X2, the other end of the fourth Y capacitor Y4 is electrically connected with a ground signal and the other end of the fifth Y capacitor Y5, and the second EMI filter circuit 11 has a structure consistent with that of the first EMI filter circuit 2; the first full-wave rectifying circuit 3 includes a forty-five rectifying bridge D45, a first pin of the forty-five rectifying bridge D45 is electrically connected to the power taking circuit 4, a second pin of the forty-five rectifying bridge D45 is electrically connected to one end of the fifth Y capacitor Y5, a third pin of the forty-five rectifying bridge D45 is electrically connected to one end of the fourth Y capacitor Y4, a fourth pin of the forty-five rectifying bridge D45 is electrically connected to the power taking circuit 4, and the second full-wave rectifying circuit 10 has a structure identical to that of the first full-wave rectifying circuit 3.

The power taking circuit 4 comprises a seventy-sixth capacitor C76, the positive electrode of the seventy-sixth capacitor C76 is electrically connected with a first pin of a forty-fifth rectifier bridge D45, one end of a first hundred resistor R100 and a first inductor L1, the negative electrode of the seventy-sixth capacitor C76 is electrically connected with the first full-wave rectifier circuit 3, a ground wire, one end of the first hundred-tenth resistor R110, one end of the seventy-fifth capacitor C75 and the PWM control circuit 5, the other end of the first hundred-tenth resistor R110 is electrically connected with one end of the first hundred-zero fourth resistor R104, one end of the seventy-eighth capacitor C78 and the PWM control circuit 5, the other end of the seventy-eighth capacitor C78 is electrically connected with the second full-wave rectifier circuit 10, the other end of the first hundred-fourth resistor R104 is electrically connected with the other end of the first hundred-resistor R100, the other end of the seventy-fifth capacitor C75 is electrically connected with the PWM control circuit 5 and the first hundred-twenty resistor R120, and the other end of the first hundred-twenty resistor R120 is electrically connected with the output voltage feedback control circuit 9.

The PWM control circuit 5 includes a thirteenth chip U33, a first pin of the thirty-third chip U33 is electrically connected to the power taking circuit 4 and one end of the first hundred twenty-first resistor R120, the other end of the first hundred twenty-first resistor R120 is electrically connected to the output voltage feedback closed loop control circuit 9, a second pin of the thirty-third chip U33 is electrically connected to one end of the eighty-second capacitor C82 and one end of the first hundred thirteenth resistor R113, the other end of the eighty-second capacitor C82 is electrically connected to a fourth pin of the thirteenth chip U33, one end of the eighty-third capacitor C80, one end of the eighty-third capacitor C83, an eighth first capacitor C81 negative electrode and the conversion switch circuit 6, a third pin of the thirty-third chip U33 is electrically connected to the other end of the eighty-first hundred twenty-first resistor R80, another end of the first hundred eleven resistor R111 is electrically connected to the conversion switch circuit 6, a fifth pin of the thirteenth chip U33 is electrically connected to one end of the first hundred seventy-eighth resistor R108 and one end of the first hundred seventy-seventh resistor R113, a third pin of the thirteenth chip U33 is electrically connected to the other end of the thirteenth resistor R6, and the eighth pin of the eighth chip U33 is electrically connected to the eighth pin of the eighth resistor R6, and the eighth pin of the eighth resistor R33 is electrically connected to the thirteenth circuit 6, and the eighth pin of the thirteenth chip U33 is electrically connected to the other end of the eighth resistor R6.

The conversion switch circuit 6 comprises a tenth MOS transistor Q10, the grid electrode of the tenth MOS transistor Q10 is electrically connected with the anode of a forty-six diode D46, one end of a first hundred-and-nine resistor R109 and the PWM control circuit 5, the drain electrode of the tenth MOS transistor Q10 is electrically connected with the anode of the forty-eight diode D40 and the source electrode of the output voltage conversion circuit 7, the source electrode of the tenth MOS transistor Q10 is electrically connected with the other end of the first hundred-and-nine resistor R109, one end of the first hundred-and-fourteen resistor R114 and the PWM control circuit, the cathode of the forty-six diode D46 and one end of the first hundred-and-nine resistor R109 are electrically connected with the PWM control circuit, the cathode of the forty-two diode D40 is electrically connected with one end of a seventy-two capacitor C72 and one end of the first hundred-and-two resistor R102, the other end of the seventy-two capacitor C72 and the other end of the first hundred-and-two resistor R102 are electrically connected with the power taking circuit 4 and the output voltage conversion circuit 7, the other end of the first hundred-fourteen resistor R114 is electrically connected with one end of a seventy-seventh capacitor C77, one end of a first hundred-twelve resistor R112, the negative electrode of a seventy-ninth capacitor C79 and the overvoltage protection circuit 8, the other end of the seventy-seventh capacitor C77 and the other end of the first hundred-twelve resistor R112 are electrically connected with one end of a first hundred-six resistor R106 and the PWM control circuit 5, the other end of the first hundred-six resistor R106 is electrically connected with one end of a first hundred-five resistor R105 and the output voltage conversion circuit 7, the other end of the first hundred-five resistor R105 is electrically connected with the anode of a forty-fourth diode D44, the cathode of the forty-fourth diode D44 is electrically connected with the anode of the seventy-ninth capacitor C79, one end of the first hundred-one resistor R101, the collector of the ninth triode Q9 and the output voltage feedback closed loop control circuit 9, the base of the ninth triode Q9 is electrically connected with the other end of the first hundred-one resistor R101 and the cathode of the forty-one diode D41, the anode of the forty-one diode D41 is grounded, an emitter of the ninth transistor Q9 is electrically connected to an anode of the forty-two diode D42, and a cathode of the forty-two diode D42 is electrically connected to the PWM control circuit 5.

The output voltage conversion circuit 7 includes a second transformer T2, a first pin of the second transformer T2 is grounded, a second pin, a third pin and a sixth pin of the second transformer T2 are all electrically connected to the conversion switch circuit 6, a tenth pin of the second transformer T2 is electrically connected to a negative electrode of the seventy-third capacitor C73, a negative electrode of the seventy-fourth capacitor C74 and a ground signal, a twelfth pin of the second transformer T2 is electrically connected to a first pin of the forty-third MOS transistor D43, a third pin of the fourth MOS transistor D43 and one end of the first hundred-third resistor R103, the other end of the first hundred-third resistor R103 is electrically connected to one end of the seventy-first capacitor C71, a second pin of the forty-third MOS transistor D43 is electrically connected to a positive electrode of the seventy-third capacitor C73, a positive electrode of the seventy-fourth capacitor C74, the other end of the seventy-fourth capacitor C71 and a third input voltage VCC, and a seventy-third input voltage VCC are all electrically connected to the other end of the seventy-fourth capacitor C74.

The overvoltage protection circuit 8 comprises a thirty-fourth optocoupler U34, a first pin of the thirty-fourth optocoupler U34 is electrically connected with the PWM control circuit 5, a fourth pin of the thirty-fourth optocoupler U34 is electrically connected with the change-over switch circuit 6 and one end of an eighth Y capacitor Y8, a second pin of the thirty-fourth optocoupler U34 is electrically connected with one end of a first hundred seventeenth resistor R117 and one end of a first hundred fifteenth resistor R115, the other end of the first hundred seventeenth resistor R117 is electrically connected with a third pin of the thirty-fourth optocoupler U34, a second pin of a third fifteenth controllable precision voltage stabilizing source U35, one end of an eighth capacitor C85 and one end of an eighth capacitor C84, the other end of the first hundred fifteenth resistor R115 is electrically connected with one end of the first hundred eighty resistor R118, the other end of the first hundred twenty-second resistor R121 is electrically connected with one end of the first hundred twenty-second resistor R122, the other end of the eighth capacitor C85 and the other end of the third fifteenth controllable precision voltage stabilizing source U35, and the other end of the eighth capacitor C8 is electrically connected with the other end of the eighth capacitor Y8.

The output voltage feedback closed-loop control circuit 9 comprises a thirty-sixth photo-couple U36, a first pin of the thirty-sixth photo-couple U36 is electrically connected with the change-over switch circuit 6, a second pin of the thirty-sixth photo-couple U36 is electrically connected with one end of a first hundred-nineteenth resistor R119, the other end of the first hundred-nineteenth resistor R119 is electrically connected with a third input voltage VCC, a third pin of the thirty-sixth photo-couple U36 is electrically connected with a cathode of a forty-eighth zener diode D48, an anode of the forty-eighth zener diode D48 is grounded, and a fourth pin of the thirty-sixth photo-couple U36 is electrically connected with the circuit 4.

Referring to fig. 4, a depth fusion on-column circuit breaker capacitor electricity-taking power supply device comprises a bottom plate 21, a wiring terminal 22 is arranged on the outer edge of one side of the bottom plate 21, a super capacitor module 17 and a management unit board 23 are arranged on the bottom plate 21, an electric quantity display board 24 is arranged on the bottom plate 21, a plurality of electric quantity display lamps 25 are electrically connected on the electric quantity display board 24, an upper cover plate 26 is covered on the bottom plate 21, long holes are formed in the cover plate 26 in cooperation with the wiring terminal 22, through holes 27 for allowing the plurality of power supply quantity display lamps 25 to penetrate are formed in the cover plate 26, and all the wiring terminal 22, the super capacitor module 17 and the electric quantity display board 24 are electrically connected. The power in the device can be visually monitored by the power display panel 24. The two-way power supply CPT13, the management unit 14 and the storage battery control circuit 15 are all arranged on the management unit board 23.

The principle is as follows:

referring to fig. 1 and 7, a CPU of model stm32f103VCT6 is provided in the management unit. When the CPU pin YK_BL outputs high level, the triode V2 is conducted, the V1 MOST is conducted, the VDD5 obtains +5V voltage, so that the K1-K7 relays are all conducted, after the relays are conducted, the B1-B2+ and the B2+ of the K1 are connected in series, the B2+ and the B3+ are connected in series, the B3+ and the B4+ are connected in series, the B4+ and the B5+ are connected in series, the B5+ and the B6+ are connected in series, the B6+ and the B7+ are connected in series, 8 batteries are connected in a tail-hand manner, the head end is B1+, the tail end is B8-, and the voltage between the B1+ and the B8-is as follows: 3.2x8=25.6v, satisfying the voltage required in the opening and closing operation; meanwhile, when the CPU pin YK_DCTC outputs a high level, the relay K9 is conducted, VBL+ and VBL-are temporarily disconnected and B1+ and B8-are connected, and the backup capacitor supplies power; meanwhile, when the CPU pin YK_KC outputs a high level, the relay K8 is conducted, BI+ and B8-are switched to DC24 V_OUT-and DC24V_OUT+ through the relay, and the DC24 V_OUT-and the DC24V_OUT+ are operation voltages during opening and closing operation of the controller.

When the CPU pin YK_DCTC outputs a low level after the opening and closing operation is finished, the relay K9 is turned off, VBL+ is connected with VBL-and B1+ and B8-, and the system voltage is restored to B1+ and B8-power supply. Meanwhile, a CPU pin YK_BL outputs a low level, a triode V2 is turned off, and a V1 MOST is turned off, so that all the K1-K7 relays are turned off and restore to a default state, B1+ and B2+ of K1 are connected in parallel, B2+ and B3+ are connected in parallel, B3+ and B4+ are connected in parallel, B4+ and B5+ are connected in parallel, B5+ and B6+ are connected in parallel, B6+ and B7+ are connected in parallel, the total capacity of 8 batteries after connection is 8 x 5 Ah=40Ah, and the voltage is kept unchanged to be 3.2V. Under the condition of CPT1 and CPT2 external alternating current power failure, the rated voltage of the lithium battery is converted into the system power supply voltage of 5V, and the efficiency is far higher than that of the traditional 25.6V direct voltage reduction to the 5V system power supply. The power supply module skillfully utilizes the relay to switch the battery in series and parallel, reduces the loss power consumption through the low-voltage difference voltage, meets the high-voltage amplitude required by the switching-off action of the pole-mounted circuit breaker, and meets the working voltage of the system during normal operation.

The device management unit is provided with power supply self-adaptive energy-taking CPT power, can simultaneously meet the requirements of external core unit output power, battery charging power and super-capacity charging power, and meets the requirements of power supply module output power = core unit power + battery charging power + super-capacity charging power, and is preferentially provided for the core unit; once overcurrent or short-circuit protection occurs on the battery, the battery is disconnected, and the battery is recovered through a battery starting key; when CPT is supplied, the battery is automatically restored. Meanwhile, the double-path CPT capacitor point-taking input solves the defect of the traditional single-path input, and the working mode of double backups of the lithium battery and the super capacitor can solve the problem of short service life of the single backups. Meanwhile, the voltage and the current can be accurately monitored, the problems of overcharge, overdischarge, overcurrent damage and the like of the battery are avoided, and the service life of the battery is prolonged.

The foregoing is merely a preferred embodiment of the present utility model and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present utility model, which are intended to be comprehended within the scope of the present utility model.

Claims (2)

1. The utility model provides a circuit breaker electric capacity electricity supply unit is got to degree of depth fuses post, is got electric power CPT (13), its characterized in that including the double-circuit: the double-circuit power supply CPT (13) is electrically connected with a management unit (14), a CPU (Central processing Unit) is arranged in the management unit (14), the CPU is electrically connected with a storage battery control circuit (15), the storage battery control circuit (15) is electrically connected with an overvoltage protection circuit (8), the overvoltage protection circuit (8) is electrically connected with the management unit (14), an output voltage conversion circuit (7) and a threshold detection module (16), the threshold detection module (16) is electrically connected with a super capacitor module (17), the output voltage conversion circuit (7) is electrically connected with the management unit (14), the model of the CPU is stm32f103VCT6,

the storage battery control circuit (15) comprises a storage battery circuit, a first control circuit and a second control circuit, the storage battery circuit comprises eight storage batteries with the same specification and seven relays with the same model, the storage batteries are connected with the relays in a staggered way, a first pin of each relay is electrically connected with a fourth input voltage (VDD 5), an eighth pin of each relay is grounded, the storage battery comprises a first storage battery and an eighth storage battery, each relay comprises a first relay and a seventh relay, a negative electrode (B1-) of each first storage battery is electrically connected with a second pin of the first relay (K1), a positive electrode (B1+) of each first storage battery is electrically connected with a sixth pin of the first relay (K1), a negative electrode (B8-) of each eighth storage battery is electrically connected with a second pin of the seventh relay (K7), the positive electrode (B8+) of the eighth storage battery is electrically connected with the seventh pin of the seventh relay (K7), the negative electrode of the other storage batteries is electrically connected with the second pin of the former relay and the third pin of the latter relay, the positive electrode of the other storage batteries is electrically connected with the fourth pin of the former relay, the gas-carrying pin of the former relay and the sixth pin of the latter relay, a first diode (D1) is electrically connected between the first pin of the first relay (K1) and the eighth pin of the first relay (K1), the first pin of the seventh relay (K7) is also electrically connected with the source electrode of the first MOS tube (V1), the drain electrode of the first MOS tube (V1) is electrically connected with the fifth input voltage (V5P 0), the grid electrode of the first MOS tube (V1) is electrically connected with one end of the first resistor (R1) and the collector electrode of the second triode (V2), the other end of the first resistor (R1) is electrically connected with a fifth input voltage (V5P 0), the base electrode of the second triode (V2) is electrically connected with one end of the second resistor (R2) and one end of the first capacitor (C1), the other end of the second resistor (R2) is electrically connected with one end of the third resistor (R3) and the YK_BL pin of the CPU, and the other end of the third resistor (R3) is electrically connected with the other end of the first capacitor (C1), the emitter electrode of the second triode (V2) and a ground signal;

the first control circuit comprises a ninth relay (K9), a first pin of the ninth relay (K9) is electrically connected with a fifth input voltage (V5P 0) and a cathode of a second diode (D2), a second pin of the ninth relay (K9) is electrically connected with a sixth input voltage (VBL+) and a second pin of a first wiring terminal (X1), a third pin of the ninth relay (K9) is electrically connected with a positive electrode (B1+) of a first storage battery, a sixth pin of the ninth relay (K9) is electrically connected with a negative electrode (B8-) of the eighth storage battery, a seventh pin of the ninth relay (K9) is electrically connected with a seventh input voltage (VBL-) and a first pin of the first wiring terminal (X1), a eighth pin of the ninth relay (K9) is electrically connected with an anode of the second diode (D2) and a collector of a third triode (V3), a base of the third triode (V3) is electrically connected with one end of a fourth resistor (R4) and one end of a second capacitor (TC 2), a sixth pin of the fourth resistor (R4) is electrically connected with a third resistor (R6) and the other end of the third resistor (C2) and the other end of the third resistor (R) is electrically connected with a third resistor (R2);

the second control circuit comprises an eighth relay (K8), a first pin of the eighth relay (K8) is electrically connected with a fifth input voltage (V5P 0) and a cathode of a third diode (D3), a third pin of the eighth relay (K8) is electrically connected with an anode of an eighth storage battery (B8-), a fourth pin of the eighth relay (K8) is electrically connected with a seventh input voltage (D24 V_OUT-) and a second pin of a second wiring terminal (X2), a fifth pin of the eighth relay (K8) is electrically connected with the eighth input voltage (D24 V_OUT+) and the first pin of the second wiring terminal (X2), a sixth pin of the eighth relay (K8) is electrically connected with a positive electrode (B1+) of the first storage battery, a base of the fourth triode (V4) is electrically connected with one end of a fifth resistor (R5) and one end of a third capacitor (C3), and a base of the fourth triode (V4) is electrically connected with a base of the fifth resistor (R5) and the other end of the third resistor (R7) is electrically connected with the other end of the third resistor (R7).

2. The depth fusion on-pole circuit breaker capacitor power supply device as claimed in claim 1, wherein: the power supply device comprises a bottom plate (21), wherein a wiring terminal (22), a management unit board (23) and a super capacitor module (17) are arranged on the bottom plate (21), the management unit board (23) is electrically connected with a power display board (24), the power display board (24) is electrically connected with a plurality of power display lamps (25), a cover plate (26) is arranged on the upper cover of the bottom plate (21), and a plurality of through holes (27) for the power display lamps (25) to penetrate are formed in the cover plate (26); the two-way power supply CPT (13), the management unit (14) and the storage battery control circuit (15) are all arranged on the management unit board (23).