CN220121819U

CN220121819U - Semiconductor packaging device

Info

Publication number: CN220121819U
Application number: CN202320121744.3U
Authority: CN
Inventors: 林裕凯; 宋嘉濠
Original assignee: Advanced Semiconductor Engineering Inc
Current assignee: Advanced Semiconductor Engineering Inc
Priority date: 2023-01-16
Filing date: 2023-01-16
Publication date: 2023-12-01
Anticipated expiration: 2033-01-16

Abstract

The utility model provides a semiconductor packaging device, which comprises a die sealing structure, wherein the die sealing structure comprises: a body structure having a first surface; the alignment part is formed on the first surface, and the top surface of the alignment part and the first surface are positioned on different planes. The alignment part formed on the surface of the mold sealing structure is an obvious three-dimensional structure, when the alignment part is used as an alignment mark, a three-dimensional structure part corresponding to the alignment part is formed on the rewiring layer on the subsequent Cheng Zhongmo mold sealing structure, the alignment mark function is continuously provided, the gradual blurring caused by the lamination of the dielectric layers is avoided, in addition, the alignment part and the mold sealing structure are integrally formed, the material is consistent, the problem of oxidization is avoided, and the misjudgment caused by chromatic aberration is avoided.

Description

Semiconductor packaging device

Technical Field

The utility model relates to the technical field of semiconductor packaging, in particular to a semiconductor packaging device.

Background

Some semiconductor packages, such as FoCoS (Fan-Out Chip on Substrate, fan-out-type chip-on-substrate) structures, include a mold compound and a chip embedded in the mold compound, and have a long redistribution layer (Redistribution Layer, RDL) on the mold compound surface on the backside (backside) side of the chip.

For these semiconductor packages, precise alignment in the process is important. One common Alignment method is to set Alignment mark (Alignment mark) on the back of the chip, but the Alignment mark is gradually blurred after being stacked by multiple dielectric layers (PI) in the RDL process, which affects the Alignment accuracy. Another alignment method is to provide copper pillars (Cu pilar), where the copper pillars are buried in a molding compound to form TMV (Through molding via, plastic-sealed through holes), and the copper pillars are exposed as positioning marks after the surface of the molding compound is worn out, but the color difference of the exposed copper pillars compared with the surrounding surface of the molding compound changes after oxidation, and the deviation in alignment may even be misjudged as filler particles (Skip) and skipped (Skip), so that alignment cannot be performed.

The above results show that the alignment marks commonly used at present have the technical problems of low alignment accuracy and limited capability of the alignment system for judging the alignment marks.

Disclosure of Invention

The utility model provides a semiconductor packaging device which is used for solving the technical problems that the existing common alignment marks are low in alignment accuracy and the capacity of an alignment system for judging the alignment marks is limited.

In order to achieve the above purpose, the utility model adopts the following technical scheme: a semiconductor package apparatus comprising a mold structure, the mold structure comprising: a body structure having a first surface; the alignment part is formed on the first surface, and the top surface of the alignment part and the first surface are positioned on different planes.

In some alternative embodiments, the alignment portion protrudes from the first surface.

In some alternative embodiments, the alignment portion is recessed from the first surface.

In some alternative embodiments, the semiconductor package apparatus further includes a first redistribution layer disposed on the first surface, where the first redistribution layer covers the alignment portion and has a portion that is wrapped around the alignment portion and corresponds to the shape of the alignment portion.

In some alternative embodiments, the semiconductor package apparatus further includes a second redistribution layer disposed on the other side of the mold structure with respect to the first redistribution layer, the second redistribution layer having a different line density than the first redistribution layer.

In some alternative embodiments, the first redistribution layer is a low density wire and the second redistribution layer is a high density wire, as compared to the first redistribution layer.

In some alternative embodiments, the semiconductor package apparatus further includes solder balls disposed on the first redistribution layer, and the alignment portions are lower than the solder balls.

In some optional embodiments, the semiconductor package apparatus further includes a chip embedded in the molding structure, a back surface of the chip faces the first surface, and the back surface of the chip and a top surface of the alignment portion are located on different planes.

In some alternative embodiments, the wafer back protrudes from the first surface.

In some alternative embodiments, the alignment portion protrudes from the first surface, and the back of the wafer is vertically between the top surface of the alignment portion and the first surface.

The utility model provides a semiconductor packaging device, which aims to solve the technical problems that the alignment accuracy of the conventional alignment mark is not high and the capacity of an alignment system for judging the alignment mark is limited. The utility model forms the alignment part on the surface of the mold sealing structure, the top surface of the alignment part and the surface of the mold sealing structure are positioned on different planes, which is an obvious three-dimensional structure, when the alignment part is used as the alignment mark, the rewiring layer on the subsequent Cheng Zhongmo sealing structure can form a three-dimensional structure part corresponding to the alignment part, the alignment mark function is continuously provided, the gradual blurring caused by the lamination of the dielectric layer is avoided, in addition, the alignment part and the mold sealing structure are integrally formed, the materials are consistent, the problem of oxidization is avoided, the misjudgment caused by chromatic aberration is avoided, so that the alignment part can realize better alignment effect, the alignment accuracy is improved, and the capability of an alignment system for judging the alignment mark is ensured not to be limited.

Drawings

Other features, objects and advantages of the present utility model will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:

fig. 1 is a schematic longitudinal sectional structure of a semiconductor package apparatus 1a according to an embodiment of the present utility model;

fig. 2 is a schematic longitudinal sectional structure of a semiconductor package apparatus 2a according to an embodiment of the present utility model;

fig. 3A-3L are schematic diagrams illustrating steps of manufacturing a semiconductor package apparatus according to an embodiment of the present utility model.

Reference numerals/symbol description:

10-a first molding structure; 11-a body structure; 110-a first surface; 12-aligning part; 13-a first rewiring layer; 14-a second redistribution layer; 15-a first chip; 16-conductive posts; 17-bonding pads; 18-solder balls; 19-a first connector; 20-a second molding structure; 21-a second chip; 22-a second connector; 23-underfill; 30-a carrier plate; 31-a first groove; 32-a second groove; 33-isolating layer; 34-seed layer; 35-adhesive tape.

Detailed Description

The technical problems to be solved by the present utility model and the resulting technologies will be readily apparent to those skilled in the art from the descriptions of the present specification, which are described below with reference to the accompanying drawings and examples

Effects. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant utility model and are not limiting of the utility model. In addition, for convenience of description, only parts related to the relevant utility model are shown in the drawings.

It should be readily understood that the meanings of "on", "above" and "above" in the present utility model should be interpreted in the broadest sense so that "on" means not only "directly on" but also "on" including intermediate components or layers that exist therebetween.

Further, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element or component as illustrated in the figures. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 ° or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "layer" as used herein refers to a portion of material that includes regions having a certain thickness. The layers may extend over the entire underlying or overlying structure, or may have a degree less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes therebetween. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate (substrate) may be a layer, may include one or more layers therein, and/or may have one or more layers thereon, and/or thereon. One layer may comprise multiple layers. For example, the semiconductor layer may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

The term "substrate" as used herein refers to a material to which subsequent layers of material are added. The substrate itself may be patterned. The material added to the top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer, or the like. Further alternatively, the substrate may have a semiconductor device or a circuit formed therein.

It should be noted that, the structures, proportions, sizes, etc. shown in the drawings are only used for being matched with those described in the specification for understanding and reading, and are not intended to limit the applicable limitation of the present utility model, so that the present utility model has no technical significance, and any modification of structures, changes in proportions or adjustment of sizes, without affecting the efficacy and achievement of the present utility model, should still fall within the scope covered by the technical content disclosed in the present utility model. Also, the terms "upper", "first", "second", and "a" and the like are used herein for descriptive purposes only and are not intended to limit the scope of the utility model for which the utility model may be practiced, but rather for relative changes or modifications without materially altering the technical context.

It should be further noted that, in the embodiment of the present utility model, the corresponding longitudinal section may be a section corresponding to a front view direction, the corresponding transverse section may be a section corresponding to a right view direction, and the corresponding horizontal section may be a section corresponding to an upper view direction.

In addition, embodiments of the utility model and features of the embodiments may be grouped together without conflict

And (5) combining. The utility model will be described in detail below with reference to the drawings in connection with embodiments.

Referring to fig. 1, fig. 1 is a schematic longitudinal sectional structure of a semiconductor package apparatus 1a according to an embodiment of the present utility model. As shown in fig. 1, a semiconductor package apparatus 1a according to an embodiment of the present utility model includes a first molding structure 10, and the first molding structure 10 includes: a main body structure 11, and an alignment portion 12.

Wherein the body structure 11 has a first surface 110; the alignment portion 12 is formed on the first surface 110, and a top surface of the alignment portion 12 and the first surface 110 are located on different planes. That is, the alignment portion 12 is a three-dimensional structure with respect to the first surface 110 of the main body structure 11.

Here, the first mold structure 10 may be formed of various mold compounds (Molding Compound). By way of example, the mold seal may include Epoxy (Epoxy resin), filler (Filler), catalyst (Pigment), release Agent (Release Agent), flame Retardant (Flame Retardant), coupling Agent (Coupling Agent), hardener (Harden), low stress absorber (Low Stress Absorber), adhesion promoter (Adhesion Promoter), ion scavenger (Ion Trapping Agent), and the like.

In some alternative embodiments, the alignment portion 12 protrudes from the first surface 110 and is a boss structure. The alignment portion 12 has a top surface and a sidewall connected between the top surface and the first surface 110, and optionally, the top surface is parallel to the first surface 110, the sidewall may be a plane and perpendicular to the first surface 110, and the sidewall may also be a slant or a curved surface and not perpendicular to the first surface 110.

In some alternative embodiments, the semiconductor package apparatus 1a further includes a first redistribution layer 13 disposed on the first surface 110, where the first redistribution layer 13 covers the alignment portion 12, and has a portion that is wrapped around the alignment portion 12 and corresponds to the shape of the alignment portion 12. When the alignment portion 12 protrudes from the first surface 110, a protruding portion is correspondingly formed on the first redistribution layer 13. Thus, the alignment portion 12 can be used as an alignment mark to perform a better alignment effect during the process of forming each dielectric layer and each circuit layer of the first redistribution layer 13 and other subsequent processes.

In some alternative embodiments, the semiconductor package apparatus 1a further includes a second redistribution layer 14 disposed on the other side of the first molding structure 10 with respect to the first redistribution layer 13.

In some alternative embodiments, the semiconductor package apparatus 1a further includes conductive pillars 16 buried within the first mold structure 10. The second redistribution layer 14 and the first redistribution layer 13 may be electrically connected through the conductive pillars 16. The conductive pillars 16 include, but are not limited to, copper pillars (Cu pillars).

In some alternative embodiments, the semiconductor package apparatus 1a further includes a first chip 15 embedded in the first molding structure 10, and a back side (i.e., a back side) of the first chip 15 faces the first surface 110. Wherein the back of the first chip 15 and the top surface of the alignment portion 12 are located on different planes.

In some alternative embodiments, the back of the first chip 15 protrudes from the first surface 110, and is vertically between the top surface of the alignment portion 12 and the first surface 110. That is, the back of the first chip 15 is higher than the first surface 110, but lower than the top surface of the alignment portion 12. The alignment function is ensured by making the top surface of the alignment portion 12 higher than the back surface of the first chip 15.

In some alternative embodiments, the alignment portion 12 has a plurality of alignment portions, one of which is remote from the first chip 15 and the other of which is adjacent or contiguous with the first chip 15. Alternatively, the alignment portion 12 adjacent or contiguous to the first chip 15 may have an arcuate side.

In some alternative embodiments, the active face of the first chip 15 faces the second redistribution layer 14 and may be electrically connected to the second redistribution layer 14 by a first connection 19. Here, the first connection member 19 includes, but is not limited to, a copper pillar, a Bump (Bump), or the like.

In some alternative embodiments, the first rewiring layer 13 has a pad 17 formed thereon, and the semiconductor package apparatus 1a further includes a solder ball 18 disposed on the pad 17. The solder balls 18 are configured to connect to an external device, such as a PCB (Printed Circuit Board ). Here, the alignment portion 12 is lower than the solder ball 18 to avoid affecting the external connection.

In some alternative embodiments, the semiconductor package apparatus 1a further includes a second molding structure 20. The second molding structure 20 is disposed on the other side of the second redistribution layer 14 with respect to the first molding structure 10. At least one second chip 21 may be embedded in the second molding structure 20. Alternatively, the active surface of the second chip 21 faces the second redistribution layer 14, and may be electrically connected to the second redistribution layer 14 through the second connection 22. The second connector 22 includes, but is not limited to, copper posts, bumps (bumps), and the like.

In some alternative embodiments, the semiconductor package apparatus 1a further includes an underfill 23 filled between the second redistribution layer 14 and the second chip 21, covering the second connection member 22. The underfill 23 includes, but is not limited to, a capillary underfill (CUF, capillary underfill), a Molded Underfill (MUF), a Non-conductive Paste (NCP), and the like. The underfill 23 serves to protect the second connection member 22 or to prevent oxidation of the second connection member 22 and to enhance the connection strength.

In some alternative embodiments, the wire density of the second redistribution layer 14 is different from the wire density of the first redistribution layer 13. Illustratively, the first redistribution layer 13 is a low-density wiring compared to the second redistribution layer 14, and the second redistribution layer 14 is a high-density wiring, i.e. the wiring density of the second redistribution layer 14 is higher than the wiring density of the first redistribution layer 13. Since the second redistribution layer 14 is a high-density wiring, the IO (input output) density thereof may be increased to connect the first chip 15 and the second chip 21.

In some alternative embodiments, the alignment portion 12 of the present embodiment may be formed with the aid of a Carrier (Carrier) during the manufacturing process. Firstly, forming a concave groove structure in an inactive area on the surface of a carrier plate, then arranging a Chip (Chip) on the carrier plate by an active Face up (Face up) process, coating the carrier plate with a Molding compound (Molding compound) through a Molding process, filling the concave groove structure with the Molding compound in the process, removing the carrier plate (De-carrier), and protruding the Molding compound filled with the groove structure on the surface of the Molding compound to form a required alignment part 12 which can be used as an alignment mark of a subsequent process.

In the above, the embodiment of the utility model provides a semiconductor package device 1a, in which an alignment portion 12 is formed on the surface of a first molding structure 10, the top surface of the alignment portion 12 and a first surface 110 of the first molding structure 10 are located on different planes, and the alignment portion 12 is an obvious three-dimensional structure, and when the alignment portion 12 is used as an alignment mark, a three-dimensional structure portion corresponding to the alignment portion 12 is formed on a first redistribution layer 13 above the first molding structure 10 in a subsequent process

In addition, the alignment portion 12 and the first molding structure 10 are integrally formed, and are consistent in material quality, and are not misjudged due to chromatic aberration, and the problem of oxidization is avoided, so that the alignment portion 12 can achieve better alignment effect, improve alignment accuracy, and ensure that the capability of an alignment system for judging alignment marks is not limited. In addition, the alignment portion 12 of the embodiment of the present utility model does not cause a problem of accumulated offset, compared to the use of copper pillars as alignment marks.

The alignment part 12 of the embodiment of the utility model has a three-dimensional structure, is easy to identify, can meet the high alignment requirement, and is suitable for the requirement of multi-chip packaging.

The embodiment of the utility model is suitable for Fan-out type (Chip first Fan out) of a Chip-first, fan-out type stack package (Fan out PoP), fan-out type Multi-Chip Module (Fan out MCM) and other types of products.

Referring to fig. 2, fig. 2 is a schematic longitudinal sectional structure of an embodiment 2a of a semiconductor package apparatus according to the present utility model. The semiconductor packaging apparatus 2a shown in fig. 2 is similar to the semiconductor packaging apparatus 1a shown in fig. 1, except that:

in the semiconductor package apparatus 2a, the alignment portion 12 is recessed from the first surface 110 and has a groove structure. The alignment portion 12 has a top surface (or referred to as a bottom surface) recessed inward from the first surface 110.

Here, the first redistribution layer 13 disposed on the first surface 110 has a portion that is coated on the alignment portion 12 and corresponds to the shape of the alignment portion 12, that is, a corresponding groove portion, so as to ensure that the alignment portion 12 can serve as an alignment mark to perform a better alignment effect during the process of forming each dielectric layer and each circuit layer of the first redistribution layer 13 and in other subsequent processes.

Here, the back of the first chip 15 may be flush or concave with the first surface 110, instead of protruding from the first surface 110.

In some alternative implementations, the alignment portion 12 of the present embodiment may be formed with the aid of a Carrier plate (Carrier). Unlike the process of the semiconductor package apparatus 1a shown in fig. 1, the convex structure is formed in the non-effective area of the surface of the carrier, and then the carrier is removed after the molding step, the portion of the surface of the molding material corresponding to the convex structure of the surface of the carrier forms a corresponding concave to form the alignment portion 12 of the groove structure, and the alignment portion 12 can also be better used as an alignment mark in the subsequent process.

Referring to fig. 3A-3L, fig. 3A-3L are schematic views illustrating steps of manufacturing an embodiment of a semiconductor package apparatus of the present utility model. The figures have been simplified for ease of understanding.

As shown in fig. 3A to 3L, the manufacturing steps of the semiconductor package apparatus according to an embodiment of the present utility model include:

as shown in fig. 3A, a carrier plate 30 is provided. The surface of the carrier plate 30 may be formed with a first groove 31 and a second groove 32, the first groove 31 being smaller than the second groove 32.

As shown in FIG. 3B, an isolation layer 33 is attached to the surface of the carrier 30, and a sub-layer 34 is formed on the isolation layer 33 by, for example, a physical vapor deposition (Physical Vapor Deposition, PVD) process, the isolation layer 33 and

the seed layer 34 is conformal, i.e., forms the same or a corresponding shape, as the surface of the carrier plate 30. Then, the conductive pillars 16 are formed on the seed layer 34. Here, the fabricated conductive pillars 16 may be placed on the seed layer 34, or a photoresist may be provided on the seed layer 34, and the conductive pillars 16 may be formed on the seed layer 34 by photolithography, development, electroplating, or the like.

As shown in fig. 3C, a first chip 15 is provided, and a first connection member 19 is already provided on the active surface of the first chip 15. The first chip 15 is placed in the second groove 32 with the back of the die facing the carrier 30, and the tape 35 is adhered to the back of the die, and the tape 35 is used to bond the first chip 15 into the second groove 32.

As shown in fig. 3D, a molding is performed to form a first molded structure 10 over the seed layer 34 that encapsulates the first chip 15 and the conductive pillars 16. The first mold structure 10 includes a portion above the surface of the seed layer 34, which is the body structure 11 of the first mold structure 10; and also includes a portion filled in the first recess 31, which forms an alignment portion 12 protruding from a surface of the main body structure 11 (i.e., the first surface 110). As can be seen from the figure, the second recess 32 is also filled with the first molding structure 10 and surrounds the first chip 15, and this portion of the first molding structure 10 will also form the alignment portion 12. After molding, the first molded structure 10 may be thinned by grinding to expose the conductive posts 16 and the first connectors 19 from the first molded structure 10.

As shown in fig. 3E, a second redistribution layer 14 is formed on the first molding structure 10, and the second redistribution layer 14 may be electrically connected to the conductive pillars 16 and may be electrically connected to the first chip 15 through the first connection element 19. Here, the second redistribution layer 14 may include at least one dielectric layer and at least one wiring layer. Alternatively, a plurality of Micro bumps (Micro bumps) may be formed on the second redistribution layer 14.

As in fig. 3F, the structure is shown after removal of carrier plate 30 and spacer layer 33.

As shown in fig. 3G, the structure after etching to remove the seed layer 34 and the tape 35, and turning upside down is shown. At this time, the alignment portion 12 is formed and protrudes from the first surface 110 of the first molding structure 10.

As shown in fig. 3H, at least one second chip 21 is provided, and the active surface of the second chip 21 is provided with second connectors 22. The active surface of the second chip 21 is oriented to the second redistribution layer 14, and the second connection element on the active surface is connected to the micro bump on the second redistribution layer 14 and soldered to the second redistribution layer 14 in a flip-chip manner. Here, the second chip 21 is electrically and physically connected to the second redistribution layer 14 through the second connection member 22.

As shown in fig. 3I, an underfill (underfill) 23 covering the second connection members 22 may be further provided between the second chip 21 and the second redistribution layer 14. The underfill 23 serves to protect the second connection member 22 and to enhance the connection strength.

As shown in fig. 3J, the molding is performed to form a second molding structure 20 that encapsulates the second chip 21. And the second mold structure 20 may be thinned by grinding.

As shown in fig. 3K, the structure formed in fig. 3J is turned upside down, and then a first redistribution layer 13 is formed on the first surface 110 of the first molding structure 10. The manufacturing steps may include: firstly, laminating a dielectric layer, forming a seed layer on the dielectric layer, setting photoresist, performing image transfer by photoetching and developing, forming a circuit layer on the seed layer by electroplating, and finally removing the photoresist and removing redundant seeds by etching

And forming the circuit layer. Here, the first re-wiring layer 13 having a multilayer structure may be formed by repeating the above-described manufacturing steps for a plurality of rounds. Here, the first re-wiring layer 13 formed may include a number of pads 17. Here, the first redistribution layer 13 covers the alignment portion 12 on the first surface 110 of the first mold structure 10, and is in a common shape with the alignment portion 12, that is, a portion covered on the alignment portion 12 corresponds to the shape of the alignment portion 12, and is also in a bump structure.

As shown in fig. 3L, the alignment portion 12 is aligned, ball placement is performed on the pads 17 of the first redistribution layer 13, and a plurality of solder balls 18 are electrically connected to the first redistribution layer 13. The solder balls 18 are configured to connect to an external device, such as a PCB.

Thus, the semiconductor package apparatus of the embodiment of the present utility model is manufactured.

In the manufacturing process of the embodiment of the utility model, the alignment part 12 can be conveniently, quickly and accurately formed after the molding step by forming the first groove 31 on the carrier plate 30; by forming the second groove 32 on the carrier 30, the first chip 15 is placed in the second groove 32, so that the problem of chip displacement caused by the flow of the molding material in the molding step is avoided, and the relative position of the first chip 15 and the alignment part 12 is ensured to be accurate.

While the utility model has been described and illustrated with reference to specific embodiments thereof, the description and illustration is not intended to limit the utility model. It will be apparent to those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof within the embodiments thereof without departing from the true spirit and scope of the utility model as defined by the appended claims. The illustrations may not be drawn to scale. There may be a distinction between technical reproduction and actual implementation in the present utility model due to variables in the manufacturing process, etc. Other embodiments of the utility model not specifically illustrated may exist. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present utility model. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present disclosure. Thus, the order and grouping of the operations is not a limitation of the present utility model unless specifically indicated herein.

Claims

1. A semiconductor package apparatus comprising a mold structure, the mold structure comprising:

a body structure having a first surface;

the alignment part is formed on the first surface, and the top surface of the alignment part and the first surface are positioned on different planes.

2. The semiconductor package apparatus according to claim 1, wherein the alignment portion protrudes from the first surface.

3. The semiconductor package according to claim 1, wherein the alignment portion is recessed from the first surface.

4. The semiconductor package apparatus according to claim 1, further comprising a first redistribution layer provided on the first surface, the first redistribution layer covering the alignment portion and having a portion corresponding to a shape of the alignment portion, the portion being covered on the alignment portion.

5. The semiconductor package apparatus according to claim 4, further comprising a second redistribution layer disposed on the other side of the mold structure with respect to the first redistribution layer, wherein a wiring density of the second redistribution layer is different from a wiring density of the first redistribution layer.

6. The semiconductor package apparatus according to claim 5, wherein the first redistribution layer is a low-density wiring and the second redistribution layer is a high-density wiring compared to the first redistribution layer.

7. The semiconductor package apparatus according to claim 4, further comprising solder balls provided on the first rewiring layer, the alignment portions being lower than the solder balls.

8. The semiconductor package apparatus according to claim 1, further comprising a chip embedded in the molding structure, wherein a back side of the chip faces the first surface, and the back side of the chip and a top surface of the alignment portion are located on different planes.

9. The semiconductor package apparatus according to claim 8, wherein the die back protrudes from the first surface.

10. The semiconductor package according to claim 9, wherein the alignment portion protrudes from the first surface, and the back of the die is vertically interposed between a top surface of the alignment portion and the first surface.