CN220085658U

CN220085658U - Memory circuit and electronic equipment

Info

Publication number: CN220085658U
Application number: CN202320986038.5U
Authority: CN
Inventors: 潘伦; 孙靖峰; 陈聪
Original assignee: Zhejiang Sanhua Intelligent Controls Co Ltd
Current assignee: Zhejiang Sanhua Intelligent Controls Co Ltd
Priority date: 2023-04-25
Filing date: 2023-04-25
Publication date: 2023-11-24
Anticipated expiration: 2033-04-25

Abstract

The embodiment of the utility model provides a storage circuit and electronic equipment. The memory circuit includes: the power supply system comprises a microprocessor, a power switch management circuit, a resistance-capacitance filter network and a memory chip, wherein the microprocessor is electrically connected with the power switch management circuit, the microprocessor is electrically connected with the resistance-capacitance filter network, the power switch management circuit is electrically connected with the memory chip, the resistance-capacitance filter network is electrically connected with the memory chip, and the power switch management circuit is electrically connected with a power supply voltage; the microprocessor is used for controlling the on-off of the power switch management circuit; and the resistance-capacitance filter network is used for filtering interference signals of the microprocessor and the memory chip. According to the technical scheme provided by the embodiment of the utility model, the low-energy consumption control can be performed on the storage circuit based on the power switch management circuit and the resistance-capacitance filter network, and meanwhile, the interference suppression capability and the reliability of the electronic equipment using the storage circuit are improved.

Description

Memory circuit and electronic equipment

[ field of technology ]

The present utility model relates to the field of electronic technologies, and in particular, to a memory circuit and an electronic device.

[ background Art ]

In electronic devices, a memory circuit is basically used, and the memory circuit usually adopts a low-power-consumption charged erasable programmable read-only memory (Electrically Erasable Programmable read only memory, EEPROM for short) ₎ The input power of the chip and the EEPROM chip is directly supplied, and the energy consumption can be always carried out in static state. In addition, the EEPROM Chip is directly and electrically connected to a pin of a System On Chip (SOC) so that electromagnetic compatibility (Electro Magnetic Compatibility, EMC) of the signal line and the SOC is affected, and reliability of an electronic device using the memory circuit is also affected.

[ utility model ]

In view of this, the embodiments of the present utility model provide a memory circuit and an electronic device, which are used for performing low-power control on the memory circuit, and improving the interference suppression capability and the reliability of the electronic device using the memory circuit.

In one aspect, an embodiment of the present utility model provides a memory circuit, including: the power supply switch management circuit is electrically connected with the memory chip, the resistance-capacitance filter network is electrically connected with the memory chip, and the power supply switch management circuit is electrically connected with the power supply voltage;

the microprocessor is used for controlling the power switch management circuit to be turned on and off;

the resistance capacitance filter network is used for filtering the interference signals of the microprocessor and the memory chip.

According to the technical scheme provided by the embodiment of the utility model, the low-energy consumption control can be performed on the storage circuit based on the power switch management circuit and the resistance-capacitance filter network, and meanwhile, the interference suppression capability and the reliability of the electronic equipment using the storage circuit are improved.

[ description of the drawings ]

In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a memory circuit according to an embodiment of the present utility model;

FIG. 2 is a schematic diagram of another memory circuit according to an embodiment of the present utility model;

fig. 3 is a schematic diagram of another memory circuit according to an embodiment of the utility model.

[ detailed description ] of the utility model

For a better understanding of the technical solution of the present utility model, the following detailed description of the embodiments of the present utility model refers to the accompanying drawings.

It should be understood that the described embodiments are merely some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

The terminology used in the embodiments of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. As used in this application and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

It should be understood that the term "and/or" as used herein is merely one way of describing an association of associated objects, meaning that there may be three relationships, e.g., a and/or b, which may represent: the first and second cases exist separately, and the first and second cases exist separately. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship.

The electronic equipment powered by the energy storage battery is a design key point which needs to be considered first for the running current and static power consumption of all electronic circuits in the electronic equipment. Whether consumer electronics or industrial control devices, and even automotive electronics and systems.

With rapid development of science and technology and continuous iteration of consumer demand, functions of electronic devices are also continuously increasing. And is also limited by the current technology, materials, volume, battery management, application environment, etc. of the existing energy storage battery. Therefore, the electronic equipment has long service life and long endurance requirements, and needs to be optimized and improved in each link of the electronic equipment design.

In electronic devices, it is essential that a memory circuit is basically used. Meanwhile, in the electronic products in the age of electronic information and everything interconnection, electromagnetic sensitivity (Electro Magnetic Susceptibility, abbreviated as EMS) and electromagnetic interference (Electro Magnetic Interference, abbreviated as EMI) are also present in the surrounding environment at any time. The low power consumption design and the anti-interference performance of the memory circuit are important for the design of low power consumption electronic products.

An embodiment of the present utility model provides a memory circuit, fig. 1 is a schematic structural diagram of the memory circuit provided in the embodiment of the present utility model, and as shown in fig. 1, the memory circuit includes: the power supply device comprises a microprocessor 1, a power switch management circuit 2, a Resistor-Capacitance circuit (RC) filter network 3 and a memory chip 4, wherein the microprocessor 1 is electrically connected with the power switch management circuit 2, the microprocessor 1 is electrically connected with the Resistor-capacitor filter network 3, the power switch management circuit 2 is electrically connected with the memory chip 4, the Resistor-capacitor filter network 3 is electrically connected with the memory chip 4, and the power switch management circuit 2 is electrically connected with a power supply voltage (Volt Current Condenser, VCC).

The microprocessor 1 is used for controlling the power switch management circuit 2 to be turned on and off.

The resistor-capacitor filter network 3 is used for filtering the interference signals of the microprocessor 1 and the memory chip 4.

In one embodiment of the present utility model, the microprocessor 1 includes an SOC microprocessor or microprocessor unit (Microcontroller Unit, MCU for short).

The microprocessor 1 is the core of the controller system, and loads the control, monitoring, communication interaction, storage, management and the like of all peripheral functional circuits. The microprocessor 1 can control the power switch management circuit 2 to be turned on and off by a control signal set by itself according to a program, for example, the control signal is mcu_ctl. Therefore, the energy consumption control of the storage circuit is realized, the energy consumption of the storage circuit is in a minimum state, and the redundant energy consumption of an input power supply is reduced, so that a certain help is provided for prolonging the service life of the battery.

In an embodiment of the utility model, the RC filter network 3 may also be referred to as an RC circuit or RC filter.

In one embodiment of the present utility model, the rc filter network 3 is electrically connected to the memory chip 4 through a serial bus. For example, serial buses include a serial peripheral interface (Serial Peripheral Interface, SPI) bus or an integrated circuit bus (Inter-Integrated Circuit, IIC).

In an embodiment of the present utility model, the rc filter network 3 may optimize and improve the EMC performance of the microprocessor 1 and the memory chip 4 through the SPI bus.

In one embodiment of the present utility model, the memory chip 4 comprises an EEPROM chip.

As an alternative, the communication rate of the EEPROM chip of the SPI bus serial interface is much higher than the communication rate of the IIC bus serial interface. Meanwhile, the operation of millions of writing cycles is performed, the data retention time is hundreds of years, and the requirements of the pull-up resistor and the pull-down resistor compatible with SPI protocol can be met according to the electrical connection requirements of the SPI bus.

Fig. 2 is a schematic structural diagram of another memory circuit provided in the embodiment of the present utility model, and as shown in fig. 2, the microprocessor 1 includes a first interface 11, a second interface 12, a third interface 13, a fourth interface 14, a fifth interface 15, and a sixth interface 16, the power switch management circuit 2 includes a seventh interface 21, and the rc filter network 3 includes an eighth interface 31, a ninth interface 32, a tenth interface 33, an eleventh interface 34, and a twelfth interface 35; the first interface 11 is electrically connected to the seventh interface 21, the second interface 12 is electrically connected to the eighth interface 31, the third interface 13 is electrically connected to the ninth interface 32, the fourth interface 14 is electrically connected to the tenth interface 33, the fifth interface 15 is electrically connected to the eleventh interface 34, and the sixth interface 16 is electrically connected to the twelfth interface 35.

The power switch management circuit 2 further includes a thirteenth interface 22, the rc filter network 3 further includes a fourteenth interface 36, a fifteenth interface 37, a sixteenth interface 38, a seventeenth interface 39, and an eighteenth interface 40, and the memory chip 4 includes a nineteenth interface 41, a twentieth interface 42, a twenty-first interface 43, a twenty-second interface 44, a twenty-third interface 45, and a twenty-fourth interface 46; the thirteenth interface 22 is electrically connected with the nineteenth interface 41, the fourteenth interface 36 is electrically connected with the twentieth interface 42, the fifteenth interface 37 is electrically connected with the twenty-first interface 43, the sixteenth interface 38 is electrically connected with the twenty-second interface 44, the seventeenth interface 39 is electrically connected with the twenty-third interface 45, and the eighteenth interface 40 is electrically connected with the twenty-fourth interface 46.

The embodiment of the utility model provides another memory circuit, and fig. 3 is a schematic structural diagram of the another memory circuit provided in the embodiment of the utility model, as shown in fig. 3, a resistor-capacitor filter network in the memory circuit includes a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5 and a sixth capacitor C6, a second interface 12 is electrically connected with a twentieth interface 42 (mcu_/CS chip-select serial interface) through the sixth resistor R6, the second interface 12 is electrically connected with a first end of the second capacitor C2, and a second end of the second capacitor C2 is grounded; the third interface 13 is electrically connected with a twenty-first interface 43 (MCU_SO data output serial interface) through a seventh resistor R7, the third interface 13 is electrically connected with a first end of a third capacitor C3, and a second end of the third capacitor C3 is grounded; the fourth interface 14 is electrically connected with a twenty-second interface 44 (MCU_/WP write protection serial interface) through an eighth resistor R8, the fourth interface 14 is electrically connected with a first end of a fourth capacitor C4, and a second end of the fourth capacitor C4 is grounded; the fifth interface 15 is electrically connected with a twenty-third interface 45 (mcu_si data input serial interface) through a tenth resistor R10, the fifth interface 15 is electrically connected with a first end of a fifth capacitor C5, and a second end of the fifth capacitor C5 is grounded; the sixth interface 16 is electrically connected to a twenty-fourth interface 46 (MCUSCK high-speed clock serial interface) through a ninth resistor R9, the sixth interface 16 is electrically connected to a first terminal of a sixth capacitor C6, and a second terminal of the sixth capacitor C6 is grounded. Wherein,

the twenty-fourth interface 46 is electrically connected to the first end of the eleventh resistor R11, and the second end of the eleventh resistor R11 is grounded, where the eleventh resistor R11 is a pull-down resistor of the twenty-fourth interface 46, and is used for normal level requirements of the SPI bus.

The power switch management circuit 2 comprises a first resistor R1, a second resistor R2 and an electronic switch Q1, wherein the microprocessor 1 is connected with the second resistor R2 in series through a first interface 11, the second resistor R2 is connected with the first resistor R1 in series, and the first resistor R1 is electrically connected with the electronic switch Q1 in parallel.

In one embodiment of the present utility model, the electronic switch Q1 includes a transistor or a field effect transistor. For example, the electronic switch Q1 includes a PNP transistor, an NPN transistor, an N-type substrate, a p-channel, a MOS transistor (positive channel Metal Oxide Semiconductor, PMOS) field effect transistor for carrying a current by a flow of holes, or an N-Metal-Oxide-Semiconductor (NMOS) field effect transistor.

The base of the electronic switch Q1 is electrically connected to the first resistor R1 and the second resistor R2, the emitter of the electronic switch Q1 is electrically connected to the supply voltage VCC and the first resistor R1, the collector of the electronic switch Q1 is electrically connected to the first end of the first capacitor C1 and the nineteenth interface 41 (mcu_vcc power supply serial interface) of the memory chip 4, and the second end of the first capacitor C1 is grounded. The first end of the first resistor R1 is electrically connected to the power supply voltage VCC and the emitter of the electronic switch Q1, and the second end of the first resistor R1 is electrically connected to the second resistor R2 and the base of the electronic switch Q1.

The collector of the electronic switch Q1 is electrically connected to a third resistor R3, a fourth resistor R4 and a fifth resistor R5, the third resistor R3 is connected in series with a sixth resistor R6, the fourth resistor R4 is connected in series with an eighth resistor R8, and the fifth resistor R5 is electrically connected to a twenty-fifth interface 47 (mcu_/HOLD device HOLD serial interface) of the memory chip 4.

The memory chip 4 further includes a twenty-sixth interface 48 (mcu_gnd ground serial interface), and the twenty-sixth interface 48 is grounded.

In an embodiment of the present utility model, the microprocessor 1 is responsible for outputting the control signals for turning on and off the power switch management circuit 2. And only when the memory chip 4 and the microprocessor 1 need to exchange data, the control signal MCU_CTL is controlled to output a low level, so that the electronic switch Q1 meets the conduction condition, and the power supply voltage VCC supplies power to the nineteenth interface 41 of the memory chip 4, thereby meeting the working condition of the memory chip 4.

The second resistor R2 is a current limiting resistor of the base of the electronic switch Q1, and is prevented from being damaged due to overcurrent. The first resistor R1 is a pull-up resistor of the base of the electronic switch Q1, so that the base of the electronic switch Q1 is normally pulled up to a high level state, and malfunction caused by unfixed level of the base of the electronic switch Q1 is prevented. The electronic switch Q1 may input the power supply voltage VCC to the nineteenth interface 41 of the memory chip 4 or may turn off the power supply voltage VCC. The first capacitor C1 is a bypass capacitor of the nineteenth interface 41 of the memory chip 4 for suppressing noise interference signals.

The third resistor R3, the fourth resistor R4, and the fifth resistor R5 are pull-up resistors for being compatible with the requirements of the SPI protocol bus level, so that the twentieth interface 42 (mcu_/CS chip select serial interface), the twenty-second interface 44 (mcu_/WP write protect serial interface), and the twenty-fifth interface 47 (mcu_/HOLD device HOLD serial interface) are normally pulled up to the power supply voltage VCC.

The memory chip 4 is an EEPROM memory chip of SPI serial bus interface, and is used for program storage of frequent rewriting.

The filter circuit comprises a sixth resistor R6, a second capacitor C2, a seventh resistor R7, a third capacitor C3, an eighth resistor R8 and a fourth capacitor C4, wherein a ninth resistor R9, a sixth capacitor C6, a tenth resistor R10 and a fifth capacitor C5 are respectively a twentieth interface 42 (MCU_/CS chip selection serial interface), a twenty-first interface 43 (MCU_SO data output serial interface), a twenty-second interface 44 (MCU_/WP write protection serial interface), a twenty-fourth interface 46 (MCU_SCK high-speed clock serial interface) and a twenty-third interface 45 (MCU_SI data input serial interface) and a filter network of each bus serial port signal, and the filter circuit is used for filtering high-frequency interference signals on signal lines, SO that the high-frequency interference signals are prevented from affecting the operation of the microprocessor 1 and the memory chip 4, and the abnormal operation of the microprocessor 1 and the memory chip 4 is prevented.

In the technical scheme provided by the embodiment of the utility model, the storage circuit comprises: the power supply system comprises a microprocessor, a power switch management circuit, a resistance-capacitance filter network and a memory chip, wherein the microprocessor is electrically connected with the power switch management circuit, the microprocessor is electrically connected with the resistance-capacitance filter network, the power switch management circuit is electrically connected with the memory chip, the resistance-capacitance filter network is electrically connected with the memory chip, and the power switch management circuit is electrically connected with a power supply voltage; the microprocessor is used for controlling the on-off of the power switch management circuit; and the resistance-capacitance filter network is used for filtering interference signals of the microprocessor and the memory chip. According to the technical scheme provided by the embodiment of the utility model, the low-energy consumption control can be performed on the storage circuit based on the power switch management circuit and the resistance-capacitance filter network, and meanwhile, the interference suppression capability and the reliability of the electronic equipment using the storage circuit are improved.

In the technical scheme provided by the embodiment of the utility model, the energy consumption of the EEPROM storage circuit can be minimized by controlling the on/off of the input power supply of the EEPROM storage chip. The power is turned on and input only when the microprocessor needs to communicate with the EEPROM memory chip. The static power consumption of the EEPROM storage circuit can be reduced to the maximum extent, and a certain help is provided for long endurance.

According to the technical scheme provided by the embodiment of the utility model, the communication speed of the SPI bus is higher, and the communication requirement of the high-speed communication speed can be met.

In the technical scheme provided by the embodiment of the utility model, the RC filter network is used for suppressing the high-frequency interference and crosstalk signals between the signal wires on the SPI bus, so that the high-frequency interference and the crosstalk signals are released to the ground, and the microprocessor and the memory chip work more reliably.

The embodiment of the utility model provides electronic equipment, which comprises the memory circuit.

In an embodiment of the present utility model, the electronic device is an electronic device with low power consumption requirements, for example, the electronic device includes a thermal management controller.

The foregoing description of the preferred embodiments of the utility model is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the utility model.

Claims

1. A memory circuit, comprising: the power supply management circuit comprises a microprocessor (1), a power supply switch management circuit (2), a resistance capacitance filter network (3) and a memory chip (4), wherein the microprocessor (1) is electrically connected with the power supply switch management circuit (2), the microprocessor (1) is electrically connected with the resistance capacitance filter network (3), the power supply switch management circuit (2) is electrically connected with the memory chip (4), the resistance capacitance filter network (3) is electrically connected with the memory chip (4), and the power supply switch management circuit (2) is electrically connected with a power supply voltage VCC;

the microprocessor (1) is used for controlling the power switch management circuit (2) to be turned on and off;

the resistance capacitance filter network (3) is used for filtering interference signals of the microprocessor (1) and the memory chip (4).

2. The memory circuit according to claim 1, wherein the microprocessor (1) comprises a first interface (11), a second interface (12), a third interface (13), a fourth interface (14), a fifth interface (15) and a sixth interface (16), the power switch management circuit (2) comprises a seventh interface (21), and the resistive-capacitive filter network (3) comprises an eighth interface (31), a ninth interface (32), a tenth interface (33), an eleventh interface (34) and a twelfth interface (35); the first interface (11) is electrically connected with the seventh interface (21), the second interface (12) is electrically connected with the eighth interface (31), the third interface (13) is electrically connected with the ninth interface (32), the fourth interface (14) is electrically connected with the tenth interface (33), the fifth interface (15) is electrically connected with the eleventh interface (34), and the sixth interface (16) is electrically connected with the twelfth interface (35).

3. The memory circuit according to claim 2, wherein the power switch management circuit (2) further comprises a thirteenth interface (22), the rc filter network (3) further comprises a fourteenth interface (36), a fifteenth interface (37), a sixteenth interface (38), a seventeenth interface (39) and an eighteenth interface (40), the memory chip (4) comprises a nineteenth interface (41), a twentieth interface (42), a twenty-first interface (43), a twenty-second interface (44), a twenty-third interface (45) and a twenty-fourth interface (46); wherein the thirteenth interface (22) is electrically connected with the nineteenth interface (41), the fourteenth interface (36) is electrically connected with the twentieth interface (42), the fifteenth interface (37) is electrically connected with the twenty-first interface (43), the sixteenth interface (38) is electrically connected with the twenty-second interface (44), the seventeenth interface (39) is electrically connected with the twenty-third interface (45), and the eighteenth interface (40) is electrically connected with the twenty-fourth interface (46).

4. A memory circuit according to claim 3, characterized in that the resistive-capacitive filter network comprises a sixth resistor (R6), a seventh resistor (R7), an eighth resistor (R8), a ninth resistor (R9), a tenth resistor (R10), a second capacitor (C2), a third capacitor (C3), a fourth capacitor (C4), a fifth capacitor (C5) and a sixth capacitor (C6), the second interface (12) being electrically connected to the twentieth interface (42) via the sixth resistor (R6), the second interface (12) being electrically connected to a first end of the second capacitor (C2), a second end of the second capacitor (C2) being grounded; the third interface (13) is electrically connected with the twenty-first interface (43) through the seventh resistor (R7), the third interface (13) is electrically connected with the first end of the third capacitor (C3), and the second end of the third capacitor (C3) is grounded; the fourth interface (14) is electrically connected with the twenty-second interface (44) through the eighth resistor (R8), the fourth interface (14) is electrically connected with the first end of the fourth capacitor (C4), and the second end of the fourth capacitor (C4) is grounded; the fifth interface (15) is electrically connected with the twenty-third interface (45) through the tenth resistor (R10), the fifth interface (15) is electrically connected with the first end of the fifth capacitor (C5), and the second end of the fifth capacitor (C5) is grounded; the sixth interface (16) is electrically connected with the twenty-fourth interface (46) through the ninth resistor (R9), the sixth interface (16) is electrically connected with the first end of the sixth capacitor (C6), and the second end of the sixth capacitor (C6) is grounded.

5. The memory circuit of claim 4, wherein the twenty-fourth interface (46) is electrically connected to a first terminal of an eleventh resistor (R11), a second terminal of the eleventh resistor (R11) being grounded.

6. The memory circuit according to claim 1, characterized in that the power switch management circuit (2) comprises a first resistor (R1), a second resistor (R2) and an electronic switch (Q1), the microprocessor (1) being connected in series with the second resistor (R2) through a first interface (11), the second resistor (R2) being connected in series with the first resistor (R1), the first resistor (R1) being electrically connected in parallel with the electronic switch (Q1).

7. The memory circuit according to claim 6, characterized in that the base of the electronic switch (Q1) is electrically connected to the first resistor (R1) and the second resistor (R2), the emitter of the electronic switch (Q1) is electrically connected to a supply Voltage (VCC) and the first resistor (R1), the collector of the electronic switch (Q1) is electrically connected to a first end of a first capacitor (C1) and a nineteenth interface (41) of the memory chip (4), and the second end of the first capacitor (C1) is grounded.

8. The memory circuit according to claim 7, characterized in that the collector is electrically connected to a third resistor (R3), a fourth resistor (R4) and a fifth resistor (R5), the third resistor (R3) being connected in series with a sixth resistor (R6), the fourth resistor (R4) being connected in series with an eighth resistor (R8), the fifth resistor (R5) being electrically connected to a twenty-fifth interface (47) of the memory chip (4).

9. The memory circuit according to claim 1, wherein the memory chip (4) further comprises a twenty-sixth interface (48), the twenty-sixth interface (48) being grounded.

10. An electronic device comprising a memory circuit as claimed in any one of claims 1 to 9.