CN220067509U - Display information scrambling device - Google Patents

Abstract

The utility model discloses a display information scrambling device, which comprises display information scrambling equipment, a display screen, a synchronous signal transmitter and synchronous glasses; the display information scrambling device is provided with a display information input interface and a display information output interface, wherein the display information input interface is used for inputting display information, and the display information output interface is used for outputting scrambled display information to the display screen; the display information scrambling device also transmits a synchronization signal to the synchronization glasses through a synchronization signal transmitter. The device realizes that the device can normally watch through the synchronous glasses, and the scrambling picture is obtained when the display screen is shot without the synchronous glasses or by adopting shooting equipment, and can realize various scrambling effects through various different algorithms, thereby being applicable to various application scenes.

Description

Display information scrambling device

Technical Field

The utility model relates to the technical field of display, in particular to a display information scrambling device.

Background

At present, various display terminals (such as a liquid crystal display, a conference integrated machine, an LED display screen and the like) are widely applied to various occasions such as daily offices, conference rooms, monitoring rooms and the like. However, in some application scenarios, the content displayed by the display terminal is not expected to be watched and recorded by unauthorized people, so that a corresponding technical means is required to realize the safety protection function of the displayed content, or the content of the display screen cannot be obtained when the unauthorized people cannot watch the display information of the display screen, shoot and record or shoot the display screen by using a video camera or a camera, and meanwhile, the person can be ensured to watch the content displayed on the display screen normally.

Aiming at the scene, a device for encrypting or scrambling the display information needs to be designed, so that the information on the display screen is protected, unauthorized persons cannot watch the content of the display screen, and clear display content cannot be obtained through recording and photographing.

Disclosure of Invention

The utility model mainly solves the technical problems of providing a display information scrambling device, solving the problems of lack of safety protection on display contents of a display screen, preventing unauthorized persons from watching and illegally shooting, and not affecting normal watching of authorized persons in the prior art.

In order to solve the technical problems, the utility model adopts a technical scheme that the display information scrambling device comprises display information scrambling equipment, a display screen, a synchronous signal transmitter and synchronous glasses; the display information scrambling device is provided with a display information input interface and a display information output interface, wherein the display information input interface is used for inputting display information, and the display information output interface is used for outputting scrambled display information to the display screen; the display information scrambling device also transmits a synchronization signal to the synchronization glasses through the synchronization signal transmitter.

Preferably, the display information scrambling device comprises a shell and a PCB circuit board arranged in the shell, wherein the display information input interface and the display information output interface are both arranged on the PCB circuit board, and the PCB circuit board is also provided with a video decoding chip IT68052, a scrambling control module and a video encoding chip IT6264; the display information input interface is electrically connected with the scrambling control module through the video decoding chip IT68052, and the scrambling control module is electrically connected with the display information output interface through the video encoding chip IT 6264.

Preferably, the scrambling control module includes a core logic unit, an input logic unit and an output logic unit, where the core logic unit is electrically connected with the video decoding chip IT68052 through the input logic unit and is electrically connected with the video encoding chip IT6264 through the output logic unit.

Preferably, a single chip microcomputer is arranged on the PCB, and the single chip microcomputer is electrically connected with the video decoding chip IT68052, the video encoding chip IT6264 and the scrambling control module.

Preferably, a scrambling control switch and an infrared receiving module are arranged on the PCB, and the scrambling control switch and the infrared receiving module are electrically connected with the single chip microcomputer.

Preferably, a program upgrade circuit is provided on the PCB, and the program upgrade circuit includes a program upgrade interface and an oscillator chip CP2102 electrically connected with the program upgrade interface.

Preferably, the housing comprises an upper housing and a lower housing which are detachably connected.

Preferably, the upper shell comprises a top panel, and a left panel and a right panel which are perpendicular to the top panel, wherein a plurality of heat dissipation holes are formed in the left panel and the right panel.

Preferably, the lower housing includes a bottom panel, and front and rear panels perpendicular to the bottom panel, and the front panel is provided with a plurality of through holes.

Preferably, the display information scrambling device has a synchronization signal interface for connecting the synchronization signal transmitter.

The beneficial effects of the utility model are as follows: the utility model discloses a display information scrambling device, which comprises display information scrambling equipment, a display screen, a synchronous signal transmitter and synchronous glasses; the display information scrambling device is provided with a display information input interface and a display information output interface, wherein the display information input interface is used for inputting display information, and the display information output interface is used for outputting scrambled display information to the display screen; the display information scrambling device also transmits a synchronization signal to the synchronization glasses through a synchronization signal transmitter. The device realizes that the device can normally watch through the synchronous glasses, and the scrambling picture is obtained when the synchronous glasses are not worn or the shooting equipment is adopted to shoot the display screen, and can realize a plurality of different scrambling effects through a plurality of different algorithms, thereby being applicable to a plurality of application scenes.

Drawings

FIG. 1 is a block diagram showing an embodiment of an information scrambling apparatus according to the present utility model;

FIG. 2 is a schematic diagram showing the constitution of a display information scrambling circuit in a display information scrambling apparatus according to the present utility model;

FIG. 3 is a schematic diagram showing the constitution of a scrambling control module in an information scrambling apparatus according to the present utility model;

FIG. 4 is a schematic diagram of a single chip microcomputer in a display information scrambling device according to the present utility model;

FIG. 5 is a schematic diagram of a communication module of a single chip microcomputer in a display information scrambling device according to the present utility model;

fig. 6 is a schematic diagram of an oscillator chip CP2102 in a display information scrambling apparatus of the present utility model;

FIG. 7 is a schematic diagram of a program upgrade interface of a display information scrambling device in a display information scrambling apparatus according to the present utility model;

FIG. 8 is a schematic diagram of a video decoding chip IT68052 in a display information scrambling device according to the present utility model;

FIG. 9 is a schematic diagram of a display information input interface in a display information scrambling device according to the present utility model;

FIG. 10 is a schematic diagram of an input logic unit in a display information scrambling device according to the present utility model;

FIG. 11 is a schematic diagram of a video encoding chip IT6264 in a display information scrambling device according to the present utility model;

FIG. 12 is a schematic diagram of a display information output interface in a display information scrambling apparatus according to the present utility model;

FIG. 13 is a schematic diagram of an output logic unit in a display information scrambling device according to the present utility model;

FIG. 14 is a schematic diagram of a memory logic unit in a display information scrambling device according to the present utility model;

FIG. 15 is a schematic diagram of a memory chip MT41J64M16JT in a display information scrambling device according to the present utility model;

FIG. 16 is a schematic diagram of a clock logic unit in a display information scrambling device according to the present utility model;

FIG. 17 is a schematic diagram showing a clock generator ICS844021I in the information scramble apparatus of the present utility model;

FIG. 18 is a schematic diagram of debug logic in a display information scrambling apparatus according to the present utility model;

FIG. 19 is a schematic diagram of a debug interface in a display information scrambling apparatus according to the present utility model;

FIG. 20 is a schematic diagram showing a power supply circuit in the information scrambling device of the present utility model;

FIG. 21 is a front view of a display information scrambling apparatus in a display information scrambling device of the present utility model;

FIG. 22 is a side view of a display information scrambling device in a display information scrambling apparatus of the present utility model;

FIG. 23 is an exploded schematic view of a display information scrambling apparatus in a display information scrambling device of the present utility model;

fig. 24 is a schematic view of a pair of synchronous glasses in a display information scrambling device according to the present utility model.

Detailed Description

In order that the utility model may be readily understood, a more particular description thereof will be rendered by reference to specific embodiments that are illustrated in the appended drawings. Preferred embodiments of the present utility model are shown in the drawings. This utility model may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. The terminology used in the description of the utility model herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. The term "and/or" as used in this specification includes any and all combinations of one or more of the associated listed items.

Fig. 1 shows a schematic diagram showing the composition of an embodiment of the information scrambling apparatus. In fig. 1, the apparatus includes: a display screen 1, a display information scrambling device 2 and synchronization glasses 3, and a synchronization signal transmitter 21. The display information input interface of the display information scrambling device 2 inputs a first screen 11 (i.e., display information) to be displayed, and the first screen 11 may be derived from various video devices, for example, a mobile phone, a computer, or the like, which has a function of transmitting display information, and is input to the display information scrambling device 2 by a wired or wireless method.

The display information output interface of the display information scrambling device 2 outputs scrambled display information to the display screen 1, the scrambled display information includes a first screen 11 and a second screen 12 interfering with the first screen 11, the display information scrambling device 2 controls the display screen 1 to alternately and cyclically display the first screen 11 and the second screen 12 in time, the content displayed by the second screen is regarded as the interference to the first screen, and since the display time of each frame image in the first screen 11 and each frame image in the second screen 12 is very short, when the human eyes directly watch and shoot the device, the screen to be watched is a mixed screen of the first screen 11 and the second screen 12, whereby the screen displayed as a whole by the display screen 1 is a scrambled screen mixed with a normal screen and an interfering screen. The scrambled pictures comprise incomplete pictures, and pictures with unclear or fuzzy overall or partial display, namely, clear, complete and effective shot pictures and videos cannot be formed, so that the visual effect is affected and the visual fatigue is generated.

Preferably, the display screen is a large screen comprising a liquid crystal display, a conference integrated machine, an LED display array and other various display terminal devices.

Here, the first frame 11 is not a specific single frame, but a frame sequence including a plurality of frame images, and thus the first frame 11 may be regarded as a short for the first frame sequence. Similarly, the second frame 12 is not a specific single frame, but a frame sequence including a plurality of frame images, and thus the second frame 12 may be regarded as an abbreviation of the second frame sequence. Therefore, the alternately displayed first screen 11 and second screen 12 in time here refers to actually alternately displaying each frame of image in the first screen sequence and each frame of image in the second screen sequence in a cyclic manner.

Therefore, in this case, when the photographing apparatus 4, including various video recording and image photographing apparatuses having photographing and photographing functions, is used, the whole picture of the photographed display screen is a scrambled picture which is abnormally displayed, display effects such as incomplete, ghost, splash screen, disordered text, mosaic, loss of sensitive information hiding, etc. occur, and thus the photographed video and image cannot be normally viewed and recognized, or important sensitive information in the picture is shielded, and the whole screen or the sensitive display area loses the definition required by normal display, thereby having the purpose of preventing photographing. Or, the photographed display content is distorted, cannot be recovered and affects the actual look and feel, and causes look and feel fatigue and visual impairment.

Correspondingly, when the display screen 1 displays the first picture 11, the synchronous glasses 3 receive the synchronous signal from the display information scrambling equipment 2, and control the two lenses of the synchronous glasses 3 to be synchronously opened, and at the moment, the lamplight of the display screen 1 is watched through the two lenses; when the display screen 1 displays the second picture, the two lenses of the synchronous glasses 3 are synchronously closed, and at the moment, the light of the display screen 1 is blocked by the two lenses and is not watched. So that only the normal first picture display content can be seen through the synchronization glasses 3.

Preferably, the synchronous opening and closing control of the synchronous glasses 3 is controlled by the display information scrambling device 2, and the display information scrambling device 2 sends a synchronous control signal to the synchronous glasses 3 through wireless communication signals such as infrared, wireless electromagnetic waves, bluetooth and the like, so that the synchronous glasses 3 are kept synchronous with the switching of the first screen 11 and the second screen 12. In fig. 1, the display information scrambling device 2 transmits a synchronization signal to the synchronization glasses 3 through a synchronization signal transmitter 21. The synchronization control signal may be a spread spectrum encrypted signal, whereby the synchronization control signal may be prevented from being disturbed and losing control of the synchronization glasses. Therefore, the synchronization glasses 3 are controlled by the synchronization of the display information scrambling device 2 so as to be synchronized with the switching of the first screen 11 and the second screen 12.

The above is a description of the composition and operation principle of the display information scrambling device, and the following describes further a display information scrambling circuit in the display information scrambling apparatus 2, which is disposed on a PCB circuit board in the display information scrambling apparatus 2.

As shown in fig. 2, the display information scrambling circuit includes a single-chip microcomputer a01, a display information input circuit a02 electrically connected to the single-chip microcomputer a01, a scrambling control module a04, and a display information output circuit a03. The singlechip A01 is used for configuring a display information input circuit A02, a scrambling control module A04 and a display information output circuit A03; the display information input circuit a02 is used for converting input display information and outputting the display information to the scrambling control circuit a04, the scrambling control module a04 is used for scrambling the display information and outputting the display information to the display information output circuit a03, and the display information output circuit a03 is used for converting and outputting the scrambled display information.

Further, as shown in fig. 3, in the present utility model, the scrambling control module a04 is designed by an xc7a75tfgg484 programmable logic device through an algorithm, so as to implement a scrambling function for display information. The scrambling control module A04 comprises a core logic unit B01, an input logic unit B02, an output logic unit B03, a singlechip communication logic unit B04, a storage logic unit B05, a clock logic unit B06 and a debugging logic unit B07.

In the scrambling control module a04, an input logic unit B02 is electrically connected to the display information input circuit a02, an output logic unit B03 is electrically connected to the display information output circuit a03, a single-chip microcomputer communication logic unit B04 is electrically connected to the single-chip microcomputer, a storage logic unit B05 is electrically connected to a storage chip, a clock logic unit B06 is electrically connected to a clock generator, and a debug logic unit B07 is electrically connected to a debug interface.

Further, as shown in fig. 4, in the present utility model, the singlechip is a chip STM32F103RETX, and the singlechip is powered by the second dc power supply +3.3v.

In fig. 4, the singlechip is electrically connected with a scrambling control switch SWDIO, and the scrambling control terminal PA13 of the singlechip in fig. 4 is electrically connected with the scrambling control switch SWDIO. The scramble control switch SWDIO can control whether the above-described scramble control module a04 scrambles the input display information. For example: after the scrambling control switch SWDIO is turned on, the scrambling control module A04 scrambles the input display information, and the scrambling control module A04 outputs the scrambled display information; and when the scrambling control switch SWDIO is closed, the scrambling control module A04 outputs unscrambled display information, and normal display information is displayed on the display screen 1.

Further, the 33 th pin to the 36 th pin of the singlechip in fig. 4 are connected with the singlechip communication module B04 (BANK 14) in fig. 5 through an SPI synchronous serial bus, and the 53 rd pin and the 54 th pin of the singlechip in fig. 4 are also connected with the singlechip communication module B04 (BANK 14) in fig. 5 through serial port communication, so that the singlechip can carry out configuration parameters on the scrambling control module A04; in fig. 5, the singlechip communication module B04 (BANK 14) is powered by the second dc power supply +3.3v.

Further, as shown in fig. 6 and fig. 7, the single chip microcomputer in fig. 4 is further connected with a program upgrade circuit, and the program upgrade circuit includes a program upgrade interface J4 and an oscillator chip CP2102 connected to the program upgrade interface J4. The VBUS end of the oscillator chip CP2102 is electrically connected to the first core of the program upgrade interface J4; the first data input end D of the oscillator chip CP2102 is electrically connected with the second core of the program upgrade interface J4, and the second data input end D+ of the oscillator chip CP2102 is electrically connected with the third core of the USB interface J4; the serial port writing end TXD of the oscillator chip CP2102 is electrically connected to the serial port reading end PB10 of the single chip microcomputer in fig. 4, and the serial port reading end RXD of the oscillator chip CP2102 is electrically connected to the serial port writing end PB11 of the single chip microcomputer in fig. 4.

Preferably, the program upgrading interface J4 is a USB interface, and the program of the scrambling control module A04 can be updated on line through the USB interface, and the program is programmed into the scrambling control module A04 by the singlechip in an SPI mode, so that corresponding interference programs can be correspondingly input according to different display information, and the optimal interference effect can be obtained.

Further, as shown in fig. 8 and 9, the display information input circuit includes a display information input interface J1 and a video decoding chip IT68052, where the display information input interface J1 is used to input display information and is electrically connected to the scrambling control module a04 through the video decoding chip IT 68052; the video decoding chip IT68052 is used for converting the image input by the display information input interface J1, that is, converting the HDMI format signal into an LVDS signal and outputting the LVDS signal to the scrambling control module a04. Specifically, the video decoding chip IT68052 is electrically connected to the core logic unit B01 in the scrambling control module a04 through the input logic unit B02.

In fig. 8, pin 31 of the video decoding chip IT68052 is electrically connected to pin 19 of the input interface J1 shown in fig. 9; the 18 th pin of the display input interface J1 is electrically connected with the third direct current +5V; the 26 th pin and the 27 th pin of the video decoding chip IT68052 are correspondingly and electrically connected with the 16 th pin and the 15 th pin of the display input interface J1; the 31 st pin of the video decoding chip IT68052 is electrically connected with the 13 th pin of the display input interface J1 in FIG. 7, and the 41 st pin to the 49 th pin of the video decoding chip IT68052 are correspondingly electrically connected with the 12 th pin, the 10 th pin, the 9 th pin, the 7 th pin, the 6 th pin, the 4 th pin, the 3 rd pin and the 1 st pin of the display input interface; the 12 th pin to the 15 th pin of the video decoding chip IT6264 are correspondingly and electrically connected with the 6 th pin, the 4 th pin, the 3 rd pin and the 1 st pin of the display output interface J1.

Preferably, the display information input interface J1 is an HDMI interface.

Further, as shown in fig. 10, the video decoding chip IT68052 is electrically connected to the input logic unit B02 (BANK 15), and the input logic unit B02 (BANK 15) is powered by the fourth dc power supply +2.5v.

Further, in fig. 8, the data end PCSDA (pin 22) of the video decoding chip IT68052 is electrically connected to the first data end PC2 of the single-chip microcomputer in fig. 4, the clock end PCSCL (pin 23) of the video decoding chip IT68052 is electrically connected to the first clock end PC1 of the single-chip microcomputer in fig. 4, the synchronization end INT (pin 20) of the video decoding chip IT68052 is electrically connected to the first synchronization control end PC3 of the single-chip microcomputer in fig. 4, and the SCDT end (pin 17) of the video decoding chip IT68052 is electrically connected to the input/output end PA1 of the single-chip microcomputer in fig. 4, so that the single-chip microcomputer can perform configuration parameters on the video decoding chip IT 68052.

Further, as shown in fig. 11 and 12, the display information output circuit includes a display information output interface J2 and a video encoding chip IT6264, where the video encoding chip IT6264 is electrically connected to the output logic unit B03, and is configured to convert the LVDS signal into an HDMI signal; and the display information output interface J2 is also electrically connected, and the display information output interface J2 is used for outputting scrambled display information.

In fig. 11, pins 1 to 3 of the video encoding chip IT6264 are correspondingly and electrically connected with pins 19, 16 and 15 of the information output interface J2 shown in fig. 12; the 7 th pin to the 10 th pin of the chip IT6264 are correspondingly and electrically connected with the 12 th pin, the 10 th pin, the 9 th pin and the 7 th pin of the display information output interface J2; the 12 th pin to the 15 th pin of the chip IT6264 are correspondingly and electrically connected with the 6 th pin, the 4 th pin, the 3 rd pin and the 1 st pin of the display information output interface J2; the power supply end of the display information output interface J2 is powered by a +5V power supply.

In fig. 11, a data end PCSDA (34 th pin) of the video coding chip IT6264 is electrically connected to a second data end PA5 of the single-chip microcomputer in fig. 4, a clock end PCSCL (35 th pin) of the video coding chip IT6264 is electrically connected to a second clock end PA6 of the single-chip microcomputer in fig. 4, and a synchronization end INT (33 rd pin) of the video coding chip IT6264 is electrically connected to a second synchronization control end PA4 of the single-chip microcomputer in fig. 4, so that the single-chip microcomputer can perform configuration parameters on the video coding chip IT 6264.

Further, as shown in fig. 13, a schematic diagram of an output logic unit B03 (BANK 16), the video encoding chip IT6264 is electrically connected to the output logic unit B03 (BANK 16), and the output logic unit B03 (BANK 16) is powered by a fourth dc power source +2.5v.

Further, as shown in fig. 14 and 15, fig. 14 is a schematic diagram of a memory logic unit B05 (BANK 34), and fig. 15 is a schematic diagram of a memory chip MT41J64M16JT. The core logic unit B01 in the scrambling control module is electrically connected with the memory chip MT41J64M16JT through the memory logic unit B05 (BANK 34).

In fig. 15, the address terminals (DDRA 0 to a12, ddr_ba0, ddr_ba1, ddr_ba2, ddr_rasn, ddr_cke, ddr_wen, ddr_casn, ddr_odt, ddr_resetn, ddr_clk_ P, DDR _clk_n) of the memory chip MT41J64M16JT are connected to the memory logic unit B05 (BANK 34) in fig. 14; the data terminals (DDR_D16, DDR_D17, DDR_D18, DDR_D19, DDR_D20, DDR_D21, DDR_D22, DDR_D23, DDR_DQS2_ P, DDR _DQS2_ N, DDR _DQM; DDR_D24, DDR_D25, DDR_D26, DDR_D27, DDR_D28, DDR_D29, DDR_D30, DDR_D31, DDR_DQS3_ P, DDR _DQS3_ N, DDR _DQM3) of the memory chip MT41J64M16JT are correspondingly connected to the memory logic unit B05 (BANK 34) in FIG. 14.

Preferably, the memory chip MT41J64M16JT is powered by the fifth dc power supply +1.5v, and the memory logic unit B05 (BANK 34) is also powered by the fifth dc power supply +1.5v.

Further, as shown in fig. 16 and 17, fig. 16 is a schematic diagram of the clock logic unit B06 (BANK 216), and fig. 17 is a schematic diagram of the clock generator ICS844021I.

The core logic unit B01 in the scramble control module is electrically connected to the clock generator ICS844021I via the clock logic unit B06 (BANK 216). Specifically, the crystal oscillator input pin xtal_in and the crystal oscillator output pin xtal_out of the clock generator ICS844021I are electrically connected to an external crystal oscillator; the two output ends (QO, NQO) of the clock generator ICS844021I are respectively and electrically connected with one capacitor C241 and C240 and then connected with the clock logic unit (BANK 216), and the two power supply ends (VDDA, VDD) of the clock generator ICS844021I are correspondingly and electrically connected with the voltages of VDDA_SFPCLK, VDD_SFPCLK, VDDA_SFPCLK and VDD_SFPCLK which are 3.3V.

Further, as shown in fig. 18 and 19, fig. 18 is a schematic diagram of a debug logic unit B07 (BANK 0), and fig. 19 is a schematic diagram of a debug interface J5, wherein the first core to the fourth core of the debug interface J5 are electrically connected to the debug logic unit B07 (BANK 0); the core logic unit in the scrambling control module is electrically connected with the debugging interface J5 through the debugging logic unit B07 (BANK 0), and the scrambling control module can be debugged through the debugging interface J5.

Further, as shown IN fig. 20, the display information scrambling circuit further includes a power circuit, the power circuit includes a chip SY8113B, an input terminal IN of the chip SY8113B inputs a first dc power +12v, and an output terminal OUT outputs a second dc power +3.3v.

Specifically, the input end IN of the chip SY8113B is connected to the first dc power supply +12v through the power interface J6, the output end LX is electrically connected to the inductor L4 and then outputs the second dc power supply +3v, the feedback end FB of the chip SY8113B is electrically connected to the first feedback resistor R110 and then connected to the second dc power supply +3v, and is electrically connected to the second feedback resistor R114 and then grounded.

In this circuit, the voltage output from the output terminal OUT of the chip SY8113B can be adjusted by adjusting the first feedback resistor R110 and the second feedback resistor R114, for example, to generate a third dc power supply +5v, a fourth dc power supply +2.5v, and a fifth dc power supply +1.5v.

Further, as shown in fig. 21 to 23, the present utility model further provides a display information scrambling device 2, where the display information scrambling device 2 includes a housing 5 and a PCB circuit board 6 disposed inside the housing 5, and the PCB circuit board 6 is provided with the display information scrambling circuit, for example, a display information input interface J1, a video decoding chip IT68052, a scrambling control module, a video encoding chip IT6264, a display information output interface J2, a single chip microcomputer, a power interface J6, a program upgrading interface J4, and the like.

Preferably, the PCB circuit board 6 is further provided with a synchronization signal interface J7, and the synchronization signal interface J7 is used for connecting with a synchronization signal transmitter to transmit a synchronization signal to the synchronization glasses; of course, a bluetooth module, a wireless communication module, etc. may be disposed on the PCB 6 to transmit a synchronization signal to the synchronization glasses.

Preferably, the PCB 6 is also provided with an infrared receiving module which is electrically connected with the singlechip; the infrared remote controller can realize the switching of the display information scrambling device 2 between the normal mode and the scrambling mode through the infrared receiving module, and complete various operation functions.

Preferably, the housing 5 includes an upper housing 501 and a lower housing 502 which are detachably connected. The upper shell 501 comprises a top panel 7, a left panel 8 and a right panel 9 perpendicular to the top panel 7, and a plurality of heat dissipation holes 10 are formed in the left panel 8 and the right panel 9, and the heat dissipation holes 10 are beneficial to heat dissipation of the PCB 6; the lower case 502 includes a bottom panel 13, and a front panel 14 and a rear panel 15 perpendicular to the bottom panel 13, and a plurality of through holes 16 are provided in the front panel 14, and the through holes 16 are used to expose the display information input interface J1, the display information output interface J2, the power interface J6, the program upgrade interface J4, and the synchronization signal interface J7.

Further, the lower housing 502 further includes a left connecting plate 17 and a right connecting plate 18 perpendicular to the bottom panel 13, and the left connecting plate 17 and the right connecting plate 18 are concave in shape and are correspondingly and fixedly connected with the left panel 8 and the right panel 9 in a threaded connection manner; screw holes 19 are formed in the left connecting plate 17 and the right connecting plate 18, and connecting holes 20 through which screws pass are correspondingly formed in the left panel 8 and the right panel 9.

Preferably, the scrambling control switch SWDIO is located on the right panel 9 of the display information scrambling device 2.

Further, as shown in fig. 24, the synchronous glasses 3 are provided with a temperature sensor for sensing the body temperature, when the temperature sensor does not sense the body temperature close to the human body, the lenses of the synchronous glasses 3 are controlled to be always in a closed state, and in this way, photographing by the synchronous glasses 3, for example, photographing by placing the synchronous glasses 3 in front of the photographing lens, can be avoided. Further, the temperature sensor is arranged at the position GY1 at the inner side of the nose support of the synchronous glasses and is used for sensing the temperature of a human body near the nose; and a temperature sensor is provided at an inner side position GY2 of the rear end of the clip leg of the synchro glasses 3 for sensing the temperature of the human body near the ears. Further, after the synchronous glasses 3 sense at least the effective human body temperatures acquired by the temperature sensors at two different positions, the lenses of the synchronous glasses 3 are controlled to be in a normal working state, otherwise, the lenses of the synchronous glasses 3 are controlled to be always in a closed state.

Further, the synchronous glasses 3 receive a synchronous signal from the display information scrambling device 2, the synchronous signal is a wireless communication signal, and the synchronous control of the opening action of the lenses of the synchronous glasses 3 is adapted to the first picture display, including time synchronization, frequency adaptation and the like. Preferably, the wireless communication signal is a direct sequence spread spectrum signal or a frequency hopping signal which is encrypted and/or has anti-interference capability, so that the wireless communication signal can be ensured to effectively and reliably synchronously control the synchronous glasses 3, and the synchronous glasses 3 are prevented from being interfered and not working.

The utility model discloses a display information scrambling device, which comprises display information scrambling equipment, a display screen, a synchronous signal transmitter and synchronous glasses; the display information scrambling device is provided with a display information input interface and a display information output interface, wherein the display information input interface is used for inputting display information, and the display information output interface is used for outputting scrambled display information to the display screen; the display information scrambling device also transmits a synchronization signal to the synchronization glasses through a synchronization signal transmitter. The device realizes that the device can normally watch through synchronous glasses, and the shooting equipment obtains a scrambling picture when shooting a display screen, and can realize various scrambling effects in various modes, thereby being applicable to various application scenes.

The foregoing description is only illustrative of the present utility model and is not intended to limit the scope of the utility model, and all equivalent structural changes made by the present utility model and the accompanying drawings, or direct or indirect application in other related technical fields, are included in the scope of the present utility model.

Claims (9)

1. A display information scrambling device, characterized by: the system comprises display information scrambling equipment, a display screen, a synchronous signal transmitter and synchronous glasses; the display information scrambling device is provided with a display information input interface and a display information output interface, wherein the display information input interface is used for inputting display information, and the display information output interface is used for outputting scrambled display information to the display screen; the display information scrambling device also transmits a synchronizing signal to the synchronizing glasses through the synchronizing signal transmitter; the display information scrambling equipment comprises a shell and a PCB circuit board arranged in the shell, wherein the display information input interface and the display information output interface are both arranged on the PCB circuit board, and a video decoding chip IT68052, a scrambling control module and a video coding chip IT6264 are also arranged on the PCB circuit board; the display information input interface is electrically connected with the scrambling control module through the video decoding chip IT68052, and the scrambling control module is electrically connected with the display information output interface through the video encoding chip IT 6264.

2. The display information scrambling device of claim 1, wherein: the scrambling control module comprises a core logic unit, an input logic unit and an output logic unit, wherein the core logic unit is electrically connected with the video decoding chip IT68052 through the input logic unit, and is electrically connected with the video encoding chip IT6264 through the output logic unit.

3. The display information scrambling device of claim 2, wherein: the PCB is provided with a singlechip, and the singlechip is electrically connected with the video decoding chip IT68052, the video encoding chip IT6264 and the scrambling control module.

4. A display information scrambling apparatus as recited in claim 3, wherein: the PCB is provided with a scrambling control switch and an infrared receiving module, and the scrambling control switch and the infrared receiving module are electrically connected with the singlechip.

5. The display information scrambling apparatus of claim 4, wherein: the PCB circuit board is provided with a program upgrading circuit, and the program upgrading circuit comprises a program upgrading interface and an oscillator chip CP2102 electrically connected with the program upgrading interface.

6. The display information scrambling device of any of claims 1 to 5, wherein: the housing includes a detachably connected upper housing and lower housing.

7. The display information scrambling apparatus of claim 6, wherein: the upper shell comprises a top panel, and a left panel and a right panel which are perpendicular to the top panel, wherein a plurality of heat dissipation holes are formed in the left panel and the right panel.

8. The display information scrambling device of claim 7, wherein: the lower shell comprises a bottom panel, a front panel and a rear panel, wherein the front panel and the rear panel are perpendicular to the bottom panel, and a plurality of through holes are formed in the front panel.

9. The display information scrambling device of claim 8, wherein: the display information scrambling device has a synchronization signal interface for connecting the synchronization signal transmitter.