CN220067427U

CN220067427U - Modem system for satellite communication master station

Info

Publication number: CN220067427U
Application number: CN202321711490.7U
Authority: CN
Inventors: 沈方佩; 汤善东; 刘捷; 王喜
Original assignee: Nanjing Konway High Tech Co ltd
Current assignee: Nanjing Konway High Tech Co ltd
Priority date: 2023-07-03
Filing date: 2023-07-03
Publication date: 2023-11-21
Anticipated expiration: 2033-07-03

Abstract

The utility model discloses a modulation and demodulation system for a satellite communication master station, and relates to the technical field of satellite communication. The network management control unit and the channel control unit are independent units, the network port end of the network management control unit is respectively connected with the network port end of the channel control unit and the control network port end of the service unit through the switching unit, and the radio frequency end of the channel control unit is connected with the radio frequency end of the service unit. The utility model adopts a distributed architecture, and the network management control unit and the channel control unit are independent in the system, thereby realizing centralized control and management of the service modem unit, being convenient and fast to operate, and being a satellite modem system with low coupling, high multiplexing and easy expansion.

Description

Modem system for satellite communication master station

Technical Field

The utility model relates to the technical field of satellite communication, in particular to a modulation-demodulation system for a satellite communication master station.

Background

The existing satellite modem integrates a control unit and a communication unit into an integrated structure, has the conditions of repeated functions, redundant modules and the like under the condition of supporting network access communication of multiple devices, cannot realize centralized control of multiple devices by a single interface, and is complex in operation. In terms of performance, the conventional satellite modem cannot reasonably allocate satellite resources by a control unit, so that the communication efficiency of the system is greatly affected.

Disclosure of Invention

The utility model aims to: a modem system for a satellite communication master station is provided to solve the problem of the prior art.

The technical scheme is as follows: a modem system for a satellite communications master station, comprising:

the switching unit is used for realizing network connection and data transmission;

the network management control unit is connected with the exchange unit and used for issuing an instruction and returning a real-time running state;

the network port end is connected with the switching unit, and the switching unit receives the instruction issued by the network management control unit;

one end of the combining and separating unit is connected with the radio frequency end of the channel control unit and is used for combining or separating a plurality of radio frequency signals;

the network port end of the service modem unit is connected with the switching unit, the radio frequency end is connected with the combining and dividing unit, the switching unit is used for receiving the instruction issued by the channel control unit, and the channel control unit is used for controlling and distributing the satellite signals received and transmitted by the service modem unit.

According to one aspect of the utility model, the combining and dividing unit comprises a combiner and a divider, one end of the combiner is connected with the radio frequency end output port of the channel control unit, the other end of the combiner is connected with the radio frequency end output port of the service modem unit, one end of the divider is connected with the radio frequency end input port of the star channel control unit, and the other end of the divider is connected with the radio frequency end input port of the service modem unit.

According to one aspect of the utility model, the service modem unit comprises a plurality of service modem units, the radio frequency end output ports of the plurality of service modem units are connected with a plurality of ports of the combiner, and the radio frequency end input ports of the service modem units are connected with a plurality of ports of the splitter.

According to one aspect of the utility model, the splitter is further connected to a low noise frequency converter.

According to one aspect of the utility model, the combiner is further coupled to a power amplifier.

According to one aspect of the present utility model, the circuit of the network management control unit includes: the power management chip U1, the capacitor C2, the capacitor C3, the capacitor C4, the capacitor C5, the capacitor C6, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5 and the inductor L1, wherein one end of the resistor R3 is grounded, the other end is connected with the pin 7 of the power management chip U1, one end of the resistor R1 is grounded, the other end is connected with one end of the capacitor C4, the other end of the capacitor C4 is connected with the pin 6 of the power management chip U1, the pin 8 of the power management chip U1 is connected with the power supply VDD, the pin 9 of the power management chip U1 is grounded, one end of the capacitor C1 is grounded, the other end is connected with the pin 8 of the power management chip U1, one end of the capacitor C2 is grounded, the other end links to each other with power management chip U1's pin 8, power management chip U1's pin 1 links to each other with inductance L1 and electric capacity C3's one end simultaneously, electric capacity C3's the other end links to each other with power management chip U1's pin 2, inductance L1's the other end links to each other with resistance R4's one end and power VCC simultaneously, resistance R4's the other end links to each other with resistance R5's one end and power management chip U1's pin 5 simultaneously, resistance R5's the other end ground connection, power management chip U1's pin 3 links to each other with resistance R2's one end, resistance R2's the other end power VDD, power management chip U1's pin 4 ground connection, electric capacity C5 connects in parallel with electric capacity C6's one end with electric capacity C5, the other end ground connection VCC.

According to one aspect of the utility model, the circuitry of the channel control unit comprises: the socket CH8-J8, the socket CH8-J9, the socket J6, the socket J7, the socket J10, the double-circuit inverter U5, the double-circuit inverter U6, the resistor R30, the resistor R31, the resistor R32, the resistor R33, the resistor R34, the resistor R35, the capacitor C38 and the capacitor C39, wherein the pin 11 of the socket J6 is grounded, the pin 12 of the socket J6 is connected with one end of the resistor R31, the other end of the resistor R31 is connected with the pin 4 of the double-circuit inverter U5, the pin 5 of the double-circuit inverter U5 is connected with one end of the capacitor C38, the other end of the capacitor C38 is grounded, the pin 5 of the double-circuit inverter U5 is connected with the power VCC, the pin 10 of the socket J6 is grounded, the pin 9 of the socket J6 is connected with one end of the resistor R30, the other end of the resistor R30 is connected with the pin 6 of the double-circuit inverter U5, the pin 2 of the double-circuit inverter U5 is grounded, pin 13 and pin 14 of the socket J6 are grounded, pin 11 of the socket J7 is grounded, pin 12 of the socket J7 is connected with one end of resistor R33, the other end of resistor R33 is connected with pin 4 of double-circuit inverter U6, pin 5 of double-circuit inverter U6 is connected with one end of capacitor C39, the other end of capacitor C39 is grounded, pin 5 of double-circuit inverter U6 is grounded to power VCC, pin 10 of socket J7 is grounded, pin 9 of socket J7 is connected with one end of resistor R32, the other end of resistor R32 is connected with pin 6 of double-circuit inverter U6, pin 2 of double-circuit inverter U6 is grounded, pin 1 of double-circuit inverter U6 is connected with pin 4 of socket GH8-J8, pin 3 of double-circuit inverter U6 is connected with pin 3 of socket GH8-J8, pin 13 and pin 14 of socket J7 are grounded, pin 2 of socket GH8-J8 is connected to power, pin 1 of row socket GH8-J8 is grounded, port M1 and port M2 of row socket GH8-J8 are grounded, pin 11 of net socket J10 is grounded, pin 12 of net socket J10 is connected with one end of resistor R35, the other end of resistor R35 is connected with pin 3 of row socket GH8-J9, pin 10 of net socket J10 is grounded, pin 9 of net socket J10 is connected with one end of resistor R34, the other end of resistor R34 is connected with pin 4 of row socket GH8-J9, pin 13 and pin 14 of net socket J10 are grounded, pin 1 of row socket GH8-J9 is grounded, and port M1 and port M2 of row socket GH8-J9 are grounded.

According to one aspect of the present utility model, the circuit of the service modem unit includes: the control chip U2, the memory U3, the network port transformer U4, the socket GH6-J5, the resistor R6, the resistor R7, the resistor R8, the resistor R9, the resistor R10, the resistor R11, the resistor R12, the resistor R13, the resistor R14, the resistor R15, the resistor R16, the resistor R17, the resistor R18, the resistor R19, the resistor R20, the resistor R21, the resistor R22, the resistor R23, the resistor R24, the resistor R26, the resistor R27, the resistor R28, the resistor R29, the capacitor C7, the capacitor C8, the capacitor C9, the capacitor C10, the capacitor C11, the capacitor C12, the capacitor C13, the capacitor C14, the capacitor C15, the capacitor C16, the electrolytic capacitor C17, the electrolytic capacitor C18, the capacitor C19, the electrolytic capacitor C20, the capacitor C21, the electrolytic capacitor C22, the capacitor C23, the capacitor C24, the capacitor C25, the capacitor C26, the capacitor C27, the capacitor C30, the capacitor C31, the capacitor C32, the capacitor C33, the capacitor C34, the capacitor C35, the capacitor C36, the capacitor C37, the FB1, the diode FB1, wherein the pins 4, 8, 14, 15, 22, 37, 48, 53, 54, 55 and 63 of the control chip U2 are grounded, the pin 50 of the control chip U2 is connected to one end of a resistor R7, the other end of the resistor R7 is connected to a power supply VDD, the pin 57 of the control chip U2 is simultaneously connected to one end of a capacitor C7 and one end of a resistor R26, the other end of the capacitor C7 is simultaneously connected to one end of a resistor R27 and the pin 56 of the control chip U2, the other end of the resistor R26 is connected to the pin 2 of the socket GH6-J5, the other end of the resistor R27 is connected to the pin 3 of the socket GH6-J5, the pin 21 of the control chip U2 is connected to one end of a diode D1, the other end of the diode D1 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to a power supply VCC, the pin 45 of the control chip U2 is simultaneously connected to one end of the resistor R24 and one end of the capacitor C15, the other end of the resistor R24 is connected with the power VCC, the other end of the capacitor C15 is connected with the ground, the pin 58 of the control chip U2 is connected with one end of the resistor R10, the other end of the resistor R10 is connected with the ground, the pin 62 of the control chip U2 is connected with one end of the resistor R15 and the pin 3 of the memory U3 at the same time, the other end of the resistor R15 is connected with the pin 4 of the memory U3, the pin 38 of the control chip U2 is connected with one end of the resistor R19, the other end of the resistor R19 is connected with the pin 2 of the memory U3, the pin 39 of the control chip U2 is connected with the pin 1 of the memory U3, the pin 6 of the memory U3 is connected with one end of the resistor R16, the other end of the resistor R16 is connected with the power VCC, the other end of the capacitor C13 is connected with the ground, the pin 52 of the control chip U2 is connected with the variable resistor FB1, the electrolytic capacitor C22 and one end of the capacitor C23 at the same time, the other end of the variable resistor FB1 is simultaneously connected with one end of the electrolytic capacitor C17 and one end of the capacitor C16, the other ends of the electrolytic capacitor C17 and the capacitor C16 are grounded, the other ends of the electrolytic capacitor C22 and the capacitor C23 are grounded, the pin 51 of the control chip U2 is simultaneously connected with one end of the variable resistor FB2, one end of the electrolytic capacitor C18 and one end of the capacitor C19, the other ends of the variable resistor FB2 are simultaneously connected with one end of the electrolytic capacitor C20 and one end of the capacitor C21, the other ends of the electrolytic capacitor C20 and the capacitor C21 are grounded, the other ends of the electrolytic capacitor C18 and the capacitor C19 are grounded, the pin 16 and the pin 44 of the control chip U2 are simultaneously connected with one end of the capacitor C24 and one end of the capacitor C25, the other ends of the capacitor C24 and the capacitor C25 are grounded, the pin 6, the pin 59 and the pin 60 of the control chip U2 are simultaneously connected with one end of the capacitor C26 and one end of the capacitor C27, the other ends of the capacitor C26 and the capacitor C27 are grounded, and the other ends of the control chip U2 are grounded, pin 24, pin 36 and pin 49 are connected with one end of capacitor C30, capacitor C31, capacitor C32 and capacitor C33 at the same time, the other ends of capacitor C30, capacitor C31, capacitor C32 and capacitor C33 are grounded, pin 1, pin 11 and pin 64 of control chip U2 are connected with one end of capacitor C34, capacitor C35 and capacitor C36 at the same time, the other ends of capacitor C34, capacitor C35 and capacitor C36 are grounded, pin 18 of control chip U2 is connected with one end of resistor R21, pin 19 of control chip U2 is connected with one end of resistor R20, pin 7 of control chip U2 is grounded, pin 12 of control chip U2 is connected with pin 3 of network port transformer U4, pin 13 of control chip U2 is connected with pin 1 of network port transformer U4, pin 9 of control chip U2 is connected with pin 8 of network port transformer U4, pin 10 of control chip U2 is connected with pin 6 of network port transformer U4, the pin 3 of the control chip U2 is connected with one end of a resistor R8 and one end of a resistor R9 at the same time, the other end of the resistor R9 is connected with one end of an inductor C8 and one end of a crystal oscillator Y1 at the same time, the other end of the inductor C8 is grounded, the pin 2 of the control chip U2 is connected with the other end of the resistor R8, the pin 3 of the crystal oscillator Y1 and one end of the inductor C9 at the same time, the other end of the inductor C9 is grounded, the pin 2 and the pin 7 of a crystal oscillator Y1 are grounded, the pin 2 and the pin 7 of a network port transformer U4 are connected with one end of a resistor R12 and one end of a capacitor C11 at the same time, the other end of the capacitor C11 is grounded, the other end of the resistor R14 is connected with one end of a resistor R13 and one end of a capacitor C10 at the same time, the other end of the capacitor C10 is grounded, the other end of the resistor R13 is connected with the pin 3 of the network port transformer U4, the pin 6 of the network port transformer U4 is connected with one end of a resistor R22, the other end of the resistor R22 is connected with one end of the resistor R23 and one end of the capacitor C14 at the same time, the other end of the capacitor C14 is grounded, the other end of the resistor R23 is connected with the pin 8 of the network port transformer U4, the pin 15 of the network port transformer U4 is connected with one end of the resistor R17, the other end of the resistor R17 is connected with one end of the capacitor C12, the other end of the capacitor C12 is grounded, the pin 10 of the network port transformer U4 is connected with one end of the resistor R18, the other end of the resistor R18 is connected with one end of the capacitor C12, the pin 1 of the socket GH6-J5 is connected with one end of the capacitor C37 at the same time and the power supply VDD, the other end of the capacitor C37 is grounded, the pin 4 of the socket GH6-J5 is connected with one end of the resistor R28, the pin 5 of the socket GH6-J5 is grounded, the pin 6 of the socket GH6-J5 is grounded, and the port M1 and the port M2 of the socket GH6-J5 are grounded.

The beneficial effects are that: the utility model realizes the centralized control and management of the service modem unit through the design of the modem system of the satellite communication main station, so that the operation is more convenient, the expansibility and the economy of the system are improved by adopting the design of the distributed architecture, and the reliability and the stability of the system are improved by the redundancy backup of the service modem unit.

Drawings

Fig. 1 is a schematic diagram of the minimum system composition of the present utility model.

Fig. 2 is a schematic diagram of a multi-path traffic pattern connection structure according to the present utility model.

Fig. 3 is a system topology of the present utility model.

Fig. 4 is a circuit diagram of the network management control unit.

Fig. 5 is a circuit diagram of a channel control unit.

Fig. 6 is an enlarged view of a portion a in fig. 5.

Fig. 7 is an enlarged view of a portion B in fig. 5.

Fig. 8 is an enlarged view of a portion C in fig. 5.

Fig. 9 is an enlarged view of a portion D in fig. 5.

Fig. 10 is an enlarged view of a portion E in fig. 5.

Fig. 11 is an enlarged view of the portion F in fig. 5.

Fig. 12 is an enlarged view of a portion G in fig. 5.

Fig. 13 is an enlarged view of the H portion in fig. 5.

Fig. 14 is a circuit diagram of a service modem unit.

Fig. 15 is an enlarged view of a portion a in fig. 14.

Fig. 16 is an enlarged view of a portion B in fig. 14.

Fig. 17 is an enlarged view of a portion C in fig. 14.

Fig. 18 is an enlarged view of a portion D in fig. 14.

Detailed Description

At present, the existing satellite modem adopts an integrated architecture of a control unit and a communication unit, has the conditions of repeated functions and redundant modules under the condition of supporting network access communication of multiple devices, can not realize centralized control of multiple devices by a single interface, and is relatively complex in operation. In terms of performance, reasonable distribution of satellite resources cannot be realized, and communication efficiency of the system is greatly affected.

Therefore, the utility model comprehensively considers cost, performance and reliability, and designs a satellite modem system with low coupling, high multiplexing and easy expansion.

The utility model uses three parts of network management control unit, channel control unit and service modulation demodulation unit to replace the existing unit integrated system, and specifically comprises:

The combining and separating unit comprises a combiner and a splitter, one end of the combiner is connected with the radio frequency end output port of the channel control unit, the other end of the combiner is connected with the radio frequency end output port of the service modem unit, one end of the splitter is connected with the radio frequency end input port of the star channel control unit, and the other end of the splitter is connected with the radio frequency end input port of the service modem unit.

Further embodiment fig. 1 is a schematic diagram of the minimum system according to the present utility model, wherein the rf ports are connected by rf lines and the ports are connected by net lines. The radio frequency part of the channel control unit is connected with the satellite service modem unit through the combining and branching unit to realize the control and distribution of satellite signals transmitted and received by the service modem unit by the channel control unit, and the network management control unit is connected with the channel control unit and the satellite service modem unit through the switch to realize the issuing of control instructions among the units of the system, the return of real-time running states and the like.

In a further embodiment, the service modem unit includes a plurality of service modem units, the radio frequency end output ports of the plurality of service modem units are connected with a plurality of ports of the combiner, and the radio frequency end input ports of the service modem units are connected with a plurality of ports of the splitter.

As shown in fig. 2, compared with the minimum system composition, the multi-channel service mode connection system can change the number of the access service modem units according to actual needs, the multi-channel service modem units are connected to the channel control unit through the combiner-divider to realize system capacity expansion, all units in the system realize centralized control, and each device in the system is subjected to operation parameter configuration and operation state monitoring through a user terminal interface.

In a further embodiment the splitter is connected to a low noise frequency converter and the combiner is connected to a power amplifier.

Further embodiment as shown in fig. 3, the working mode of the present utility model is as follows: the user accesses the network management control unit through the network cable, and issues a control instruction to the channel control unit at the interface of the user terminal. And the channel control unit responds to the instruction of the network management control unit to carry out receiving and transmitting configuration on the service unit, wherein the receiving and transmitting configuration comprises a modulation mode, a coding mode, a working frequency, an IP address, a feed clock of the LNB, the feed clock of the BUC, and the like, so that satellite network service is provided for equipment needing to access the network. The user can also check the running state of each unit in real time through the terminal interface, such as the current working mode, the real-time signal receiving and transmitting rate, the signal frequency point sending and receiving, and the like. The service modem unit responds to the instruction of the channel control unit and provides the designated satellite network service for the equipment.

The system mainly comprises a network management control unit, a channel control unit and a service modulation and demodulation unit, wherein the three parts are connected with a switch through a combining and branching unit to carry out modulation and demodulation on receiving and transmitting satellite signals, so that multiple devices can be simultaneously accessed into a satellite network to access the network.

In a further embodiment the service modem unit supports redundancy backup. The system adopts a distributed architecture, the network management control unit and the channel control unit are independent in the system, a user can select a corresponding service modem unit to access according to the number of devices actually accessed to satellite network communication, when expansion is needed, only the service modem unit is needed to be added, the network management control unit and the channel control unit are not needed to be newly added, the expansibility and the economy of the system are improved, the service modem unit supports redundancy backup, and the reliability and the stability of the system can be effectively improved.

In a further embodiment, as shown in fig. 4, the circuit of the network management control unit includes: the power management chip U1, the capacitor C2, the capacitor C3, the capacitor C4, the capacitor C5, the capacitor C6, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5 and the inductor L1, wherein one end of the resistor R3 is grounded, the other end is connected with the pin 7 of the power management chip U1, one end of the resistor R1 is grounded, the other end is connected with one end of the capacitor C4, the other end of the capacitor C4 is connected with the pin 6 of the power management chip U1, the pin 8 of the power management chip U1 is connected with the power supply VDD, the pin 9 of the power management chip U1 is grounded, one end of the capacitor C1 is grounded, the other end is connected with the pin 8 of the power management chip U1, one end of the capacitor C2 is grounded, the other end links to each other with power management chip U1's pin 8, power management chip U1's pin 1 links to each other with inductance L1 and electric capacity C3's one end simultaneously, electric capacity C3's the other end links to each other with power management chip U1's pin 2, inductance L1's the other end links to each other with resistance R4's one end and power VCC simultaneously, resistance R4's the other end links to each other with resistance R5's one end and power management chip U1's pin 5 simultaneously, resistance R5's the other end ground connection, power management chip U1's pin 3 links to each other with resistance R2's one end, resistance R2's the other end power VDD, power management chip U1's pin 4 ground connection, electric capacity C5 connects in parallel with electric capacity C6's one end with electric capacity C5, the other end ground connection VCC.

The circuitry of the channel control unit is shown in fig. 5-13 and includes: the socket CH8-J8, the socket CH8-J9, the socket J6, the socket J7, the socket J10, the double-circuit inverter U5, the double-circuit inverter U6, the resistor R30, the resistor R31, the resistor R32, the resistor R33, the resistor R34, the resistor R35, the capacitor C38 and the capacitor C39, wherein the pin 11 of the socket J6 is grounded, the pin 12 of the socket J6 is connected with one end of the resistor R31, the other end of the resistor R31 is connected with the pin 4 of the double-circuit inverter U5, the pin 5 of the double-circuit inverter U5 is connected with one end of the capacitor C38, the other end of the capacitor C38 is grounded, the pin 5 of the double-circuit inverter U5 is connected with the power VCC, the pin 10 of the socket J6 is grounded, the pin 9 of the socket J6 is connected with one end of the resistor R30, the other end of the resistor R30 is connected with the pin 6 of the double-circuit inverter U5, the pin 2 of the double-circuit inverter U5 is grounded, pin 13 and pin 14 of the socket J6 are grounded, pin 11 of the socket J7 is grounded, pin 12 of the socket J7 is connected with one end of resistor R33, the other end of resistor R33 is connected with pin 4 of double-circuit inverter U6, pin 5 of double-circuit inverter U6 is connected with one end of capacitor C39, the other end of capacitor C39 is grounded, pin 5 of double-circuit inverter U6 is grounded to power VCC, pin 10 of socket J7 is grounded, pin 9 of socket J7 is connected with one end of resistor R32, the other end of resistor R32 is connected with pin 6 of double-circuit inverter U6, pin 2 of double-circuit inverter U6 is grounded, pin 1 of double-circuit inverter U6 is connected with pin 4 of socket GH8-J8, pin 3 of double-circuit inverter U6 is connected with pin 3 of socket GH8-J8, pin 13 and pin 14 of socket J7 are grounded, pin 2 of socket GH8-J8 is connected to power, pin 1 of row socket GH8-J8 is grounded, port M1 and port M2 of row socket GH8-J8 are grounded, pin 11 of net socket J10 is grounded, pin 12 of net socket J10 is connected with one end of resistor R35, the other end of resistor R35 is connected with pin 3 of row socket GH8-J9, pin 10 of net socket J10 is grounded, pin 9 of net socket J10 is connected with one end of resistor R34, the other end of resistor R34 is connected with pin 4 of row socket GH8-J9, pin 13 and pin 14 of net socket J10 are grounded, pin 1 of row socket GH8-J9 is grounded, and port M1 and port M2 of row socket GH8-J9 are grounded.

The circuits of the service modem unit are shown in fig. 14-18, and include: the control chip U2, the memory U3, the network port transformer U4, the socket GH6-J5, the resistor R6, the resistor R7, the resistor R8, the resistor R9, the resistor R10, the resistor R11, the resistor R12, the resistor R13, the resistor R14, the resistor R15, the resistor R16, the resistor R17, the resistor R18, the resistor R19, the resistor R20, the resistor R21, the resistor R22, the resistor R23, the resistor R24, the resistor R26, the resistor R27, the resistor R28, the resistor R29, the capacitor C7, the capacitor C8, the capacitor C9, the capacitor C10, the capacitor C11, the capacitor C12, the capacitor C13, the capacitor C14, the capacitor C15, the capacitor C16, the electrolytic capacitor C17, the electrolytic capacitor C18, the capacitor C19, the electrolytic capacitor C20, the capacitor C21, the electrolytic capacitor C22, the capacitor C23, the capacitor C24, the capacitor C25, the capacitor C26, the capacitor C27, the capacitor C30, the capacitor C31, the capacitor C32, the capacitor C33, the capacitor C34, the capacitor C35, the capacitor C36, the capacitor C37, the FB1, the diode FB1, wherein the pins 4, 8, 14, 15, 22, 37, 48, 53, 54, 55 and 63 of the control chip U2 are grounded, the pin 50 of the control chip U2 is connected to one end of a resistor R7, the other end of the resistor R7 is connected to a power supply VDD, the pin 57 of the control chip U2 is simultaneously connected to one end of a capacitor C7 and one end of a resistor R26, the other end of the capacitor C7 is simultaneously connected to one end of a resistor R27 and the pin 56 of the control chip U2, the other end of the resistor R26 is connected to the pin 2 of the socket GH6-J5, the other end of the resistor R27 is connected to the pin 3 of the socket GH6-J5, the pin 21 of the control chip U2 is connected to one end of a diode D1, the other end of the diode D1 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to a power supply VCC, the pin 45 of the control chip U2 is simultaneously connected to one end of the resistor R24 and one end of the capacitor C15, the other end of the resistor R24 is connected with the power VCC, the other end of the capacitor C15 is connected with the ground, the pin 58 of the control chip U2 is connected with one end of the resistor R10, the other end of the resistor R10 is connected with the ground, the pin 62 of the control chip U2 is connected with one end of the resistor R15 and the pin 3 of the memory U3 at the same time, the other end of the resistor R15 is connected with the pin 4 of the memory U3, the pin 38 of the control chip U2 is connected with one end of the resistor R19, the other end of the resistor R19 is connected with the pin 2 of the memory U3, the pin 39 of the control chip U2 is connected with the pin 1 of the memory U3, the pin 6 of the memory U3 is connected with one end of the resistor R16, the other end of the resistor R16 is connected with the power VCC, the other end of the capacitor C13 is connected with the ground, the pin 52 of the control chip U2 is connected with the variable resistor FB1, the electrolytic capacitor C22 and one end of the capacitor C23 at the same time, the other end of the variable resistor FB1 is simultaneously connected with one end of the electrolytic capacitor C17 and one end of the capacitor C16, the other ends of the electrolytic capacitor C17 and the capacitor C16 are grounded, the other ends of the electrolytic capacitor C22 and the capacitor C23 are grounded, the pin 51 of the control chip U2 is simultaneously connected with one end of the variable resistor FB2, one end of the electrolytic capacitor C18 and one end of the capacitor C19, the other ends of the variable resistor FB2 are simultaneously connected with one end of the electrolytic capacitor C20 and one end of the capacitor C21, the other ends of the electrolytic capacitor C20 and the capacitor C21 are grounded, the other ends of the electrolytic capacitor C18 and the capacitor C19 are grounded, the pin 16 and the pin 44 of the control chip U2 are simultaneously connected with one end of the capacitor C24 and one end of the capacitor C25, the other ends of the capacitor C24 and the capacitor C25 are grounded, the pin 6, the pin 59 and the pin 60 of the control chip U2 are simultaneously connected with one end of the capacitor C26 and one end of the capacitor C27, the other ends of the capacitor C26 and the capacitor C27 are grounded, and the other ends of the control chip U2 are grounded, pin 24, pin 36 and pin 49 are connected with one end of capacitor C30, capacitor C31, capacitor C32 and capacitor C33 at the same time, the other ends of capacitor C30, capacitor C31, capacitor C32 and capacitor C33 are grounded, pin 1, pin 11 and pin 64 of control chip U2 are connected with one end of capacitor C34, capacitor C35 and capacitor C36 at the same time, the other ends of capacitor C34, capacitor C35 and capacitor C36 are grounded, pin 18 of control chip U2 is connected with one end of resistor R21, pin 19 of control chip U2 is connected with one end of resistor R20, pin 7 of control chip U2 is grounded, pin 12 of control chip U2 is connected with pin 3 of network port transformer U4, pin 13 of control chip U2 is connected with pin 1 of network port transformer U4, pin 9 of control chip U2 is connected with pin 8 of network port transformer U4, pin 10 of control chip U2 is connected with pin 6 of network port transformer U4, the pin 3 of the control chip U2 is connected with one end of a resistor R8 and one end of a resistor R9 at the same time, the other end of the resistor R9 is connected with one end of an inductor C8 and one end of a crystal oscillator Y1 at the same time, the other end of the inductor C8 is grounded, the pin 2 of the control chip U2 is connected with the other end of the resistor R8, the pin 3 of the crystal oscillator Y1 and one end of the inductor C9 at the same time, the other end of the inductor C9 is grounded, the pin 2 and the pin 7 of a crystal oscillator Y1 are grounded, the pin 2 and the pin 7 of a network port transformer U4 are connected with one end of a resistor R12 and one end of a capacitor C11 at the same time, the other end of the capacitor C11 is grounded, the other end of the resistor R14 is connected with one end of a resistor R13 and one end of a capacitor C10 at the same time, the other end of the capacitor C10 is grounded, the other end of the resistor R13 is connected with the pin 3 of the network port transformer U4, the pin 6 of the network port transformer U4 is connected with one end of a resistor R22, the other end of the resistor R22 is connected with one end of the resistor R23 and one end of the capacitor C14 at the same time, the other end of the capacitor C14 is grounded, the other end of the resistor R23 is connected with the pin 8 of the network port transformer U4, the pin 15 of the network port transformer U4 is connected with one end of the resistor R17, the other end of the resistor R17 is connected with one end of the capacitor C12, the other end of the capacitor C12 is grounded, the pin 10 of the network port transformer U4 is connected with one end of the resistor R18, the other end of the resistor R18 is connected with one end of the capacitor C12, the pin 1 of the socket GH6-J5 is connected with one end of the capacitor C37 at the same time and the power supply VDD, the other end of the capacitor C37 is grounded, the pin 4 of the socket GH6-J5 is connected with one end of the resistor R28, the pin 5 of the socket GH6-J5 is grounded, the pin 6 of the socket GH6-J5 is grounded, and the port M1 and the port M2 of the socket GH6-J5 are grounded.

Although the utility model has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the utility model. Accordingly, the specification and drawings are merely exemplary illustrations of the present utility model as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the utility model. It will be apparent to those skilled in the art that various modifications and variations can be made to the present utility model without departing from the scope of the utility model. Thus, it is intended that the present utility model also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.

The foregoing is only a preferred embodiment of the utility model, it being noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the present utility model, and such modifications and adaptations are intended to be comprehended within the scope of the utility model.

Claims

1. A modem system for a satellite communications master station, comprising:

2. The modem system for a satellite communication master station according to claim 1, wherein the combining and dividing unit comprises a combiner and a splitter, one end of the combiner is connected to the radio frequency end output port of the channel control unit, the other end is connected to the radio frequency end output port of the service modem unit, one end of the splitter is connected to the radio frequency end input port of the satellite channel control unit, and the other end is connected to the radio frequency end input port of the service modem unit.

3. The modem system for a satellite communication master station according to claim 2, wherein the service modem unit comprises a plurality of service modem units, the radio frequency end output ports of the plurality of service modem units are connected with a plurality of ports of the combiner, and the radio frequency end input ports of the service modem units are connected with a plurality of ports of the splitter.

4. A modem system for a satellite communications master station according to claim 3, wherein the splitter is further connected to a low noise frequency converter.

5. A modem system for a satellite communications master station as claimed in claim 3, wherein the combiner is further coupled to a power amplifier.

6. The modem system for a satellite communication master station according to claim 1, wherein the circuit of the network management control unit comprises: the power management chip U1, the capacitor C2, the capacitor C3, the capacitor C4, the capacitor C5, the capacitor C6, the resistor R1, the resistor R2, the resistor R3, the resistor R4, the resistor R5 and the inductor L1, wherein one end of the resistor R3 is grounded, the other end is connected with the pin 7 of the power management chip U1, one end of the resistor R1 is grounded, the other end is connected with one end of the capacitor C4, the other end of the capacitor C4 is connected with the pin 6 of the power management chip U1, the pin 8 of the power management chip U1 is connected with the power supply VDD, the pin 9 of the power management chip U1 is grounded, one end of the capacitor C1 is grounded, the other end is connected with the pin 8 of the power management chip U1, one end of the capacitor C2 is grounded, the other end links to each other with power management chip U1's pin 8, power management chip U1's pin 1 links to each other with inductance L1 and electric capacity C3's one end simultaneously, electric capacity C3's the other end links to each other with power management chip U1's pin 2, inductance L1's the other end links to each other with resistance R4's one end and power VCC simultaneously, resistance R4's the other end links to each other with resistance R5's one end and power management chip U1's pin 5 simultaneously, resistance R5's the other end ground connection, power management chip U1's pin 3 links to each other with resistance R2's one end, resistance R2's the other end power VDD, power management chip U1's pin 4 ground connection, electric capacity C5 connects in parallel with electric capacity C6's one end with electric capacity C5, the other end ground connection VCC.

7. The modem system for a satellite communication master station according to claim 1, wherein the circuit of the channel control unit comprises: the socket CH8-J8, the socket CH8-J9, the socket J6, the socket J7, the socket J10, the double-circuit inverter U5, the double-circuit inverter U6, the resistor R30, the resistor R31, the resistor R32, the resistor R33, the resistor R34, the resistor R35, the capacitor C38 and the capacitor C39, wherein the pin 11 of the socket J6 is grounded, the pin 12 of the socket J6 is connected with one end of the resistor R31, the other end of the resistor R31 is connected with the pin 4 of the double-circuit inverter U5, the pin 5 of the double-circuit inverter U5 is connected with one end of the capacitor C38, the other end of the capacitor C38 is grounded, the pin 5 of the double-circuit inverter U5 is connected with the power VCC, the pin 10 of the socket J6 is grounded, the pin 9 of the socket J6 is connected with one end of the resistor R30, the other end of the resistor R30 is connected with the pin 6 of the double-circuit inverter U5, the pin 2 of the double-circuit inverter U5 is grounded, pin 13 and pin 14 of the socket J6 are grounded, pin 11 of the socket J7 is grounded, pin 12 of the socket J7 is connected with one end of resistor R33, the other end of resistor R33 is connected with pin 4 of double-circuit inverter U6, pin 5 of double-circuit inverter U6 is connected with one end of capacitor C39, the other end of capacitor C39 is grounded, pin 5 of double-circuit inverter U6 is grounded to power VCC, pin 10 of socket J7 is grounded, pin 9 of socket J7 is connected with one end of resistor R32, the other end of resistor R32 is connected with pin 6 of double-circuit inverter U6, pin 2 of double-circuit inverter U6 is grounded, pin 1 of double-circuit inverter U6 is connected with pin 4 of socket GH8-J8, pin 3 of double-circuit inverter U6 is connected with pin 3 of socket GH8-J8, pin 13 and pin 14 of socket J7 are grounded, pin 2 of socket GH8-J8 is connected to power, pin 1 of row socket GH8-J8 is grounded, port M1 and port M2 of row socket GH8-J8 are grounded, pin 11 of net socket J10 is grounded, pin 12 of net socket J10 is connected with one end of resistor R35, the other end of resistor R35 is connected with pin 3 of row socket GH8-J9, pin 10 of net socket J10 is grounded, pin 9 of net socket J10 is connected with one end of resistor R34, the other end of resistor R34 is connected with pin 4 of row socket GH8-J9, pin 13 and pin 14 of net socket J10 are grounded, pin 1 of row socket GH8-J9 is grounded, and port M1 and port M2 of row socket GH8-J9 are grounded.

8. The modem system for a satellite communication master station according to claim 1, wherein the circuit of the service modem unit comprises: the control chip U2, the memory U3, the network port transformer U4, the socket GH6-J5, the resistor R6, the resistor R7, the resistor R8, the resistor R9, the resistor R10, the resistor R11, the resistor R12, the resistor R13, the resistor R14, the resistor R15, the resistor R16, the resistor R17, the resistor R18, the resistor R19, the resistor R20, the resistor R21, the resistor R22, the resistor R23, the resistor R24, the resistor R26, the resistor R27, the resistor R28, the resistor R29, the capacitor C7, the capacitor C8, the capacitor C9, the capacitor C10, the capacitor C11, the capacitor C12, the capacitor C13, the capacitor C14, the capacitor C15, the capacitor C16, the electrolytic capacitor C17, the electrolytic capacitor C18, the capacitor C19, the electrolytic capacitor C20, the capacitor C21, the electrolytic capacitor C22, the capacitor C23, the capacitor C24, the capacitor C25, the capacitor C26, the capacitor C27, the capacitor C30, the capacitor C31, the capacitor C32, the capacitor C33, the capacitor C34, the capacitor C35, the capacitor C36, the capacitor C37, the FB1, the diode FB1, wherein the pins 4, 8, 14, 15, 22, 37, 48, 53, 54, 55 and 63 of the control chip U2 are grounded, the pin 50 of the control chip U2 is connected to one end of a resistor R7, the other end of the resistor R7 is connected to a power supply VDD, the pin 57 of the control chip U2 is simultaneously connected to one end of a capacitor C7 and one end of a resistor R26, the other end of the capacitor C7 is simultaneously connected to one end of a resistor R27 and the pin 56 of the control chip U2, the other end of the resistor R26 is connected to the pin 2 of the socket GH6-J5, the other end of the resistor R27 is connected to the pin 3 of the socket GH6-J5, the pin 21 of the control chip U2 is connected to one end of a diode D1, the other end of the diode D1 is connected to one end of the resistor R6, the other end of the resistor R6 is connected to a power supply VCC, the pin 45 of the control chip U2 is simultaneously connected to one end of the resistor R24 and one end of the capacitor C15, the other end of the resistor R24 is connected with the power VCC, the other end of the capacitor C15 is connected with the ground, the pin 58 of the control chip U2 is connected with one end of the resistor R10, the other end of the resistor R10 is connected with the ground, the pin 62 of the control chip U2 is connected with one end of the resistor R15 and the pin 3 of the memory U3 at the same time, the other end of the resistor R15 is connected with the pin 4 of the memory U3, the pin 38 of the control chip U2 is connected with one end of the resistor R19, the other end of the resistor R19 is connected with the pin 2 of the memory U3, the pin 39 of the control chip U2 is connected with the pin 1 of the memory U3, the pin 6 of the memory U3 is connected with one end of the resistor R16, the other end of the resistor R16 is connected with the power VCC, the other end of the capacitor C13 is connected with the ground, the pin 52 of the control chip U2 is connected with the variable resistor FB1, the electrolytic capacitor C22 and one end of the capacitor C23 at the same time, the other end of the variable resistor FB1 is simultaneously connected with one end of the electrolytic capacitor C17 and one end of the capacitor C16, the other ends of the electrolytic capacitor C17 and the capacitor C16 are grounded, the other ends of the electrolytic capacitor C22 and the capacitor C23 are grounded, the pin 51 of the control chip U2 is simultaneously connected with one end of the variable resistor FB2, one end of the electrolytic capacitor C18 and one end of the capacitor C19, the other ends of the variable resistor FB2 are simultaneously connected with one end of the electrolytic capacitor C20 and one end of the capacitor C21, the other ends of the electrolytic capacitor C20 and the capacitor C21 are grounded, the other ends of the electrolytic capacitor C18 and the capacitor C19 are grounded, the pin 16 and the pin 44 of the control chip U2 are simultaneously connected with one end of the capacitor C24 and one end of the capacitor C25, the other ends of the capacitor C24 and the capacitor C25 are grounded, the pin 6, the pin 59 and the pin 60 of the control chip U2 are simultaneously connected with one end of the capacitor C26 and one end of the capacitor C27, the other ends of the capacitor C26 and the capacitor C27 are grounded, and the other ends of the control chip U2 are grounded, pin 24, pin 36 and pin 49 are connected with one end of capacitor C30, capacitor C31, capacitor C32 and capacitor C33 at the same time, the other ends of capacitor C30, capacitor C31, capacitor C32 and capacitor C33 are grounded, pin 1, pin 11 and pin 64 of control chip U2 are connected with one end of capacitor C34, capacitor C35 and capacitor C36 at the same time, the other ends of capacitor C34, capacitor C35 and capacitor C36 are grounded, pin 18 of control chip U2 is connected with one end of resistor R21, pin 19 of control chip U2 is connected with one end of resistor R20, pin 7 of control chip U2 is grounded, pin 12 of control chip U2 is connected with pin 3 of network port transformer U4, pin 13 of control chip U2 is connected with pin 1 of network port transformer U4, pin 9 of control chip U2 is connected with pin 8 of network port transformer U4, pin 10 of control chip U2 is connected with pin 6 of network port transformer U4, the pin 3 of the control chip U2 is connected with one end of a resistor R8 and one end of a resistor R9 at the same time, the other end of the resistor R9 is connected with one end of an inductor C8 and one end of a crystal oscillator Y1 at the same time, the other end of the inductor C8 is grounded, the pin 2 of the control chip U2 is connected with the other end of the resistor R8, the pin 3 of the crystal oscillator Y1 and one end of the inductor C9 at the same time, the other end of the inductor C9 is grounded, the pin 2 and the pin 7 of a crystal oscillator Y1 are grounded, the pin 2 and the pin 7 of a network port transformer U4 are connected with one end of a resistor R12 and one end of a capacitor C11 at the same time, the other end of the capacitor C11 is grounded, the other end of the resistor R14 is connected with one end of a resistor R13 and one end of a capacitor C10 at the same time, the other end of the capacitor C10 is grounded, the other end of the resistor R13 is connected with the pin 3 of the network port transformer U4, the pin 6 of the network port transformer U4 is connected with one end of a resistor R22, the other end of the resistor R22 is connected with one end of the resistor R23 and one end of the capacitor C14 at the same time, the other end of the capacitor C14 is grounded, the other end of the resistor R23 is connected with the pin 8 of the network port transformer U4, the pin 15 of the network port transformer U4 is connected with one end of the resistor R17, the other end of the resistor R17 is connected with one end of the capacitor C12, the other end of the capacitor C12 is grounded, the pin 10 of the network port transformer U4 is connected with one end of the resistor R18, the other end of the resistor R18 is connected with one end of the capacitor C12, the pin 1 of the socket GH6-J5 is connected with one end of the capacitor C37 at the same time and the power supply VDD, the other end of the capacitor C37 is grounded, the pin 4 of the socket GH6-J5 is connected with one end of the resistor R28, the pin 5 of the socket GH6-J5 is grounded, the pin 6 of the socket GH6-J5 is grounded, and the port M1 and the port M2 of the socket GH6-J5 are grounded.