CN220041869U

CN220041869U - Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Info

Publication number: CN220041869U
Application number: CN202223309144.4U
Authority: CN
Inventors: 吴家伟; 童宇诚
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2022-12-09
Filing date: 2022-12-09
Publication date: 2023-11-17
Anticipated expiration: 2032-12-09

Abstract

The utility model discloses a semiconductor device, which comprises a first stacked channel layer, wherein the first stacked channel layer comprises a first surface and a second surface which are opposite. A first gate structure is located on the first face of the first stacked channel layer. And the first gate dielectric layer is positioned between the first gate structure and the first stacking channel layer. The second stacking channel layer is positioned between the first grid dielectric layer and the first stacking channel layer, wherein the concentration of a metal component in the second stacking channel layer is larger than that of the metal component in the first stacking channel layer, so that stable threshold voltage and improved carrier mobility can be obtained at the same time, and the element performance is further improved.

Description

Semiconductor device with a semiconductor layer having a plurality of semiconductor layers

Technical Field

The present utility model relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including an oxide semiconductor channel layer.

Background

A Thin Film Transistor (TFT) is a field effect transistor having a semiconductor layer deposited on a substrate as an active layer (channel layer), and can be conveniently fabricated on various substrates, such as a wafer, a glass substrate, a ceramic substrate, or a high molecular polymer such as Polyimide (PI), polycarbonate (PC), or polyethylene terephthalate (PET) substrate, and can also be conveniently integrated with a back end of line (BEOL) of an integrated circuit, providing higher flexibility of circuit design and reducing a chip area. For example, it can be used to fabricate embedded (embedded) memory. The oxide semiconductor (oxide semiconductor) is particularly suitable as a material for an active layer (channel layer) of a thin film transistor because of its advantages such as high field effect carrier mobility (field effect mobility), low deposition temperature, and high film uniformity.

Disclosure of Invention

The present utility model is directed to a semiconductor device including an oxide semiconductor channel layer formed by a two-stage atomic layer deposition cycle so that it can be divided into two parts of different composition concentrations in a thickness direction, and a stable threshold voltage and an improved carrier mobility can be simultaneously obtained, further improving device performance, and a method of manufacturing the same.

The manufacturing method of the semiconductor device provided by the embodiment of the utility model comprises the following steps. Firstly, providing a substrate, then performing a first atomic layer deposition cycle for M times to form a first stacked channel layer on the substrate, and then performing a second atomic layer deposition cycle for N times to form a second stacked channel layer on the first stacked channel layer, wherein M and N are positive integers which are respectively greater than or equal to 1, and the concentration of a metal component in the second stacked channel layer is greater than the concentration of the metal component in the first stacked channel layer. Then, a gate dielectric layer is formed on the second stacked channel layer, and then a gate structure is formed on the gate dielectric layer.

According to another embodiment of the present utility model, a method for manufacturing a semiconductor device includes the following steps. A substrate is provided first, a bottom gate structure is formed on the substrate, and then a bottom gate dielectric layer is formed on the bottom gate structure. Then, a first atomic layer deposition cycle is performed for N times to form a first stacked channel layer on the gate dielectric layer, and then a second atomic layer deposition cycle is performed for M times to form a second stacked channel layer on the first stacked channel layer, wherein M and N are positive integers, and the concentration of a metal component in the first stacked channel layer is greater than the concentration of the metal component in the second stacked channel layer.

According to still another embodiment of the present utility model, a semiconductor device is provided that includes a first stacked channel layer, a first gate structure, a first gate dielectric layer, and a second stacked channel layer. The first stacked via layer includes opposing first and second faces. The first gate structure is located on the first face of the first stacked channel layer. The first gate dielectric layer is located between the first gate structure and the first stacked channel layer. The second stacked channel layer is located between the first gate dielectric layer and the first stacked channel layer. The concentration of a metal component in the second stacked channel layer is greater than the concentration of the metal component in the first stacked channel layer.

Drawings

The accompanying drawings are included to provide a further understanding of embodiments of the utility model and are incorporated in and constitute a part of this specification. These drawings and description serve to illustrate principles of some embodiments. It should be noted that all illustrations are schematic, and relative dimensions and proportions are adjusted for ease of illustration and drawing. The same reference signs represent corresponding or similar features in different embodiments.

Fig. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present utility model.

FIG. 2 is a schematic diagram illustrating steps of a first ALD cycle according to one embodiment of the present utility model.

FIG. 3 is a schematic diagram illustrating steps of a second atomic layer deposition cycle according to one embodiment of the present utility model.

Fig. 4 is a schematic cross-sectional view of a semiconductor device according to a second embodiment of the present utility model.

Fig. 5 is a schematic cross-sectional view of a semiconductor device according to a third embodiment of the present utility model.

Fig. 6 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment of the present utility model.

Fig. 7 is a schematic cross-sectional view of a semiconductor device according to a fifth embodiment of the present utility model.

Wherein reference numerals are as follows:

10. substrate and method for manufacturing the same

12. Interlayer dielectric layer

20. Composite sub-layer

22. First metal oxide layer

24. Second metal oxide layer

26. Third metal oxide layer

28. Fourth metal oxide layer

10A semiconductor device

10B semiconductor device

10C semiconductor device

10D semiconductor device

10E semiconductor device

CL channel layer

CL1 first stacked channel layer

CL2 second stacked channel layer

CL3 third stacked channel layer

DE drain structure

DE1 first atomic layer deposition cycle

DE1-1 subcycling

DE1-2 sub-cycle

DE1-3 sub-cycle

DE2 second atomic layer deposition cycle

DL1 grid dielectric layer

DL2 grid dielectric layer

GE1 grid structure

GE2 grid structure

M times

m1 times

m2 times

m3 times

N times

OP opening

Number of P times

S1 first side

S2 second surface

SE source structure

V1 source contact

V2 drain contact

Detailed Description

The following description of the preferred embodiments of the present utility model will be presented to enable those skilled in the art to make and use the utility model, and is provided in connection with the accompanying drawings. It should be understood that the following embodiments may be substituted, rearranged, and mixed with features of several different embodiments to achieve other embodiments without departing from the spirit of the disclosure.

In order to facilitate the reader's understanding and simplicity of the drawing, the various figures in the disclosure depict only a portion of the display device, and specific elements in the figures are not necessarily drawn to scale. Furthermore, the number and size of the elements in the drawings are illustrative only and are not intended to limit the scope of the present disclosure. In the drawings, the same or similar elements may be denoted by the same reference numerals. As used herein, the terms "about" and "relative" refer to the portions of the article that are in turn, and thus, are intended to refer to the same elements as those illustrated in the figures.

In this specification, when an element or film is referred to as being "on" or "connected to" another element or film, it can be directly on or connected to the other element or film or other elements or films can be present therebetween. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or film, there are no intervening elements or films present therebetween.

In this specification, a "substrate" is intended to mean any component comprising an exposed surface upon which material may be deposited to fabricate an integrated circuit structure in accordance with embodiments of the present utility model, and may be a semiconductor wafer or a substrate composed of other materials. In some cases, a "substrate" also includes layers of materials and structures fabricated thereon.

Throughout this specification, the terms "forming", "depositing" and "disposing" are used to describe applying a layer of material to a substrate, and, unless otherwise indicated herein, may be performed by any suitable conventional method, such as physical vapor deposition (physical vapor deposition, PVD), chemical vapor deposition (chemical vapor deposition, CVD), electrochemical deposition (electrochemical deposition, ECD), molecular beam epitaxy (molecular beam epitaxy, MBE), atomic layer deposition (atomic layer deposition, ALD), high density plasma chemical vapor deposition (high density plasma chemical vapor deposition, HDP-CVD), plasma-assisted chemical vapor deposition (plasma-enhanced chemical vapor deposition, PECVD), sputtering, evaporation, electroplating, and others not mentioned herein.

Although the terms "first," "second," "third," etc. may be used to describe or name various elements, these elements are not limited by these terms. Such terms are used merely to distinguish one element from another element in the specification, regardless of the order in which such elements are manufactured. The same terms may not be used in the claims and may be substituted with "first", "second", "third", etc. in the order in which the elements of the claims are recited. Accordingly, a first element described in the specification may be termed a second element in the claims.

The semiconductor device and the manufacturing method thereof provided by the utility model can be applied to any device including an oxide semiconductor channel layer, such as a transistor, a diode, a resistor, a capacitor, and a memory, but are not limited thereto.

Referring to fig. 1, a cross-sectional view of a semiconductor device 10A according to a first embodiment of the present utility model is shown. As shown in fig. 1, the semiconductor device 10A includes a substrate 10, a channel layer CL, a gate dielectric layer DL1, a gate structure GE1, and source and drain structures SE and DE.

The substrate 100 may include a semiconductor substrate such as, but not limited to, a silicon (Si) substrate, an epitaxial silicon (epi-Si) substrate, a silicon germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate. In some embodiments, the substrate 100 further includes circuit elements and/or interconnect structures (not shown) fabricated on the semiconductor substrate by semiconductor processes. The circuit elements may include active elements or passive elements such as, but not limited to, transistors, diodes, resistors, capacitors. The interconnect structure may include an interlayer dielectric layer and conductive structures, such as metal interconnects and contact plugs and conductive pads, disposed in the interlayer dielectric layer. In other embodiments, the substrate 100 may include a non-semiconductor substrate, such as a substrate made of glass, ceramic, quartz, sapphire, polyimide (PI), polycarbonate (PC) or polyethylene terephthalate (polyethylene terephthalate, PET), silicon oxide (silicon oxide) coating, silicon nitride (silicon nitride) coating, or a combination of the foregoing materials, but is not limited thereto.

The channel layer CL is a stacked layer composed of a plurality of nano-films deposited on the substrate 10, and includes a first surface S1 and a second surface S2 opposite to each other, wherein the second surface S2 faces the substrate 10. The channel layer CL can be further divided into a first stacked channel layer CL1 and a second stacked channel layer CL2 according to the material and arrangement of the stacked films. According to an embodiment of the present utility model, the first stacked channel layer CL1 is formed by stacking a plurality of composite sub-layers 20, wherein each composite sub-layer 20 is formed by sequentially stacking a first metal oxide layer 22, a second metal oxide layer 24 and a third metal oxide layer 26. The second stacked channel layer CL2 is entirely composed of the fourth metal oxide layer 28. The number of layers of the composite sub-layer 20 and the metal oxide layers 22, 24, 26, 28 shown in fig. 1 is merely exemplary, and the actual number of layers is adjusted according to design requirements.

The first metal oxide layer 22, the second metal oxide layer 24, the third metal oxide layer 26 and the fourth metal oxide layer 28 each comprise a metal oxide (metal oxide), wherein the metal component is preferably selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), indium gallium, indium zinc, gallium zinc, indium gallium zinc. According to an embodiment of the present utility model, the first metal oxide layer 22 is an indium oxide (InO) layer, the second metal oxide layer 24 is a gallium oxide (GaO) layer, the third metal oxide layer 26 is a zinc oxide (ZnO) layer, and the fourth metal oxide layer 28 is an indium oxide (InO) layer. The first stack channel layer CL1 may be referred to as an Indium Gallium Zinc Oxide (IGZO) layer as a whole, and the second stack channel layer CL2 may be referred to as an indium oxide (InO) layer as a whole. The energy band of indium forms the main electron transport path of the channel layer CL, gallium mainly controls the carrier concentration (carrier density) of the channel layer CL, and zinc can adjust the crystalline/amorphous (crystalline/amorphous) degree of the channel layer CL.

It should be noted that, the lamination sequence of the first metal oxide layer 22, the second metal oxide layer 24 and the third metal oxide layer 26 in the composite sub-layer 20 shown in fig. 1 from bottom (near the substrate 10) to top (far from the substrate 10) is one embodiment of the present utility model, and is not intended to limit the present utility model. In other embodiments the stacking sequence may be adjusted depending on the design of the semiconductor device.

The gate dielectric layer DL1 is disposed on the first surface S1 of the channel layer CL and may be composed of a single or multiple dielectric material layers, and suitable dielectric materials may include silicon oxide (SiO ₂ ) Silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide nitride (SiCN), high dielectric constant (high-k) dielectric materials such as hafnium oxide (HfO) ₂ ) Hafnium silicon oxide (HfSiO) ₄ ) Hafnium silicon oxynitride (HfSiON), aluminum oxide (AlO) zinc oxide (ZrO ₂ ) Titanium oxide (TiO) ₂ ) Such as metal oxide dielectrics, or combinations of the above, but are not limited thereto. According to an embodiment of the utility model, the material of the gate dielectric layer DL1 includes silicon oxide.

The gate structure GE1 is disposed on the first surface S1 of the channel layer CL and is separated from the channel layer CL by the gate dielectric layer DL1 without direct contact. The source structure SE and the drain structure DE are respectively disposed on the first surface S1 of the channel layer CL and located at both sides of the gate structure GE1, and are in direct contact with the second stacked channel layer CL2 of the channel layer CL. The gate structure GE1, the source structure SE, and the drain structure DE respectively include conductive materials, such as metal or nonmetal conductive materials, such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W), titanium and titanium nitride (Ti/TiN), polysilicon (polysilicon), doped silicon (doped silicon), silicide (silicon), or any combination thereof, but are not limited thereto. In some embodiments, the portion of the channel layer CL in contact with the source structure SE and the drain structure DE may include an n-type or p-type doped region (not shown).

In some embodiments, the method of manufacturing the semiconductor device 10A may include the following steps. First, a substrate 10 is provided, then, a first atomic layer deposition cycle (DE 1 shown in fig. 2) is performed M times, a first stacked channel layer CL1 is formed on the substrate 10, and then, a second atomic layer deposition cycle (DE 2 shown in fig. 3) is performed N times, a second stacked channel layer CL2 is formed on the first stacked channel layer CL1, so as to obtain a channel layer CL, where M and N are respectively a positive integer. Then, a deposition process is performed to form a gate dielectric layer DL1 and a gate material layer (e.g., a conductive layer, not shown) on the second stacked channel layer CL2, and then a patterning process (e.g., a photolithography and etching process) is performed multiple times to remove the redundant portions of the gate dielectric layer DL1, the gate material layer and the channel layer CL, so as to obtain the gate dielectric layer DL1, the gate structure GE1 and the channel layer CL shown in fig. 1. In some embodiments, the channel layer CL may optionally be patterned before depositing the gate dielectric layer DL1 and the gate material layer. In some embodiments, an ion implantation process may be selectively performed after patterning the gate structure GE1, and n-type (e.g., arsenic) or p-type (e.g., boron) doping is implanted into the channel layer CL at both sides of the gate structure GE1 using the gate structure GE1 as a mask. Subsequently, a deposition process is performed to form a conductive layer covering the channel layer CL and the gate structure GE1, and then a patterning process is performed to pattern the conductive layer into the source structure SE and the drain structure DE. In some embodiments, an ion implantation process may be performed after patterning the gate structure GE1, and n-type (e.g., arsenic) or p-type (e.g., boron) doping is performed in the channel layer CL on both sides of the gate structure GE1 by using the gate structure GE1 as a mask to form doped regions, so as to reduce the contact resistance of the source structure SE and the drain structure DE. In some embodiments, an annealing process (an) or a plasma treatment may be additionally performed at any suitable stage after the formation of the channel layer CL to adjust the electrical properties of the channel layer CL.

Please refer to fig. 2, which is a schematic diagram illustrating a first ald cycle DE1 according to an embodiment of the utility model. The first atomic layer deposition cycle DE1 is, for example, plasma-enhanced atomic layer deposition, PEALD), which is a super cycle (super cycle) including a plurality of sub-cycles, wherein each sub-cycle includes supplying a metal precursor (metal precursor) into the deposition chamber in a gas phase pulse form, contacting the surface of the substrate 10 and being adsorbed on the surface of the substrate 10, and supplying an oxygen reactant (oxygen reactant) into the deposition chamber in a gas phase pulse form, and reacting with the metal precursor adsorbed on the surface of the substrate 10 to form a metal oxide layer of the composite sub-layer 20 (refer to fig. 1), that is, one composite sub-layer 20 is obtained after completing the first atomic layer deposition cycle DE 1. The deposition chamber may be evacuated using a vacuum pump, or using argon (Ar) or nitrogen (N) ₂ ) Purging (purge) with inert gas to remove excess metal precursor, oxygen reactant, and reaction by-products from the deposition chamber.

As shown in fig. 2, each first atomic layer deposition cycle DE1 includes performing sub-cycles DE1-1 m1 to form a first metal oxide layer 22, then performing sub-cycles DE1-2 m2 to form a second metal oxide layer 24, and then performing sub-cycles DE1-3 m3 to form a third metal oxide layer 26, where m1, m2, m3 are positive integers greater than or equal to 1, respectively. It should be specifically noted that the execution sequence of the sub-cycles DE1-1, DE1-2, DE1-3 shown in fig. 2 is taken as an example, and actually needs to be adjusted according to the expected lamination sequence of the first metal oxide layer 22, the second metal oxide layer 24, and the third metal oxide layer 26 of the composite sub-layer 20, which is not limited to the embodiment shown in fig. 2.

In some embodiments, to form indium oxide (InO) of first metal oxide layer 22, each sub-cycle DE1-1 includes contacting substrate 10 with an indium precursor and then with an oxygen reactant. To form gallium oxide (GaO) of the second metal oxide layer 24, each sub-cycle DE1-2 includes contacting the substrate 10 with a gallium precursor and then with an oxygen reactant. To form zinc oxide (ZnO) of the third metal oxide layer 26, each sub-cycle DE1-3 includes contacting the substrate 10 with a zinc precursor and then with an oxygen reactant. In some embodiments, the indium precursor may include tris (dimethylamino) indium (DADI), the gallium precursor may include trimethylgallium (TMGa), the zinc precursor may include Diethylzinc (DEZ), and the oxygen reactant may include oxygen (O ₂ ) But is not limited thereto. In some embodiments, additional reactant gases, such as, but not limited to, NH, may be provided during the steps of the deposition cycle ₃ 、N ₂ O、NO ₂ 、H ₂ O ₂ To improve the film forming quality of the metal oxide layer.

Please refer to fig. 3, which is a diagram illustrating a second ald cycle DE2 according to an embodiment of the present utility model. The second atomic layer deposition cycle DE2 may be PEALD and includes the same steps as the sub-cycle DE1-1 of the first atomic layer deposition cycle DE1, and thus may include the same materials as the lowermost layer of the second stacked via layer and the first stacked via layer. According to one embodiment of the utility model, the second atomic layer deposition cycle DE2 includes the same steps as the sub-cycle DE1-1, including contacting the substrate 10 with an indium precursor and then with an oxygen reactant to react to form indium oxide (InO) of the fourth metal oxide layer 28.

In some embodiments, the first atomic layer deposition cycle DE1 and the second atomic layer deposition cycle DE2 are performed continuously in-situ (in-situ) in the same deposition chamber without breaking vacuum. In some embodiments, if the gate dielectric layer DL1 is selected to be formed by an atomic layer deposition process, the deposition cycle of the gate dielectric layer DL1 may be continued in situ in the same deposition chamber after the second atomic layer deposition cycle DE2 is completed.

In some embodiments, the process temperature of the first and second atomic layer deposition cycles DE1 and DE2 is not greater than 400 ℃, for example, may be between 20 ℃ and 400 ℃, 100 ℃ and 350 ℃, or 150 ℃ and 300 ℃. In some embodiments, the process temperature of the second atomic layer deposition cycle DE2 may be slightly greater than the process temperature of the first atomic layer deposition cycle DE1 to obtain higher carrier mobility in the portion of the second stacked channel layer CL2.

The number of layers of the first and second stacked via layers CL1 and CL2 may be controlled to achieve a desired thickness by adjusting the number M of the first atomic layer deposition cycles DE1 and the number N of the second atomic layer deposition cycles DE 2. The number of layers and thickness of each of the first, second and third metal oxide layers 22, 24 and 26 of the first stacked channel layer CL1 are controlled by adjusting the number of times m1, m2 and m3 of the sub-cycles DE1-1, DE1-2, DE 1-3. For example, m1 equal to 1 indicates that the first metal oxide layer 22 includes a single layer of indium oxide (InO), and m1 equal to 2 indicates that the first metal oxide layer 22 includes two layers of indium oxide (InO). The same concept applies to the second metal oxide layer 24 and the third metal oxide layer 26.

According to an embodiment of the present utility model, N is preferably greater than M, for example, about 1 to 1.5 times M, and M1, M2, M3 are equal to each other and less than any one of M and N, so that the stack composition and component concentration of the channel layer CL obtained can achieve a preferred carrier mobility. According to an embodiment of the present utility model, M may be between 5 and 10, N may be between 10 and 15, and M1, M2, and M3 are each 1, that is, the first stacked channel layer CL1 is formed by 5 to 10 composite sublayers 20, wherein each composite sublayer 20 is formed by a single layer of indium oxide (InO), a single layer of gallium oxide (GaO), and a single layer of zinc oxide (ZnO). With such a stack composition design, the atomic percent (atomic percentage) concentration of indium, gallium, zinc, oxygen of first stacked channel layer CL1 is between 16% and 25%, respectively, or the ratio is about 1:1:1:1. The second stacked channel layer CL2 is composed of 10 to 15 layers of indium oxide (InO), wherein the atomic percentage concentration of indium and oxygen is between 45% and 55%, respectively, or the ratio is about 1:1. According to an embodiment of the present utility model, the first stacked channel layer CL1 may have a higher amorphous (amorphlus) degree than the second stacked channel layer CL2 due to the difference of the stacked layers, and thus the channel layer CL may also be referred to as a hetero channel layer (hetero channel layer). The semiconductor device 10A of the present utility model can improve carrier mobility, carrier concentration and threshold stability by providing the second stacked channel layer CL2 with a high indium concentration (In-rich) entirely composed of InO as the main channel region between the first stacked channel layer CL1 and the gate structure GE1 In an IGZO ratio of about 1:1:1:1.

The design of the hetero-channel layer of the present utility model can also be applied to other types of semiconductor devices. The following description will be made with respect to different embodiments of the present utility model, and for simplicity of description, the following description mainly describes different parts of each embodiment, and the same parts will not be repeated. In addition, like parts in the various embodiments of the present utility model are designated by like reference numerals to facilitate cross-reference between the various embodiments.

Referring to fig. 4, a cross-sectional view of a semiconductor device 10B according to a second embodiment of the present utility model is shown. As with the semiconductor device 10A shown in fig. 1, the semiconductor device 10B includes a substrate 10, a channel layer CL, a gate dielectric layer DL1, a gate structure GE1, and source and drain structures SE and DE. Unlike the semiconductor device 10A shown in fig. 1, the source structure SE and the drain structure DE of the semiconductor device 10B are disposed between the channel layer CL and the substrate 10, that is, the source structure SE and the drain structure DE are located on the second face S2 of the channel layer CL opposite to the gate structure GE1. The manufacturing method of the semiconductor device 10B may include the following steps. First, a substrate 10 is provided, then a deposition process and a patterning process are performed, a conductive layer is formed on the substrate 10 and patterned into a source structure SE and a drain structure DE, and then a first atomic layer deposition cycle DE1 (refer to fig. 2) is performed M times and a second atomic layer deposition cycle DE2 (refer to fig. 3) is performed N times, so that a first stacked channel layer CL1 and a second stacked channel layer CL2 (which together form a channel layer CL) are sequentially formed and cover the source structure SE and the drain structure DE. The stack composition, stack material, and constituent concentration of the first stack channel layer CL1 and the second stack channel layer CL2 may be referred to the description of the first embodiment described above, and will not be repeated here. After patterning the channel layer CL, a deposition process is performed to form a gate dielectric layer DL1 and a gate material layer (not shown) on the channel layer CL, and then the gate material layer is patterned to obtain the gate structure GE1 shown in fig. 4. Subsequently, semiconductor processes such as etching, deposition, patterning, etc. are performed to form a source contact V1 and a drain contact V2 penetrating the gate dielectric layer DL1 and electrically connected to the source structure SE and the drain structure DE, respectively. In some embodiments, the portion of the first stacked channel layer CL1 in contact with the source structure SE and the drain structure DE shown in fig. 4 is the indium oxide (InO) layer of the lowermost composite sublayer 20 thereof. In some embodiments, the second atomic layer deposition cycle DE2 may be optionally inserted one or more times before the first atomic layer deposition cycle DE1, so that a third stacked channel layer (not shown) having the same composition, the same number of layers (thickness) or different from the second stacked channel layer CL2 is formed between the first stacked channel layer CL1 and the substrate 10, the source structure SE, and the drain structure DE.

Referring to fig. 5, a cross-sectional view of a semiconductor device 10C according to a third embodiment of the present utility model is shown. As with the semiconductor device 10A shown in fig. 1, the semiconductor device 10C includes a substrate 10, a channel layer CL, a gate dielectric layer DL1, a gate structure GE1, and source and drain structures SE and DE. Unlike the semiconductor device 10A shown in fig. 1, the semiconductor device 10C is a vertical channel (vertical channel) transistor in which a source structure SE and a drain structure DE are vertically stacked on a substrate 10 and are separated by an interlayer dielectric layer 12, and a channel layer CL, a gate dielectric layer DL1 and a gate structure GE1 are disposed on sidewalls of an opening OP passing through the source structure SE, the interlayer dielectric layer 12 and a portion of the drain structure DE. The method of manufacturing semiconductor device 10C may includeThe following steps. First, a substrate 10 is provided, and then a deposition process and a patterning process (e.g., a photolithography and etching process) are sequentially performed on the substrate 10 to form a drain structure DE, an interlayer dielectric layer 12 and a source structure SE, wherein the drain structure DE and the source structure SE are formed of patterned conductive layers, and the materials may include, but are not limited to, metal or non-metal conductive materials such as aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W), titanium and titanium nitride (Ti/TiN), polysilicon (poly silicon), doped silicon (doped silicon), silicide (silicon), or any combination thereof. The interlayer dielectric layer 12 may be composed of a single layer or multiple layers of dielectric material, and suitable dielectric materials may include silicon oxide (SiO) ₂ ) Silicon nitride (SiN), silicon oxynitride (SiON), or other suitable dielectric material. An etching process is then performed to form openings OP through the source structure SE, the interlayer dielectric layer 12 and through portions of the drain structure DE. Next, a first atomic layer deposition cycle DE1 (refer to fig. 2) and a second atomic layer deposition cycle DE2 (refer to fig. 3) are sequentially performed M times, and a first stacked channel layer CL1 and a second stacked channel layer CL2 (both together constituting a channel layer CL) are formed in a common type along the side walls and the bottom surfaces of the openings OP. The stack composition, stack material, and constituent concentration of the first stack channel layer CL1 and the second stack channel layer CL2 may be referred to the description of the first embodiment described above, and will not be repeated here. Then, a deposition process is performed to form a gate dielectric layer DL1 and a gate material layer (not shown) on the channel layer CL and fill the openings OP. Then, patterning is performed to remove the gate material layer, the gate dielectric layer DL1 and the excess portion of the channel layer CL, thereby obtaining the semiconductor device 10C shown in fig. 5. The channel layer CL between the source structure SE and the drain structure DE is a vertical channel region of the semiconductor device 10C, which is turned on and off by the gate structure GE1 filled in the opening OP.

Referring to fig. 6, a cross-sectional view of a semiconductor device 10D according to a fourth embodiment of the present utility model is shown. As with the semiconductor device 10A shown in fig. 1, the semiconductor device 10D includes a substrate 10, a channel layer CL, a gate dielectric layer DL1, a gate structure GE1, and source and drain structures SE and DE. The semiconductor device 10D is different from the semiconductor device 10A shown in fig. 1 in that the semiconductor device 10D is a bottom gate (bottom gate) transistor, in which a gate structure GE1 is disposed between a channel layer CL and a substrate 10, and a source structure SE and a drain structure DE are respectively located on a second surface S2 and a first surface S1 opposite to the substrate 10. The manufacturing method of the semiconductor device 10D may include the following steps. First, a substrate 10 is provided, then a deposition process and a patterning process are performed to form a gate structure GE1 on the surface of the substrate 10, and then a deposition process is performed to form a gate dielectric layer DL1 to cover the substrate 10 and the gate structure GE1 comprehensively. Next, a second atomic layer deposition cycle DE2 (refer to fig. 3) is performed N times and a first atomic layer deposition cycle DE1 (refer to fig. 2) is performed M times, and a second stacked channel layer CL2 and a first stacked channel layer CL1 (both together constituting a channel layer CL) are sequentially formed on the substrate 10 and cover the gate structure GE1. The stack composition, stack material, and constituent concentration of the first stack channel layer CL1 and the second stack channel layer CL2 may be referred to the description of the first embodiment described above, and will not be repeated here. After patterning the channel layer CL, a deposition process and a patterning process are performed to form a conductive layer on the channel layer CL and pattern the conductive layer into a source structure SE and a drain structure DE, thereby obtaining the semiconductor device 10D shown in fig. 6.

Referring to fig. 7, a cross-sectional view of a semiconductor device 10E according to a fifth embodiment of the present utility model is shown. The semiconductor device 10D includes a substrate 10, a channel layer CL, a gate dielectric layer DL1, a gate structure GE1, and source and drain structures SE and DE. Unlike the semiconductor device 10A shown in fig. 1, the semiconductor device 10E is a double gate transistor, which includes a gate structure GE1 (or referred to as a top gate structure) and a gate dielectric layer DL1 (or referred to as a top gate dielectric layer) disposed on a first side S1 of a channel layer CL, and further includes a gate structure GE2 (or referred to as a bottom gate structure) and a gate dielectric layer DL2 (or referred to as a bottom gate dielectric layer) disposed between a second side S2 of the channel layer CL and the substrate 10, and the channel layer CL of the semiconductor device 10E is collectively composed of a first stacked channel layer CL1, a second stacked channel layer CL2 and a third stacked channel layer CL 3. The manufacturing method of the semiconductor device 10E may include the following steps. First, a substrate 10 is provided, then a deposition process and a patterning process are performed to form a gate structure GE2 on the surface of the substrate 10, and then a deposition process is performed to form a gate dielectric layer DL2 to cover the substrate 10 and the gate structure GE2 comprehensively. Next, a second atomic layer deposition cycle DE2 (referring to fig. 3, P is a positive integer greater than or equal to 1) is performed P times, a third stacked channel layer CL3 is formed on the gate dielectric layer DL2, then a first atomic layer deposition cycle DE1 (referring to fig. 2) is performed M times, a first stacked channel layer CL1 is formed on the third stacked channel layer CL3, and then a second atomic layer deposition cycle DE2 (referring to fig. 3) is performed N times, thereby forming a second stacked channel layer CL2 on the first stacked channel layer CL 1. The stack composition and constituent concentration of the first stacked via layer CL1 and the second stacked via layer CL2 may be referred to the description of the first embodiment described above, and will not be repeated here. The third stacked via layer CL3 and the second stacked via layer CL2 are both DE2 fabricated by the second atomic layer deposition cycle, the same reactant gases are used, and the number of times N and the number of times P may be selected to be the same or different according to device performance requirements (i.e., the thicknesses of the third stacked via layer CL3 and the second stacked via layer CL2 may be the same or different). After patterning the channel layer CL, a deposition process and a patterning process are performed, a source structure SE and a drain structure DE are formed on the channel layer CL at two sides of the gate structure GE2, then a gate dielectric layer DL is formed to cover the source structure SE, the drain structure DE and the channel layer CL comprehensively, and then a gate structure GE1 is formed on the gate dielectric layer DL.

In summary, the semiconductor device and the method for manufacturing the same according to the present utility model are designed such that the oxide semiconductor channel layer is formed by two-stage atomic layer deposition cycles, so that the oxide semiconductor channel layer can be divided into two portions with different stacked layers along the thickness direction, wherein the portion farther from the gate structure is formed by the circulating stacked layers of different oxide semiconductor materials, and the portion nearer to the gate structure is formed by a single oxide semiconductor material mainly used for forming the electron transfer path.

The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims

1. A semiconductor device, comprising:

a first stacked via layer including opposing first and second sides;

a first gate structure on the first side of the first stacked channel layer;

the first grid dielectric layer is positioned between the first grid structure and the first stacking channel layer; and

the second stacking channel layer is positioned between the first gate dielectric layer and the first stacking channel layer; the first stacking channel layer is a plurality of stacked composite sublayers, the composite sublayers are an indium oxide layer, a gallium oxide layer and a zinc oxide layer which are sequentially stacked, and the second stacking channel layer is an indium oxide layer.

2. The semiconductor device of claim 1, wherein the second face of the second stacked via layer and the second face of the first stacked via layer are both indium oxide layers.

3. The semiconductor device according to claim 1, further comprising:

a second gate structure on the second side of the first stacked channel layer;

a second gate dielectric layer between the second gate structure and the first stacked channel layer; and

and the third stacking channel layer is positioned between the second gate dielectric layer and the first stacking channel layer, wherein the materials of the second stacking channel layer and the third stacking channel layer are the same.