CN219979133U - Electrophoretic display driving system based on FPGA - Google Patents

Abstract

The utility model discloses an electrophoretic display driving system based on an FPGA, which relates to the technical field of electronic paper driving, and comprises: an FPGA driving board and a power management chip PMIC; the FPGA driving board is connected with the PC equipment through a serial port, and the output end of the FPGA driving board is connected with the driving end of the EPD electronic paper; the FPGA driving plate comprises an FPGA chip and a temperature sensor; the FPGA chip comprises SDRAM and FLASH. The driving system provided by the utility model is a bottom layer driving of the electronic paper, and has the advantages of low power consumption, strong expansibility, convenience and rapidness in upgrading and the like. The driving system provided by the utility model does not use a special driving chip, is more flexible in design, can be developed for the second time, and supports the driving of electronic paper with 16-level gray scale.

Description

Electrophoretic display driving system based on FPGA

Technical Field

The utility model relates to the technical field of electronic paper driving, in particular to an electrophoretic display driving system based on an FPGA.

Background

An electrophoretic display (Electrophoretic deposition, EPD) is a novel display technology with bistable, reflective display properties, which uses the principle that charged colloidal particles can move in an electric field, and in a liquid environment, color alternate display is realized by the movement of charged substances between electrodes to two poles of the electric field under the action of the electric field.

The driving of electronic paper in the market at present generally uses a special driving chip for an electronic paper chip manufacturer, and the MCU controls the display content of the electronic paper by operating the special driving chip; the MCU directly simulates the driving time sequence of the electronic paper through the IO pin to display the electronic paper in a software programming mode. The special chip solution is often limited to products of specific factories, and has high price and poor general performance. The implementation of the driver by using a software programming manner often occupies a large amount of resources of the MCU, resulting in the degradation of system performance.

With the improvement of the acceptance of electronic paper in the market, research and design of electronic paper driving chips with low cost and comprehensive functions are independently carried out.

Disclosure of Invention

In view of this, the utility model provides an FPGA-based driving system for an electrophoretic display, which is designed and developed for black-and-white dual-color EPD electronic paper, and is based on FPGA chips, so as to achieve the goal of low power consumption, high integration and high performance of the driving system for the electrophoretic electronic paper.

For this purpose, the utility model provides the following technical scheme:

the utility model provides an electrophoretic display driving system based on FPGA, the driving system includes: an FPGA driving board and a power management chip PMIC; the FPGA driving board is connected with the PC equipment through a serial port, and the output end of the FPGA driving board is connected with the driving end of the EPD electronic paper;

the FPGA driving plate comprises an FPGA chip and a temperature sensor; the FPGA chip comprises SDRAM and FLASH.

Further, the FPGA chip adopts the model P4CE10F17C 8.

Further, the temperature sensor employs SE95.

Further, the PC device includes: waveform conversion means and data conversion/transmission means.

Further, the FPGA driving board includes: the system comprises a main control module, a power supply module, a temperature detection module, an SDRAM read-write module, a FLASH read-write module, a data module and a serial communication module; the power module, the data module, the FLASH read-write module and the FLASH read-write module are respectively connected with the main control module in a data communication manner; the temperature detection module and the SDRAM read-write module are respectively connected with the data module in a data communication manner; the temperature detection module is connected with the temperature sensor in a data communication manner; the serial communication module is in data communication connection with the PC equipment.

Further, the driving system supports 16-level and lower gray-scale electrophoretic electronic paper driving.

The utility model has the advantages and positive effects that: the driving system provided by the utility model is a bottom layer driving of the electronic paper, and has the advantages of low power consumption, strong expansibility, convenience and rapidness in upgrading and the like. The driving system provided by the utility model does not use a special driving chip, is more flexible in design, can be developed for the second time, and supports the driving of electronic paper with 16-level gray scale.

Drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present utility model, and other drawings may be obtained according to the drawings without inventive effort to a person skilled in the art.

Fig. 1 is a block diagram of an FPGA-based electrophoretic display driving system according to an embodiment of the present utility model.

Detailed Description

In order that those skilled in the art will better understand the present utility model, a technical solution in the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present utility model, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present utility model without making any inventive effort, shall fall within the scope of the present utility model.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present utility model and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

As shown in fig. 1, the present utility model provides an EPD driving system based on FPGA, which includes: an FPGA driving board and a power management chip PMIC; the FPGA driving board is connected with the PC equipment on one hand so as to acquire waveform data through the PC equipment, and is connected with the driving end of the EPD type electronic paper on the other hand so as to output a driving signal to the EPD type electronic paper, so that the driving of the EPD type electronic paper is realized; the PMIC is used for supplying power to the FPGA drive board.

The core of the FPGA drive board is an FPGA chip, the FPGA chip can adopt the model P4CE10F17C8, and at least comprises storage areas such as SDRAM, FLASH and the like, and waveform data and drive parameters can be stored. Still include on the FPGA drive plate: and a temperature sensor, which may employ SE95 for detecting temperature and determining a driving waveform according to the temperature.

The FPGA driving plate is mainly used for driving the EPD electronic paper, and comprises the following functional modules: the main control module edp _ctrl, the power supply module pmic_ctrl, the temperature detection module se95_ctrl, the SDRAM read-write module sdam_ctrl, the Flash read-write module flash_ctrl, the data module epd_data, the serial communication module uart_ctrl and the system integrated IP soft core comprise FIFO and the like. Wherein edp _ctrl is a main control module of the FPGA and is used for controlling each functional module; pmic_ctrl is a power control module of the FPGA, and is used for implementing control of the PMIC; se95_ctrl is used to detect temperature; the srram_ctrl and the flash_ctrl are respectively used for realizing data reading and writing of SDRAM and FLASH; the FIFO comprises srram_fifo and flash_fifo; the uart_ctrl is used for realizing interaction with a data conversion/transmission tool in the PC equipment and realizing data transmission; epd_data is used to implement data processing. More specifically, pmic_ctrl, data_ctrl, flash_ctrl, srram_ctrl are respectively connected in data communication with edp _ctrl; se95_ctrl and srram_ctrl are respectively connected with epd_data in data communication; SE95 ctrl is connected in data communication with SE 95; the uart_ctrl is in data communication connection with the PC equipment; meanwhile, flash_ctrl and srram_ctrl are respectively connected with the IP soft core in a data communication way, so that data reading and processing are realized.

The PC equipment is used for generating a WF Waveform file, the WF Waveform file generates a data file through a WF debugging tool, and the data file is combined with the generated data file through a data conversion/transmission tool and is transmitted to the FLASH for storage. The picture data to be displayed is also written into the SDRAM through the serial port by the data conversion/transfer means. When the picture information is displayed, the epd_ctrl of the FPGA stores the picture data and WF waveform data into the SDRAM from the FLASH and the SDRAM through the FIFO, and reads according to the driving time sequence of the EPD refreshing. The pmic_ctrl controls the voltage required by the power supply when the electronic paper is refreshed, and controls the power supply to enter a dormant state after the refresh is finished. The speed at which charged particles move in EPD is affected by the ambient temperature, i.e. different temperatures correspond to different driving waveforms. The se95_ctrl acquires the ambient temperature by controlling the se95 data temperature sensor chip, judges the read temperature at the epd_data module and selects a proper WF waveform read of a temperature interval to drive the EPD.

The driving system is a bottom driving of the electronic paper and has the advantages of low power consumption, strong expansibility, convenience and quickness in upgrading and the like. The driving system does not use a special driving chip, is more flexible in design and can be developed secondarily. The driving system can be applied to electronic paper driving of 6 inches, 7.5 inches and other sizes, and supports electronic paper driving with gray scales of 16 levels and below.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the same; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the utility model.

Claims (6)

1. An FPGA-based electrophoretic display drive system, the drive system comprising: an FPGA driving board and a power management chip PMIC; the FPGA driving board is connected with the PC equipment through a serial port, and the output end of the FPGA driving board is connected with the driving end of the EPD electronic paper;

the FPGA driving plate comprises an FPGA chip and a temperature sensor; and the FPGA chip comprises SDRAM and FLASH.

2. The FPGA-based electrophoretic display driving system of claim 1, wherein the FPGA chip is of the type P4CE10F17C 8.

3. The FPGA-based electrophoretic display driving system of claim 1, wherein the temperature sensor employs SE95.

4. The FPGA-based electrophoretic display driving system of claim 1, wherein the PC device comprises: waveform conversion means and data conversion/transmission means.

5. The FPGA-based electrophoretic display driving system of claim 1, wherein the FPGA driving board comprises: the system comprises a main control module, a power supply module, a temperature detection module, an SDRAM read-write module, a FLASH read-write module, a data module and a serial communication module; the power supply module, the data module, the FLASH read-write module and the FLASH read-write module are respectively connected with the main control module in a data communication manner; the temperature detection module and the SDRAM read-write module are respectively connected with the data module in a data communication manner; the temperature detection module is connected with the temperature sensor in a data communication manner; the serial communication module is in data communication connection with the PC equipment.

6. The FPGA-based electrophoretic display driving system of claim 1, wherein the driving system supports 16-level and below gray scale electrophoretic electronic paper driving.