CN219938601U

CN219938601U - Mainboard and terminal equipment compatible with flash memory chips of different standards

Info

Publication number: CN219938601U
Application number: CN202320607022.9U
Authority: CN
Inventors: 邬永清
Original assignee: Shenzhen Weibu Information Co Ltd
Current assignee: Shenzhen Weibu Information Co Ltd
Priority date: 2023-03-24
Filing date: 2023-03-24
Publication date: 2023-10-31
Anticipated expiration: 2033-03-24

Abstract

The embodiment of the utility model discloses a main board compatible with flash memory chips of different standards and terminal equipment, wherein a main board body is provided with a flash memory welding position, a plurality of power supply welding positions and a voltage reduction module; welding a first flash memory chip on each flash memory welding position, welding corresponding electronic elements on each power supply welding position to form a first power supply path, and outputting a first power supply voltage and a second power supply voltage to the first flash memory chip through the first power supply path to supply power; welding a second flash memory chip on the flash memory welding positions, and welding corresponding electronic elements on each power supply welding position to form a second power supply path; the voltage reducing module reduces the first power supply voltage to a third power supply voltage, reduces the second power supply voltage to a fourth power supply voltage, and outputs the fourth power supply voltage to the second flash memory chip through the second power supply path to supply power. The flash memory chips with different standards can be welded on one main board and the voltage required by the work can be provided for the flash memory chips, so that the problem that the existing main board cannot be compatible with the flash memory chips with different standards is solved.

Description

Mainboard and terminal equipment compatible with flash memory chips of different standards

Technical Field

The present utility model relates to the field of electronic technologies, and in particular, to a motherboard compatible with flash memory chips of different standards and a terminal device.

Background

Cell phones are one of the most commonly used electronic devices in modern times, and the storage products used therein are also changing. The change of the mobile phone flash memory from the earliest SD (memory card) to the latest UFS (Universal Flash Storage, universal flash memory) chip accelerates the data writing and reading speed.

The standard of UFS chips is also being updated continuously as a flash memory commonly used at present. For example, UFS3.1 chip adopts UFS3.1 standard (latest technical specification standard), and has fast read/write speed, but is more expensive than UFS2.1 chip (UFS 2.1 standard). And, the power supply requirement of the UFS2.1 chip is 3.3V and 1.8V, and the power supply requirement of the UFS3.1 chip is 2.5V and 1.2V. If one motherboard needs to use the chips with the 2 standards, 2 motherboards need to be designed, which increases the design cost.

Disclosure of Invention

Aiming at the technical problems, the embodiment of the utility model provides a main board and terminal equipment compatible with flash memory chips of different standards, so as to solve the problem that the existing main board cannot be compatible with the flash memory chips of different standards.

The embodiment of the utility model provides a main board compatible with flash memory chips of different standards, which comprises a main board body, wherein a power module for outputting a first power supply voltage and a second power supply voltage is arranged on the main board body; the flash memory welding bit is connected with each power supply welding bit and each power supply welding bit, and the voltage reduction module is connected with each power supply welding bit;

welding a first flash memory chip on each flash memory welding position, welding corresponding electronic elements on each power supply welding position to form a first power supply path, and outputting a first power supply voltage and a second power supply voltage to the first flash memory chip through the first power supply path to supply power;

welding a second flash memory chip on the flash memory welding positions, and welding corresponding electronic elements on each power supply welding position to form a second power supply path; the voltage reduction module reduces the first power supply voltage to a third power supply voltage, reduces the second power supply voltage to a fourth power supply voltage, and outputs the third power supply voltage and the fourth power supply voltage to the second flash memory chip through a second power supply path to supply power.

Optionally, in the main board compatible with flash memory chips of different standards, a first power supply welding position, a second power supply welding position, a first capacitor, a second capacitor and a third capacitor are arranged on the main board body;

the first bonding pad of the first power supply welding position is connected with the first bonding pad of the first power supply welding position, one end of the first capacitor and the first group of power supply bonding pads of the flash memory welding position; the second bonding pad of the first power supply welding position is connected with the first power supply end, the second bonding pad of the first power supply welding position is connected with the voltage reduction module, the first bonding pad of the second power supply welding position is connected with one end of the second capacitor and the second group of power supply bonding pads of the flash memory welding position, the second bonding pad of the second power supply welding position is connected with the voltage reduction module, the first bonding pad of the second power supply welding position is connected with one end of the third capacitor and the third group of power supply bonding pads of the flash memory welding position, and the second bonding pad of the second power supply welding position is connected with the second power supply end; the other end of the first capacitor, the other end of the second capacitor and the other end of the third capacitor are grounded.

Optionally, in the motherboard compatible with flash memory chips of different standards, the first group of power supply pads includes 10 VCC pins of the flash memory chip, the second group of power supply pads includes 8 VCCQ pins of the flash memory chip, and the third group of power supply pads includes 8 VCCQ2 pins of the flash memory chip.

Optionally, in the motherboard compatible with the flash memory chips of different standards, a first flash memory chip is welded on the flash memory welding position, a first resistor is welded on the first power supply welding position, and a second resistor is welded on the second power supply welding position;

one end of the first resistor is connected with each VCC pin of the first flash memory chip and one end of the first capacitor, the other end of the first resistor is connected with the first power supply end, one end of the second resistor is connected with one end of the third capacitor and each VCCQ2 pin of the first flash memory chip, the other end of the second resistor is connected with the second power supply end, and each VCCQ pin of the first flash memory chip is suspended.

Optionally, in the motherboard compatible with the flash memory chips of different standards, a second flash memory chip is welded on the flash memory welding bit, a third resistor is welded on the first power supply welding bit, and a fourth resistor is welded on the second power supply welding bit;

one end of the third resistor is connected with each VCC pin of the second flash memory chip and one end of the first capacitor, the other end of the third resistor is connected with the voltage reduction module, the other end of the fourth resistor is connected with the voltage reduction module, and each VCCQ2 pin of the second flash memory chip is suspended.

Optionally, in the motherboard compatible with flash memory chips of different standards, the voltage reducing module includes a first voltage reducing unit and a second voltage reducing unit, where the first voltage reducing unit is connected to a second pad of the first power supply welding position, and the second voltage reducing unit is connected to a second pad of the second power supply welding position;

the first voltage reducing unit is used for reducing the first power supply voltage to a third power supply voltage and outputting the third power supply voltage to the second flash memory chip for power supply;

the second step-down unit is used for step-down the second power supply voltage to a fourth power supply voltage and outputting the fourth power supply voltage to the second flash memory chip for power supply.

Optionally, in the motherboard compatible with flash memory chips of different standards, the first step-down unit includes a first step-down chip, a fifth resistor and a sixth resistor;

the VIN pin of the first buck chip inputs a first power supply voltage, the EN pin of the first buck chip inputs an enabling signal, the BIAS pin of the first buck chip inputs a fifth power supply voltage, and the GND pin of the first buck chip is grounded; the VOUT pin of the first buck chip is connected with one end of the fifth resistor; the ADJ pin of the first buck chip is connected with the other end of the fifth resistor and one end of the sixth resistor, and the other end of the sixth resistor is grounded.

Optionally, in the motherboard compatible with flash memory chips of different standards, the first voltage reducing unit further includes a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor and an eighth capacitor;

the fourth capacitor is connected between VIN pin and ground of the first buck chip, the fifth capacitor is connected between EN pin and ground of the first buck chip, the sixth capacitor is connected between BIAS pin and ground of the first buck chip, the seventh capacitor is connected in parallel with the fifth resistor, and the eighth capacitor is connected between VOUT pin and ground of the first buck chip.

Optionally, in the motherboard compatible with flash memory chips of different standards, the first voltage dropping unit further includes a seventh resistor and an eighth resistor;

one end of the seventh resistor is connected with an EN pin of the first buck chip, the other end of the seventh resistor is input with an enabling signal, one end of the eighth resistor is connected with a BIAS pin of the first buck chip, and the other end of the eighth resistor is input with a fifth power supply voltage.

A second aspect of the embodiment of the present utility model provides a terminal device, including a housing, where the housing is provided with a motherboard compatible with flash memory chips of different standards.

In the technical scheme provided by the embodiment of the utility model, a main board compatible with flash memory chips of different standards comprises a main board body, wherein a power module for outputting a first power supply voltage and a second power supply voltage, a flash memory welding position, a plurality of power supply welding positions and a voltage reduction module are arranged on the main board body; the flash memory welding bit is connected with each power supply welding bit and each power supply welding bit, and the voltage reduction module is connected with each power supply welding bit; welding a first flash memory chip on each flash memory welding position, welding corresponding electronic elements on each power supply welding position to form a first power supply path, and outputting a first power supply voltage and a second power supply voltage to the first flash memory chip through the first power supply path to supply power; welding a second flash memory chip on the flash memory welding positions, and welding corresponding electronic elements on each power supply welding position to form a second power supply path; the voltage reduction module reduces the first power supply voltage to a third power supply voltage, reduces the second power supply voltage to a fourth power supply voltage, and outputs the third power supply voltage and the fourth power supply voltage to the second flash memory chip through a second power supply path to supply power. By selecting the loading mode of the flash memory chip and the electronic element, the voltage required by the work can be provided for the flash memory chip on a main board according to the standard of the flash memory chip, and the power supply requirements of different standards are met. And a main board does not need to be designed for each standard, so that the research and development cost and the manufacturing cost of the main board are saved.

Drawings

Fig. 1 is a block diagram of a motherboard compatible with flash memory chips of different standards in an embodiment of the present utility model.

FIG. 2 is a schematic circuit diagram of a flash welding bit, a power welding bit, and a power welding bit according to an embodiment of the present utility model.

Fig. 3 is a schematic diagram of a circuit diagram of a first flash chip according to the embodiment of the present utility model.

FIG. 4 is a diagram of a circuit diagram of a second flash memory chip according to the embodiment of the present utility model.

Fig. 5 is a circuit schematic diagram of a first step-down unit according to an embodiment of the utility model.

Fig. 6 is a circuit schematic diagram of a second step-down unit according to an embodiment of the utility model.

Fig. 7 is a schematic circuit layout diagram of a first flash memory chip in an embodiment of the utility model.

FIG. 8 is a circuit layout diagram of a second flash memory chip according to an embodiment of the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. Embodiments of the present utility model are intended to be within the scope of the present utility model as defined by the appended claims.

Referring to fig. 1 and fig. 2, the terminal device provided in the embodiment of the utility model includes a housing, in which a motherboard compatible with flash memory chips of different standards is disposed. The different standards are mainly UFS2.1 standard and UFS3.1 standard, and may be updated to UFS4.1 standard later. The differences based on different standards are mainly that the voltage values of the power supply voltages required by the flash memory chips are different, the signals defined by other pins are the same or can be used in a compatible way, and the number of the pins is the same; therefore, in this embodiment, a plurality of soldering sites are reserved on the motherboard, and according to the standard used as required, the flash memory chip and the electronic device corresponding to the standard are soldered on the corresponding soldering sites. Specifically:

the main board comprises a main board body, wherein a flash memory welding position 10, a plurality of power supply welding positions and a voltage reduction module 20 are arranged on the main board body. The flash memory welding bit 10 is connected with each power supply welding bit and each power supply welding bit, and the voltage reducing module 20 is connected with each power supply welding bit. The flash welding bit 10 is welded with a first flash memory chip or a second flash memory chip (the standards of the two flash memory chips are different and are distinguished by a first flash memory chip and a second flash memory chip); when the first flash memory chip is mounted, corresponding electronic elements are welded on each power supply welding position to form a first power supply path, and the first power supply voltage +V3P3SX and the second power supply voltage +V1P8SX are output to the first flash memory chip through the first power supply path to supply power; and when the second flash memory chip is mounted, corresponding electronic elements are welded on each power welding position to form a second power supply path. The step-down module 20 steps down the first supply voltage +v3p3sx to a third supply voltage +v2p5s_ufs, steps down the second supply voltage +v1p8sx to a fourth supply voltage +v1p2s_ufs, and outputs the third supply voltage +v2p5s_ufs and the fourth supply voltage +v1p2s_ufs to the second flash memory chip through the second supply path.

According to the embodiment, the welding modes of the flash memory chip, each power supply welding position, the power supply welding position and the electronic element of the upper part are selected according to the requirements of users. The whole circuit structure and wiring of the main board are not required to be changed, and under the condition that the layout of the main board is not changed, the flash memory chip and the electronic element can be provided with the voltage required by working according to the standard of the flash memory chip on one main board by modifying the BOM (Bill of materials ) and selecting the loading mode of the flash memory chip and the electronic element, so that the power supply requirements of different standards are met. And a main board does not need to be designed for each standard, so that the research and development cost and the manufacturing cost of the main board are saved.

It should be understood that the motherboard must further be provided with a power module and a processor, where the power module is configured to output each voltage, for example, a first power supply end of the power module is configured to output a first power supply voltage +v3p3sx of 3.3v, a second power supply end is configured to output a second power supply voltage +v1p8sx of 1.8v, and a fifth power supply end is configured to output a fifth power supply voltage +v5p0a of 5V; the processor is used for performing read-write control of data with the flash memory chip, outputting an enabling signal SLP_S3_N and the like; each pin on the processor is connected with a bonding pad on the flash welding bit 10, and when the flash chip is mounted (the flash chip is welded on the flash welding bit 10), the corresponding pin of the flash chip is connected with the processor. In this embodiment, the power supply path of the flash memory chip is mainly improved, and the connection between the flash memory chip and the processor is in the prior art, which is not described in detail herein. In this embodiment, the electronic component includes a resistor.

In this embodiment, 2 power welding bits and 2 power welding bits are provided according to the power classification of the flash memory chip. As shown in fig. 2, includes a first power welding bit 31, a second power welding bit 32, a first power welding bit 41, and a second power welding bit 42; each welding position consists of 2 welding pads which are arranged side by side, and two ends of the corresponding electronic element are welded on the 2 welding pads, so that the electronic element can be mounted. In order to filter power supply so as to enable the power supply to work more stably, a first capacitor C1, a second capacitor C2 and a third capacitor C3 are arranged on the main board; the specific connection relation is as follows:

the first bonding pad of the first power supply bonding bit 31 is connected with the first bonding pad of the first power supply bonding bit 41, one end of the first capacitor C1 and the first group of power supply bonding pads of the flash memory bonding bit 10; the second bonding pad of the first power supply welding position 31 is connected with a first power supply end, the second bonding pad of the first power supply welding position 41 is connected with a voltage reduction module, the first bonding pad of the second power supply welding position 42 is connected with one end of a second capacitor C2 and a second group of power supply bonding pads of the flash memory welding position 10, the second bonding pad of the second power supply welding position 42 is connected with the voltage reduction module 20, the first bonding pad of the second power supply welding position 32 is connected with one end of a third capacitor C3 and a third group of power supply bonding pads of the flash memory welding position 10, and the second bonding pad of the second power supply welding position 32 is connected with a second power supply end; the other end of the first capacitor C1, the other end of the second capacitor C2 and the other end of the third capacitor C3 are all grounded.

Wherein the first group of power supply pads corresponds to 10 VCC pins (including VCC1 pin-VCC 10 pin), the second group of power supply pads corresponds to 8 VCCQ pins (including VCCQ_1 pin-VCCQ_8 pin) of the flash memory chip, and the third group of power supply pads corresponds to 8 VCCQ2 pins (including VCCQ2_1 pin-VCCQ2_8 pin) of the flash memory chip. When the motherboard is manufactured, each power supply welding position and each power supply welding position are connected with the corresponding power supply welding pad of the flash memory welding position 10, and the upper part (namely, the electronic element is welded on the corresponding welding position) is selected according to the requirement of a user, namely, the welding resistance is selected. The first capacitor C1 (preferably 10 uF), the second capacitor C2 (preferably 4.7 uF) and the third capacitor C3 (preferably 10 uF) are used for filtering the connected voltage. In the implementation, 3 capacitors can be connected in parallel to each capacitor, that is, the VCC pin, the VCCQ pin, and the VCCQ2 pin are grounded through 4 capacitors, and specifically, as shown in fig. 2, the number of capacitors is increased to increase the filtering effect.

Referring to fig. 3 together, when a first flash memory chip (i.e. a flash memory chip adopting UFS2.1 standard) is soldered on the flash memory soldering bit 10, a first resistor R1 is soldered on the first power supply soldering bit 31, a second resistor R2 is soldered on the second power supply soldering bit 32, two ends of the two resistors are soldered on the first bonding pad and the second bonding pad of the paired power supply soldering bit respectively, the circuit layout is as shown in fig. 7, and only the positions of some important elements related to the embodiment on the motherboard are shown in fig. 7, which is only an example herein, and the layout can be laid out according to the requirements in specific implementation; other existing components on the motherboard are not described in detail herein.

The method comprises the following steps: one end of the first resistor R1 is connected to each VCC pin (including VCC1 pin to VCC10 pin) of the first flash memory chip UFS2.1 and one end of the first capacitor C1, the other end of the first resistor R1 is connected to the first power supply end, one end of the second resistor R2 is connected to one end of the third capacitor C3 and each VCCQ2 pin (including vccq2_1 pin to vccq2_8 pin) of the first flash memory chip UFS2.1, the other end of the second resistor R2 is connected to the second power supply end, and each VCCQ pin (including vccq_1 pin to vccq_8 pin) of the first flash memory chip UFS2.1 is suspended.

The resistances of the first resistor R1 and the second resistor R2 are preferably 0Ω, which is equivalent to a wire, and the first supply voltage +v3p3sx of 3.3v and the second supply voltage +v1p8sx of 1.8v required by the flash memory chip of UFS2.1 standard are transmitted to supply power to the first flash memory chip. At this time, the first power welding bit 41 and the second power welding bit 42 have no upper parts, and the third power supply voltage +v2p5s_ufs of 2.5V and the fourth power supply voltage +v1p2s_ufs of 1.2V are not input, so that the normal operation of the first flash memory chip is not affected.

Referring to fig. 4 together, when a second flash memory chip (i.e. a flash memory chip adopting UFS3.1 standard) is soldered on the flash memory soldering bit 10, a third resistor R3 is soldered on the first power soldering bit 41, a fourth resistor R4 is soldered on the second power soldering bit 42, two ends of the two resistors are soldered on the first bonding pad and the second bonding pad of the paired power soldering bit respectively, the circuit layout is as shown in fig. 8, and only the positions of the relevant part of the important elements on the main board are shown in fig. 8, which is only an example herein, and the layout can be according to the requirements in specific implementation; other existing components on the motherboard are not described in detail herein.

The method comprises the following steps: one end of the third resistor R3 is connected to each VCC pin (including VCC1 pin to VCC10 pin) of the second flash memory chip UFS3.1 and one end of the first capacitor C1, the other end of the third resistor R3 is connected to the third power supply end of the voltage reducing module, one end of the fourth resistor R4 is connected to one end of the third capacitor C3 and each VCCQ pin (including vccq_1 pin to vccq_8 pin) of the second flash memory chip UFS3.1, the other end of the fourth resistor R4 is connected to the fourth power supply end of the voltage reducing module, and each VCCQ2 pin (including vccq2_1 pin to vccq2_8 pin) of the second flash memory chip UFS3.1 is suspended.

The resistances of the third resistor R3 and the fourth resistor R4 are preferably 0Ω, which is equivalent to a wire, and the third supply voltage +v2p5s_ufs of 2.5V and the fourth supply voltage +v1p2s_ufs of 1.2V required by the flash memory chip of UFS3.1 standard are transmitted to the second flash memory chip to supply power. Third supply voltage

The +v2p5s_ufs and the fourth supply voltage +v1p2s_ufs are generated by the step-down module. At this time, the first power supply welding bit 31 and the second power supply welding bit 32 have no upper parts, so that the first power supply voltage +v3p3sx and the second power supply voltage +v1p8sx have no input, and the normal operation of the second flash memory chip is not affected.

Referring to fig. 5, the voltage reducing module 20 includes a first voltage reducing unit 21 and a second voltage reducing unit 22, wherein the first voltage reducing unit 21 is connected to the second pad of the first power welding position 41, and the second voltage reducing unit 22 is connected to the second pad of the second power welding position 42. The first step-down unit 21 is configured to step down the first supply voltage +v3p3sx of 3.3v to a third supply voltage +v2p5s_ufs of 2.5V and output the third supply voltage +v2p8sx to supply power to the second flash memory chip, and the second step-down unit 22 is configured to step down the second supply voltage +v1p8sx of 1.8v to a fourth supply voltage +v1p2s_ufs of 1.2V and output the fourth supply voltage +v1p2s_ufs to supply power to the second flash memory chip. The third supply voltage +v2p5s_ufs and the fourth supply voltage +v1p2s_ufs are used to meet the power supply requirements of the flash memory chip of UFS3.1 standard.

The first step-down unit 21 includes a first step-down chip U1, a fifth resistor R5, and a sixth resistor R6; the VIN pin of the first buck chip U1 inputs a first supply voltage +v3p3sx, the EN pin of the first buck chip U1 inputs an enable signal slp_s3_n (provided by the processor), the BIAS pin of the first buck chip U1 inputs a fifth supply voltage +v5p0a, and the GND pin of the first buck chip U1 is grounded; the VOUT pin of the first buck chip U1 is a third power supply end of the buck module and is connected with one end of a fifth resistor R5; the ADJ pin of the first buck chip U1 is connected to the other end of the fifth resistor R5 and one end of the sixth resistor R6, and the other end of the sixth resistor R6 is grounded.

The model of the first buck chip U1 is preferably SGM2051-ADJXG, the resistance value of the fifth resistor R5 is preferably 40.2kΩ, and the resistance value of the sixth resistor R6 is preferably 10kΩ. The voltage value calculation formula of the third power supply voltage +v2p5s_ufs output on the VOUT pin of the first buck chip U1 is:

vout 1=vfb1× (1+r5/R6) =0.5 v× (1+40.2/10) =2.51V, and the third supply voltage is approximately equal to 2.5V.

Preferably, the first step-down unit 21 further includes a fourth capacitor C4 (preferably 4.7 uF), a fifth capacitor C5 (preferably 0.1 uF), a sixth capacitor C6 (preferably 2.2 uF), a seventh capacitor C7 (preferably 0.01 uF), and an eighth capacitor C8 (preferably 10 uF); the fourth capacitor C4 is connected between the VIN pin of the first buck chip U1 and ground, the fifth capacitor C5 is connected between the EN pin of the first buck chip U1 and ground, the sixth capacitor C6 is connected between the BIAS pin of the first buck chip U1 and ground, the seventh capacitor C7 is connected in parallel with the fifth resistor R5, and the eighth capacitor C8 is connected between the VOUT pin of the first buck chip U1 and ground. These capacitors are used for filtering to make the signal on the connected pins more stable.

Preferably, the first voltage reducing unit 21 further includes a seventh resistor R7 and an eighth resistor R8, wherein one end of the seventh resistor R7 is connected to the EN pin of the first voltage reducing chip U1, the other end of the seventh resistor R7 is input with the enable signal slp_s3_n, one end of the eighth resistor R8 is connected to the BIAS pin of the first voltage reducing chip U1, and the other end of the eighth resistor R8 is input with the fifth power supply voltage +v5p0a. These two resistors are used for current limiting to protect the connected pins.

Referring to fig. 6, the second voltage reducing unit 22 includes a second voltage reducing chip U2, a ninth resistor R9, and a tenth resistor R10; the VIN pin of the second buck chip U2 inputs a second supply voltage +v1p8sx, the EN pin of the second buck chip U2 inputs an enable signal slp_s3_n (provided by the processor), the BIAS pin of the second buck chip U2 inputs a fifth supply voltage +v5p0a, and the GND pin of the second buck chip U2 is grounded; the VOUT pin of the second buck chip U2 is a fourth power supply end of the buck module and is connected with one end of a ninth resistor R9; the ADJ pin of the second buck chip U2 is connected to the other end of the ninth resistor R9 and one end of the tenth resistor R10, and the other end of the tenth resistor R10 is grounded.

The model of the second buck chip U2 is preferably SGM2051-ADJXG, the resistance value of the ninth resistor R9 is preferably 14kΩ, and the resistance value of the tenth resistor R10 is preferably 10kΩ. The voltage value calculation formula of the fourth power supply voltage +v1p2s_ufs output on the VOUT pin of the second buck chip U2 is:

vout 2=vfb2× (1+r9/r10) =0.5 v× (1+14/10) =1.2V, and the third supply voltage is equal to 1.2V.

Preferably, the second voltage reducing unit 22 further includes a ninth capacitor C9 (preferably 4.7 uF), a tenth capacitor C10 (preferably 0.1 uF), an eleventh capacitor C11 (preferably 2.2 uF), a twelfth capacitor C12 (preferably 0.01 uF), a thirteenth capacitor C13 (preferably 10 uF), an eleventh resistor R11, and a twelfth resistor R12; the specific connection and function are similar to those of the first voltage reducing unit 21, and are shown in fig. 6, which is not described in detail herein.

Since the power supply voltages output by the two step-down chips are only useful when the second flash memory chip (i.e. the flash memory chip adopting the UFS3.1 standard) is soldered, in this embodiment, although the two step-down chips are soldered on the motherboard, when the flash memory chip adopting the UFS2.1 standard is used, R3 and R4 have no upper parts, and the third power supply voltage +v2p5s_ufs and the fourth power supply voltage +v1p2s_ufs will not be input to cause an influence. In order to avoid the waste of output energy consumption of the buck chips, a first buck welding position and a second buck welding position can be arranged on the main board, when the flash memory chip of the UFS2.1 standard is used, two buck chips are not mounted, and when the flash memory chip of the UFS3.1 standard is used, two buck chips are mounted (welded on the corresponding buck welding positions). As shown in FIG. 7, the dashed boxes indicate that U1 and U2 can be added or not added, and the addition of the components can reduce subsequent operations and avoid electric energy waste.

In summary, according to the motherboard and the terminal device compatible with the flash memory chips of different standards, the required electronic elements are welded on the corresponding welding positions according to the standards of the flash memory chips of the upper part, so that power supply paths required by the different flash memory chips are formed, and the power supply requirements of the different standards are met; by setting the welding position, the power supply path on the main board can be changed by modifying the BOM (corresponding resistor and flash memory chip) under the condition of not changing the layout of the main board, so that the compatibility of the flash memory chips with different standards is realized on one main board, one main board is not required to be designed for each standard, and the research and development cost and the manufacturing cost of the main board are saved; the flash memory chip compatible with the main board can be switched at will according to the requirements of users, the welding mode is simple and easy to operate, and the use of users is convenient.

The above embodiments are only for illustrating the technical solution of the present utility model, and are not limiting; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present utility model.

Claims

1. The main board compatible with the flash memory chips with different standards comprises a main board body, wherein a power module for outputting a first power supply voltage and a second power supply voltage is arranged on the main board body; the flash memory welding bit is connected with each power supply welding bit and each power supply welding bit, and the voltage reduction module is connected with each power supply welding bit;

2. The motherboard compatible with flash memory chips of different standards according to claim 1, wherein the motherboard body is provided with a first power supply welding position, a second power supply welding position, a first capacitor, a second capacitor and a third capacitor;

3. The motherboard of a flash memory chip compatible with different standards of claim 2, wherein the first set of power supply pads comprises 10 VCC pins of the flash memory chip, the second set of power supply pads comprises 8 VCCQ pins of the flash memory chip, and the third set of power supply pads comprises 8 VCCQ2 pins of the flash memory chip.

4. The motherboard compatible with different standards of flash memory chips as recited in claim 3, wherein said flash memory soldering bit is soldered with a first flash memory chip, a first power supply soldering bit is soldered with a first resistor, and a second power supply soldering bit is soldered with a second resistor;

5. The motherboard compatible with different standards of flash memory chips as recited in claim 3, wherein a second flash memory chip is soldered on said flash memory soldering bit, a third resistor is soldered on said first power soldering bit, and a fourth resistor is soldered on said second power soldering bit;

6. The motherboard compatible with different standards of flash memory chips of claim 5 wherein said buck module includes a first buck unit and a second buck unit, said first buck unit being connected to a second pad of a first power supply bond site, said second buck unit being connected to a second pad of a second power supply bond site;

7. The motherboard compatible with different standards of flash memory chips as recited in claim 6 wherein said first buck unit comprises a first buck chip, a fifth resistor and a sixth resistor;

8. The motherboard of a flash memory chip compatible with different standards according to claim 7, wherein the first step-down unit further comprises a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor;

9. The motherboard compatible with different standards of flash memory chips of claim 8 wherein said first buck unit further comprises a seventh resistor and an eighth resistor;

10. A terminal device comprising a housing, wherein a motherboard compatible with flash memory chips of different standards according to any one of claims 1-9 is provided in the housing.