CN219929628U

CN219929628U - Packaging structure

Info

Publication number: CN219929628U
Application number: CN202321570891.5U
Authority: CN
Inventors: 雷永庆; 向兴林; 冯军
Original assignee: Mestar Microelectronics Shenzhen Co ltd
Current assignee: Mestar Microelectronics Shenzhen Co ltd
Priority date: 2023-06-19
Filing date: 2023-06-19
Publication date: 2023-10-31
Anticipated expiration: 2033-06-19

Abstract

The present utility model provides a package structure including: the semiconductor package comprises a substrate, a first chip, a second chip, a heat conduction component area, a fixing piece and a package body, wherein the first chip is positioned on the upper surface of the substrate and is electrically connected with the substrate; the second chip is positioned on the upper surface of the first chip and is electrically connected with the first chip; the second chip is provided with at least one heat conducting component area, the heat conducting component area comprises a plurality of heat conducting holes penetrating through the second chip at least, the heat conducting holes are filled with a plurality of heat conducting components, and the first chip and the second chip are fixedly connected through the heat conducting components; the fixing piece is positioned on the upper surface of the heat conduction component and is contacted with the upper surface of the second chip. According to the utility model, the plurality of heat conduction holes penetrating the second chip and the bottom surface of the heat conduction part is exposed out of the first chip, and the heat conduction part with the heat conductivity not smaller than that of the second chip is filled in the heat conduction holes, so that the heat conduction part fixedly connects the first chip with the second chip, the heat conduction path of the packaging structure is shortened, and the heat conduction efficiency of the packaging structure is enhanced.

Description

Packaging structure

Technical Field

The present utility model relates to the field of microelectromechanical systems, and in particular, to a packaging structure.

Background

Microelectromechanical systems (Micro-Electro-Mechanical System, MEMS for short) technology is a technology in the high-tech field based on microelectronics and micromachining technologies, and mechanical components, driving components, electrical control systems, digital processing systems, etc. can be integrated into a single Micro unit. The development of MEMS technology opens up a brand new technical field and industry, and the micro sensor, micro actuator, micro component, micro mechanical optical device, vacuum micro electronic device, power electronic device and other devices manufactured by MEMS technology have the advantages of microminiature, intelligence, executable, integrability, good process compatibility, low cost and the like, and have very wide application prospect in the fields of aviation, aerospace, automobile, biomedicine, environmental monitoring, military, internet of things and the like.

Microelectromechanical systems are the integration of microcircuits and micromachines on a chip as required by functionality, typically on the order of millimeters or micrometers in size. In general, the circuit portion is often designed on a control chip, and the micromechanical structure is designed on a device chip, which is coupled to the control chip.

The chip is a Die before being unpackaged, the Die is a small piece cut from a silicon Wafer (Wafer) after a certain process is finished, the Die is also called Die in the chip industry, and each Die is an independent functional chip, and when the Die is not packaged, the Die cannot be directly used because no pins and cooling fins exist.

Packaging (Package) refers to wrapping and sealing objects, and in integrated circuits, refers to fixing dies (Die) onto a receiving substrate, and simultaneously completing some connections and leading out pins, so as to Package a complete chip.

The main purpose of the chip packaging is to protect the chip and ensure that the chip after packaging should meet the electrical connection between the internal circuit of the integrated circuit chip and an external system; and secondly, the fixing and sealing functions are realized, a long-term stable and reliable working environment is provided for the chip, the electrothermal performance of the chip can be enhanced, and the high stability and reliability of the normal operation of the chip are ensured.

In the existing packaging technology, the die-to-die is integrally packaged by stacking, and is bonded or Flip Chip bonded (Flip Chip). In the conventional stack packaging technology, heat conduction between stacked dies depends on mutual contact between the dies, and heat conduction efficiency is not high, please refer to fig. 1, which is a schematic structural diagram of a first chip 01 and a second chip 02. In addition, the stacked package structure using bonding or flip chip bonding technology has an intermediate medium between the dies, which increases the heat conduction path and further reduces the heat conduction efficiency, thereby causing uneven temperature between the dies and affecting the performance of the packaged chip.

In view of this, there is an urgent need for a package structure having a short heat transfer path and high heat transfer efficiency.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present utility model is to provide a package structure for solving the problems of long heat transfer path and low heat transfer efficiency between stacked chips in the prior art.

To achieve the above and other related objects, the present utility model provides a package structure, comprising:

a substrate;

the first chip is positioned on the upper surface of the substrate and is electrically connected with the substrate;

the second chip is positioned on the upper surface of the first chip and is electrically connected with the first chip;

the heat conducting component area comprises a plurality of heat conducting holes penetrating through at least the second chip, the heat conducting holes are filled with a plurality of heat conducting components, and the first chip and the second chip are fixedly connected through the heat conducting components;

the fixing piece is positioned on the upper surface of the heat conduction component and is contacted with the upper surface of the second chip;

and the packaging body at least wraps the first chip, the second chip and the exposed surface of the fixing piece.

Optionally, a plurality of the heat conduction holes are arranged in an array in the heat conduction component area.

Alternatively, the shape of the heat conductive member includes a cylindrical shape and a square column shape.

Alternatively, the cross-sectional dimension of the heat conductive member ranges from 20 μm to 60 μm.

Optionally, the thermal conductivity of the thermally conductive member is not less than the second chip.

Optionally, the first chip is an IC chip.

Optionally, the second chip is a MEMS chip.

Optionally, the package further covers an upper surface of the substrate.

Optionally, the heat conducting component is fixedly connected to the upper surface of the first chip.

Optionally, the size of the first chip is not smaller than the size of the second chip.

As described above, the package structure of the present utility model has the following beneficial effects: the heat conducting component area of the second chip is provided with a plurality of heat conducting holes penetrating through the second chip and the bottom surface of the heat conducting component area of the second chip is exposed out of the heat conducting holes, and the heat conducting holes are filled with heat conducting components with heat conductivity not smaller than that of the second chip.

Drawings

Fig. 1 is a schematic structural diagram of a first chip and a second chip in the prior art.

Fig. 2 is a schematic structural diagram of a package structure according to the present utility model.

Fig. 3 is a schematic structural view of a part of the package structure of the present utility model.

Fig. 4 is a schematic structural view of a portion of the package structure of the present utility model.

Fig. 5 is a schematic diagram showing an arrangement of heat conduction holes of the package structure of the present utility model.

Fig. 6 is a schematic view showing another arrangement of heat conduction holes of the package structure of the present utility model.

Description of element reference numerals

01. First chip

02. Second chip

1. Substrate board

2. First chip

3. Second chip

4. Heat conducting component area

41. Heat conduction hole

5. Fixing piece

6. Package body

7. Heat conducting component

Detailed Description

Further advantages and effects of the present utility model will become apparent to those skilled in the art from the disclosure of the present utility model, which is described by the following specific examples.

Please refer to fig. 2 to fig. 6. It should be understood that the structures, proportions, sizes, etc. shown in the drawings are for illustration purposes only and should not be construed as limiting the utility model to the extent that it can be practiced, since modifications, changes in the proportions, or otherwise, used in the practice of the utility model, are not intended to be critical to the essential characteristics of the utility model, but are intended to fall within the spirit and scope of the utility model. Also, the terms such as "upper," "lower," "left," "right," "middle," and "a" and the like recited in the present specification are merely for descriptive purposes and are not intended to limit the scope of the utility model, but are intended to provide relative positional changes or modifications without materially altering the technical context in which the utility model may be practiced.

Example 1

The utility model provides a packaging structure, as shown in fig. 2, which is a schematic diagram of the packaging structure, and the packaging structure comprises: the semiconductor package comprises a substrate 1, a first chip 2, a second chip 3, a heat conducting component area 4, a fixing piece 5 and a package body 6, wherein the first chip 2 is positioned on the upper surface of the substrate 1 and is electrically connected with the substrate 1; the second chip 3 is arranged on the upper surface of the first chip 2 and is electrically connected with the second chip 3; at least one heat conducting component area 4 is arranged in the packaging structure, the heat conducting component area 4 comprises a plurality of heat conducting holes 41 penetrating through at least the second chip 3, the heat conducting holes 41 are filled with a plurality of heat conducting components 7, and the first chip 2 and the second chip 3 are fixedly connected through the heat conducting components 7; the fixing piece 5 is positioned on the upper surface of the heat conduction component 7 and is contacted with the upper surface of the second chip 3; the package 6 wraps at least the exposed surfaces of the first chip 2, the second chip 3 and the fixing member 5.

Specifically, in the case of satisfying the performance of the package structure, the material, shape and size of the substrate 1 may be selected according to the actual situation, which is not limited herein.

Specifically, pins are disposed on the substrate 1, and are used for communicating the packaging structure with an external circuit.

As an example, the first chip 2 is an IC (semiconductor integrated circuit) chip.

Specifically, in the case of meeting the performance of the package structure, the material and shape of the first chip 2 may be selected according to the actual situation, which is not limited herein.

As an example, the second chip 3 is a MEMS chip.

Specifically, in the case of meeting the performance of the package structure, the material and shape of the second chip 3 may be selected according to the actual situation, which is not limited herein.

In particular, the micromechanical structure arranged in the second chip 3 comprises a resonator body, a beam, an arm, an electrostatic motor or other suitable micromechanical structure. In this embodiment, the micromechanical structure configured in the second chip 3 is a resonator, i.e. the second chip 3 is a MEMS resonator chip.

As an example, the size of the first chip 2 is not smaller than the size of the second chip 3. For example, as shown in fig. 3, which is a schematic structural view of a part of the structure of the package structure, the size of the first chip 2 is larger than the size of the second chip 3, that is, the width of the first chip 2 is larger than the width of the second chip 3, and the length of the first chip 2 is larger than the length of the second chip 3; as shown in fig. 4, which is another schematic structural view of a part of the structure of the package structure, the size of the first chip 2 is equal to the size of the second chip 3, that is, the width of the first chip 2 is consistent with the width of the second chip 3, and the length of the first chip 2 is consistent with the length of the second chip 3.

As an example, as shown in fig. 5 to 6, one arrangement schematic view of the heat conducting holes 41 and another arrangement schematic view of the heat conducting holes 41 are respectively shown, and a plurality of the heat conducting holes 41 are arranged in an array in the heat conducting component area 4.

Specifically, in the case of satisfying the performance of the package structure, the number and the position of the heat conductive member regions 4 may be selected according to the actual situation, which is not limited herein.

Specifically, in the case of satisfying the performance of the package structure and the connection strength between the first chip 2 and the second chip 3, the array arrangement manner and the number of the heat conduction holes 41 in each of the heat conduction member areas 4 may be selected according to the actual situation, which is not limited herein.

As an example, the cross-sectional dimension of the heat conductive member 7 ranges from 20 μm to 60 μm.

As an example, the shape of the heat conductive member 7 includes a cylindrical shape, a square column shape, or other suitable shape.

As an example, the thermal conductivity of the thermally conductive member 7 is not less than that of the second chip 3.

Specifically, the material of the heat conducting member 7 includes Si, alN, al ₂ O ₃ At least one of Au, ag, cu may be other suitable thermally conductive materials.

As an example, the heat conductive member 7 is fixedly attached to the upper surface of the first chip 2.

Specifically, the heat conducting member 7 is fixedly connected to the upper surface of the first chip 2 through a bonding process.

Specifically, the bonding process of the lower surface of the heat conducting member 7 and the upper surface of the first chip 2 includes a eutectic bonding process or other suitable bonding process.

Specifically, the method for forming the heat conducting component 7 fixedly connected to the upper surface of the first chip 2 further includes direct etching forming under the condition that the performance of the package structure is satisfied.

Specifically, the heat conducting component 7 is directly etched and formed on the first chip 2 by adopting a wet etching process, so as to obtain the heat conducting component 7 fixedly connected with the upper surface of the first chip 2.

In particular, the fixing element 5 comprises glue or other suitable fixing material.

Specifically, the fixing element 5 is disposed on top of the heat conducting member 7, so that the heat conducting member 7 may be fixed on the second chip 3.

Specifically, the material and the size of the fixing member 5 may be selected according to the actual situation, and are not limited in this regard, as long as the fixing member 7 can be fixed to the second chip 3.

Specifically, the heat conduction hole 41 penetrating through the second chip 3 is formed in the heat conduction component area 4, and the heat conduction component 7 with the heat conductivity not smaller than that of the second chip 3 is filled in the heat conduction hole 41, the first chip 2 and the second chip 3 are fixedly connected through the heat conduction component 7, that is, no intermediate medium exists between the first chip 2 and the second chip 3, so that poor heat conduction efficiency between the first chip 2 and the second chip 3 caused by existence of the intermediate medium is avoided, the upper surface of the first chip 2 is in direct contact with the lower surface of the second chip 3, a heat transfer path is shortened, and the heat transfer efficiency of the packaging structure is enhanced.

Specifically, the heat conducting component 7 is embedded in the second chip 3, the bottom surface of the heat conducting component is in contact with the upper surface of the first chip 2, heat can be quickly transferred to the central structure of the packaging structure, the temperature of the first chip 2 and the temperature of the second chip 3 reach balance, and the high stability and the reliability of normal operation of the packaging structure are ensured.

Specifically, the package body 6 includes at least one of epoxy packaging glue, organic silicon packaging glue, polyurethane packaging glue, and ultraviolet light curing packaging glue, and may be other suitable packaging materials.

As an example, the package 6 also covers the upper surface of the substrate 1.

Specifically, in the case where the performance of the package structure is satisfied, the shape of the package body 6 may be selected according to the actual situation, and is not limited herein.

According to the packaging structure of the embodiment, the heat conducting component 7 is fixed on the second chip 3 through the fixing piece 5, and the plurality of heat conducting holes 41 penetrating through the second chip 3 and the bottom surface of the heat conducting component area 4 of the second chip 3 is provided to expose the first chip 2, the heat conducting holes 41 are filled with the heat conducting component 7 with the heat conductivity not smaller than that of the second chip 3, the heat conducting component 7 is fixedly connected with the first chip 2 and the second chip 3, namely, no intermediate medium exists between the first chip 2 and the second chip 3, the heat conducting efficiency difference between the first chip 2 and the second chip 3 caused by the existence of the intermediate medium is avoided, the heat conducting path of the packaging structure is shortened, the heat conducting efficiency between the first chip 2 and the second chip 3 is enhanced, in addition, the heat conducting component 7 is embedded in the second chip 3, the heat conducting efficiency between the first chip 2 and the second chip 3 is accelerated, and the heat conducting efficiency between the first chip 2 and the second chip 3 is guaranteed to reach the normal stability.

In summary, the package structure of the present utility model sets the plurality of heat conduction holes penetrating the second chip and having the bottom surface exposing the first chip in the heat conduction part region of the second chip, and fills the heat conduction part having a heat conductivity not smaller than that of the second chip in the heat conduction hole, the heat conduction part is fixed on the second chip through the fixing piece, the first chip and the second chip are fixedly connected through the heat conduction part, and no intermediate medium exists between the first chip and the second chip, so that the heat conduction efficiency difference between the first chip and the second chip caused by the existence of the intermediate medium is avoided, the upper surface of the first chip is directly contacted with the lower surface of the second chip, the heat conduction path of the package structure is shortened, the heat conduction efficiency between the first chip and the second chip is enhanced, in addition, the heat conduction part is embedded in the second chip and fixedly connected with the upper surface of the first chip, the heat can be quickly transferred to the central structure of the package structure, the temperature balance between the first chip and the second chip is accelerated, and the high stability and reliability of the normal operation of the package structure are ensured. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present utility model and its effectiveness, and are not intended to limit the utility model. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the utility model. Accordingly, it is intended that all equivalent modifications and variations of the utility model be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A package structure, comprising:

a substrate;

2. The package structure of claim 1, wherein: the plurality of heat conduction holes are arranged in the heat conduction component area in an array mode.

3. The package structure of claim 1, wherein: the shape of the heat conduction component comprises a cylinder shape and a square column shape.

4. The package structure of claim 1, wherein: the cross-sectional dimension of the heat conductive member ranges from 20 μm to 60 μm.

5. The package structure of claim 1, wherein: the thermal conductivity of the heat conduction member is not smaller than that of the second chip.

6. The package structure of claim 1, wherein: the first chip is an IC chip.

7. The package structure of claim 1, wherein: the second chip is a MEMS chip.

8. The package structure of claim 1, wherein: the package also covers the upper surface of the substrate.

9. The package structure of claim 1, wherein: the heat conduction component is fixedly connected to the upper surface of the first chip.

10. The package structure of claim 1, wherein: the size of the first chip is not smaller than the size of the second chip.