CN219892180U

CN219892180U - SPI NAND flash memory storage system

Info

Publication number: CN219892180U
Application number: CN202321107466.2U
Authority: CN
Inventors: 黎江南; 刘焱
Original assignee: Lianhe Storage Technology Jiangsu Co ltd
Current assignee: Lianhe Storage Technology Jiangsu Co ltd
Priority date: 2023-05-10
Filing date: 2023-05-10
Publication date: 2023-10-24
Anticipated expiration: 2033-05-10

Abstract

The utility model relates to the technical field of semiconductor memories, in particular to an SPI NAND flash memory system. The SPI NAND flash memory system includes: NAND flash memory chip, SPI chip, lead frame carrier and seal; the lead frame carrier comprises a carrying sheet area positioned in the middle part and a pin area positioned at the periphery of the carrying sheet area, and a plurality of frame pins are arranged in the frame pin area; the NAND flash memory chip is adhered to the front surface of the slide area through a first adhesive layer; the SPI chip is adhered to the front surface of the NAND flash memory chip through a second adhesive layer; the NAND flash memory chip is connected with the SPI chip through a plurality of first leads, and the SPI chip is correspondingly connected with the frame pin through a plurality of second leads; the NAND flash memory chip, the SPI chip, the lead frame carrier, the first lead and the second lead are packaged in the bonding layer. The SPI NAND flash memory system provided by the utility model can solve the data problem in the related technology.

Description

SPI NAND flash memory storage system

Technical Field

The utility model relates to the technical field of semiconductor memories, in particular to an SPI NAND flash memory system.

Background

The NAND flash memory device is suitable for storing a large amount of data due to the performance advantages of low cost, large capacity, high rewriting speed and the like, and is widely applied in the industry, such as digital cameras, MP3 walkman memory cards, small-sized U discs and the like.

In the related art, the interface type of the NAND flash memory bare chip is usually a parallel interface, and the NAND flash memory with the structure has interference among channels when data transmission is performed, so that the data transmission speed is limited, and the NAND flash memory with the structure has more pins, so that the product area after the NAND flash memory with the structure and a control chip are sealed is larger, the length and the number of communication wires are increased, and the data transmission speed is further limited.

Disclosure of Invention

The utility model provides an SPI NAND flash memory system which can solve the problem of data in the related technology.

In order to solve the technical problems described in the background art, the present utility model provides an SPI NAND flash memory storage system, comprising: NAND flash memory chip, SPI chip, lead frame carrier and seal;

the lead frame carrier comprises a carrying sheet area positioned in the middle part and a pin area positioned at the periphery of the carrying sheet area, and a plurality of frame pins are arranged in the frame pin area;

the NAND flash memory chip is adhered to the front surface of the slide area through a first adhesive layer;

the SPI chip is adhered to the front surface of the NAND flash memory chip through a second adhesive layer;

the NAND flash memory chip is connected with the SPI chip through a plurality of first leads, and the SPI chip is correspondingly connected with the frame pin through a plurality of second leads;

the NAND flash memory chip, the SPI chip, the lead frame carrier, the first lead and the second lead are packaged in the bonding layer.

Optionally, the frame pin includes a welding area, and a sealing fixing structure is arranged at one side of the welding area;

the sealing and fixing structure comprises an upper fixing piece extending from one side of the welding area and a lower fixing piece arranged opposite to the upper fixing piece;

a sealing fixing hole is formed in the upper fixing piece, and a fixing gap is formed between the upper fixing piece and the lower fixing piece;

and the sealing material forming the sealing layer fills the sealing fixing hole and the fixing gap.

Optionally, a particle region is formed on the surface of the lower fixing piece near the fixing slit, and a plurality of protrusion-shaped particles are formed in the particle region.

Optionally, a heat dissipation layer is formed on the back surface of the carrier region.

Optionally, the material of the heat dissipation layer includes metallic tin.

Optionally, the second lead has a higher crossover height than the first lead.

Optionally, a flash pin area is formed on the NAND flash memory chip, and an SPI pin area is formed on the SPI chip;

the SPI chip is arranged between one side of the NAND flash memory chip, on which the flash pin area is formed, and the center of the NAND flash memory chip.

Optionally, a side of the SPI chip where the SPI pin region is formed faces the flash pin region of the NAND flash chip.

Optionally, the first bonding layer includes a plurality of bonding areas, and adjacent bonding areas are spaced from each other.

Optionally, the second bonding layer includes a plurality of bonding areas, and adjacent bonding areas are spaced from each other.

The technical scheme of the utility model at least comprises the following advantages: through with the NAND flash memory chip through first adhesive linkage adhesion in the front of slide glass district, with SPI chip through the adhesion of second adhesive linkage in the front of NAND flash memory chip, the NAND flash memory chip passes through many first leads connection SPI chip, the SPI chip corresponds through many second leads and connects frame pin, NAND flash memory chip, SPI chip, lead frame carrier and first lead, second lead encapsulation in the seal that closes, can reduce the quantity of the pin of NAND flash memory chip into the quantity of frame pin, and can reduce the occupied area of device, shorten the wiring length between the chip to can improve communication rate.

Drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present utility model, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram illustrating a top view of an SPI NAND flash memory system according to one embodiment of the present utility model;

FIG. 2 shows a bottom view of FIG. 1;

FIG. 3 is a schematic bottom perspective view of portion A of FIG. 2;

FIG. 4 shows a schematic view of the B-B cross-sectional structure of FIG. 1;

fig. 5 is a schematic diagram illustrating a cross-sectional structure of an SPI NAND flash memory storage system according to another embodiment of the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the utility model are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

In the description of the present utility model, it should be noted that the directions or positional relationships indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. are based on the directions or positional relationships shown in the drawings, are merely for convenience of describing the present utility model and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a specific orientation, be configured and operated in a specific orientation, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

In the description of the present utility model, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; the two components can be directly connected or indirectly connected through an intermediate medium, or can be communicated inside the two components, or can be connected wirelessly or in a wired way. The specific meaning of the above terms in the present utility model will be understood in specific cases by those of ordinary skill in the art.

In addition, the technical features of the different embodiments of the present utility model described below may be combined with each other as long as they do not collide with each other.

Fig. 1 illustrates a schematic top view of an SPI NAND flash memory system according to an embodiment of the present utility model, fig. 2 illustrates a bottom view of fig. 1, fig. 3 illustrates a bottom perspective view of a portion a of fig. 2, fig. 4 illustrates a B-B cross-sectional view of fig. 1, and fig. 5 illustrates a cross-sectional view of an SPI NAND flash memory system according to another embodiment of the present utility model.

As can be seen in fig. 1 to 4, the SPI NAND flash memory system provided in the present embodiment includes a NAND flash memory chip 100, an SPI chip 200, a lead frame carrier 300, and a sealing layer 400.

The lead frame carrier 300 includes a carrier region 310 in the middle and a lead region 320 at the periphery of the carrier region 310, where nine frame pins are disposed in the frame lead region 320 in the embodiment shown in fig. 1, that is, four frame pins are sequentially, from top to bottom, a CS (Chip Select) pin, a DO (Digital Output) pin, a WP (Write Protect) pin, and a VSS (power ground) pin; the right side of the lead frame carrier 300 has four frame pins, namely, a VCC (power supply) pin, a HOLD (bus occupation request) pin, a CLK (clock) pin and a DI (Digital Iutput) pin from top to bottom in sequence; the underside of the leadframe carrier 300 has a pin that is connected to the VSS pin for ground.

Referring to fig. 4, the NAND flash memory chip 100 is adhered to the front surface of the carrier region 310 through a first adhesive layer 500.

With continued reference to fig. 4, spi chip 200 is adhered to the front side of NAND flash memory chip 100 by second adhesive layer 600.

The NAND flash memory chip 100 is connected to the SPI chip 200 through a plurality of first leads 700, and the SPI chip 200 is correspondingly connected to the frame pins through a plurality of second leads 800.

The NAND flash memory chip 100, the SPI chip 200, the lead frame carrier 300, and the first and second leads 700, 800 are collectively packaged in the encapsulation layer 400.

According to the embodiment, the NAND flash memory chip is adhered to the front face of the carrying area through the first adhesive layer, the SPI chip is adhered to the front face of the NAND flash memory chip through the second adhesive layer, the NAND flash memory chip is connected with the SPI chip through a plurality of first leads, the SPI chip is correspondingly connected with the frame pins through a plurality of second leads, the NAND flash memory chip, the SPI chip, the lead frame carrier, the first leads and the second leads are packaged in the sealing layer, the number of the pins of the NAND flash memory chip can be reduced to the number of the frame pins, the occupied area of devices can be reduced, the wiring length between the chips is shortened, and therefore the communication rate can be improved.

In addition, the firmness of the seal layer 400 also affects the communication quality of the device, and once the seal layer 400 shakes, the leads can be in contact with each other to interfere with communication, and even the connection point is peeled off. Referring to fig. 3, in order to improve the reliability of the encapsulation layer 400, the frame lead includes a bonding area 330, one side of the bonding area 330 is provided with an encapsulation fixing structure 340, the encapsulation fixing structure 340 includes an upper fixing piece 341 extending from one side of the bonding area 320, and a lower fixing piece 342 disposed opposite to the upper fixing piece 341, an encapsulation fixing hole 343 is formed in the upper fixing piece 341, and a fixing gap is formed between the upper fixing piece 341 and the lower fixing piece 342. When the sealing material is used for sealing, the sealing material flows to the lower fixing piece 342 through the sealing fixing hole 343 in the upper fixing piece 341, after the sealing material is solidified to form the sealing layer 400, the sealing material fills the sealing fixing hole 343 and the fixing gap, so that the sealing layer 400 is in an inverted T shape at the position of the sealing fixing hole 343, thereby strengthening the sealing layer 400, avoiding shaking and falling of the sealing layer 400, and being beneficial to maintaining the reliability of device communication.

In order to allow the sealing material flowing into the fixing slit to be firmly adhered to the lower fixing sheet 342, a particle region (not shown) is formed on the surface of the lower fixing sheet 342 adjacent to the fixing slit, and a plurality of protrusion-shaped particles are formed in the particle region, thereby improving the adhesion firmness between the sealing layer 400 and the lower fixing sheet 342 by increasing the contact area.

Referring to fig. 2 and 4, in order to improve the heat dissipation performance of the device, a heat dissipation layer 311 is formed on the back surface of the carrier region 310. Illustratively, the heat dissipation layer may be made of tin.

The bridge height h1 for the second wire 800 in the embodiment shown in fig. 1 is higher than the bridge height h2 for the first wire 700 to prevent communication interference between the second wire 800 and the first wire 700.

The flash pin area 110 is formed on the NAND flash memory chip 100, the SPI pin area 210 is formed on the SPI chip 200, the SPI chip 200 is disposed between the side of the NAND flash memory chip 100 where the flash pin area 110 is formed and the center W of the NAND flash memory chip 100, and the side of the SPI chip 200 where the SPI pin area 210 is formed faces the flash pin area 110 of the NAND flash memory chip 100 in order to further reduce the wiring length between chips to increase the communication rate.

Referring to fig. 5, a schematic diagram of a cross-sectional structure of an SPI NAND flash memory system according to another embodiment of the present utility model is shown. This embodiment is based on the embodiment shown in any one of fig. 1 to 4, in which the first adhesive layer 500 and the second adhesive layer 600 in the embodiment shown in fig. 5 include a plurality of adhesive areas, and the adhesive areas are spaced apart from each other. Since the adhesive materials used as the first adhesive layer 500 and the second adhesive layer 600 may generate a certain degree of strain under the influence of external environments such as temperature, the first adhesive layer 500 and the second adhesive layer 600 are separated into a plurality of spaced adhesive regions, so that the strain of the first adhesive layer 500 and the second adhesive layer 600 due to the environment can be reduced, and the problem that the NAND flash memory chip 100 or the SPI chip 200 is warped to influence the communication reliability is avoided.

It is apparent that the above examples are given by way of illustration only and are not limiting of the embodiments. Other variations or modifications of the above teachings will be apparent to those of ordinary skill in the art. It is not necessary here nor is it exhaustive of all embodiments. While still being apparent from variations or modifications that may be made by those skilled in the art are within the scope of the utility model.

Claims

1. An SPI NAND flash memory storage system, comprising: NAND flash memory chip, SPI chip, lead frame carrier and seal;

the lead frame carrier comprises a carrying sheet area positioned in the middle part and a pin area positioned at the periphery of the carrying sheet area, wherein a plurality of frame pins are arranged in the pin area;

2. The SPI NAND flash memory system of claim 1, wherein the frame pin includes a solder land, one side of the solder land being provided with a seal attachment structure;

3. The SPI NAND flash memory system of claim 2, wherein a pellet zone is formed on a surface of the lower stator adjacent to the fixing slit, the pellet zone having a plurality of protruding pellets formed therein.

4. The SPI NAND flash memory system of claim 1, wherein a heat sink layer is formed on a back surface of the carrier region.

5. The SPI NAND flash memory system of claim 4, wherein the heat sink layer material includes metallic tin.

6. The SPI NAND flash memory system of claim 1, wherein the second lead has a higher crossover height than the first lead.

7. The SPI NAND flash memory system of claim 1, wherein a flash pin zone is formed on the NAND flash memory chip and an SPI pin zone is formed on the SPI chip;

8. The SPI NAND flash memory system of claim 7, wherein the side of the SPI chip on which the SPI pin region is formed faces the flash pin region of the NAND flash memory chip.

9. The SPI NAND flash memory system of claim 1, wherein said first adhesive layer includes a plurality of adhesive areas, adjacent ones of said adhesive areas being spaced apart from one another.

10. The SPI NAND flash memory system of claim 1, wherein said second adhesive layer includes a plurality of adhesive areas, adjacent ones of said adhesive areas being spaced apart from one another.