CN219875724U - Receive diversity circuit and communication equipment - Google Patents

Abstract

The utility model discloses a receiving diversity circuit and a communication device. Each front-end circuit is used for receiving one path of radio frequency signal and converting the radio frequency signal into an intermediate frequency signal; the intermediate frequency processing circuits are connected with the front-end circuits in a one-to-one correspondence manner, and are used for processing the corresponding intermediate frequency signals to obtain corresponding modulation signals and field intensity signals; and the control circuit is connected with the intermediate frequency processing circuits and is used for carrying out weighting processing on the multipath modulation signals and the field intensity signals to obtain received signals so as to realize multipath diversity reception of the signals. By the mode, the utility model can realize the receiving diversity of the signals and can improve the sensitivity of the diversity.

Description

Receive diversity circuit and communication equipment

Technical Field

The present utility model relates to the field of electronic technologies, and in particular, to a receive diversity circuit and a communication device.

Background

The cluster system is a high-efficiency, multifunctional and high-capacity advanced wireless dispatching communication system, which is a communication system combining a wireless dispatching system of special service with a wire switching technology, a computer technology and a large-scale integrated circuit, and a receiving diversity circuit in the cluster system receives and diversity multiple paths of signals.

Because the performance index of the receiving diversity circuit in the cluster system has important influence on the overall performance, the performance of the receiving diversity circuit directly influences the performance of the whole cluster system, the upper limit of the index of the post-stage circuit of the cluster system is determined, and the development of the receiving diversity circuit with good performance is a necessary requirement for improving the performance of the whole cluster system.

The existing receiving diversity circuit adopts SA616D intermediate frequency processing chips to realize multi-diversity, the scheme needs a large number of peripheral auxiliary circuits and chips, has high cost, occupies the space of a printed circuit board (Printed Circuit Board, PCB) with large area, needs to use laminated PCBs, has poor overall consistency and has lower diversity sensitivity.

Disclosure of Invention

The utility model provides a receiving diversity circuit and a communication device, which can realize the receiving diversity of signals and improve the sensitivity of diversity.

In order to solve the technical problems, the utility model adopts a technical scheme that: there is provided a receive diversity circuit comprising: each front-end circuit is used for receiving one path of radio frequency signal and converting the radio frequency signal into an intermediate frequency signal; the intermediate frequency processing circuits are connected with the front-end circuits in a one-to-one correspondence manner, and are used for processing the corresponding intermediate frequency signals to obtain corresponding modulation signals and field intensity signals; and the control circuit is connected with the intermediate frequency processing circuits and is used for carrying out weighting processing on the multipath modulation signals and the field intensity signals to obtain received signals so as to realize multipath diversity reception of the signals.

Wherein the receive diversity circuit further comprises: the shielding cover is arranged outside the front-end circuits and the intermediate frequency processing circuits and is used for increasing the anti-interference capacity of the front-end circuits and the intermediate frequency processing circuits.

Wherein the receive diversity circuit further comprises: and the frequency source is respectively connected with the intermediate frequency processing circuits and used for respectively providing external frequency signals for the intermediate frequency processing circuits.

Wherein the receive diversity circuit further comprises: the power divider is respectively connected with the frequency source and the intermediate frequency processing circuits, and is used for dividing an external frequency signal into a plurality of frequency sub-signals and respectively outputting the plurality of frequency sub-signals to the plurality of intermediate frequency processing circuits.

Wherein the frequency source comprises: the first oscillating circuit is respectively connected with the intermediate frequency processing circuits and is used for outputting external frequency signals; the phase-locked loop is connected with the first oscillating circuit and is used for receiving and controlling an external frequency signal of the first oscillating circuit and feeding the controlled external frequency signal back to the first oscillating circuit.

Wherein, intermediate frequency processing circuit includes: the signal processing circuit is connected with the front-end circuit and is used for processing the intermediate frequency signal to obtain a modulation signal and a field intensity signal; and the second oscillating circuit is connected with the signal processing circuit and is used for generating an internal frequency signal to the signal processing circuit.

The signal processing circuit comprises an AD9864 chip.

The plurality of intermediate frequency processing circuits comprise three intermediate frequency processing circuits, and the plurality of front-end circuits comprise three front-end circuits.

Wherein the receive diversity circuit further comprises: the receiving board is provided with a plurality of front-end circuits and a plurality of intermediate frequency processing circuits; the control circuit is arranged on the control board; a first terminal arranged on one side of the receiving plate close to the control plate; the second terminal is arranged on one side of the control board, close to the receiving board, and is connected with the first terminal, and the intermediate frequency processing circuit is connected with the control circuit through the first terminal and the second terminal.

In order to solve the technical problems, the utility model adopts another technical scheme that: there is provided a communication device including: the receive diversity circuit of any of the above.

Compared with the prior art, the utility model has the beneficial effects that: the receiving diversity circuit comprises a plurality of front-end circuits, a plurality of intermediate frequency processing circuits and a control circuit. Each front-end circuit is used for receiving one path of radio frequency signal and converting the radio frequency signal into an intermediate frequency signal; the intermediate frequency processing circuits are connected with the front-end circuits in a one-to-one correspondence manner, and are used for processing the corresponding intermediate frequency signals to obtain corresponding modulation signals and field intensity signals; and the control circuit is connected with the intermediate frequency processing circuits and is used for carrying out weighting processing on the multipath modulation signals and the field intensity signals to obtain received signals so as to realize multipath diversity reception of the signals. Through the mode, the multi-channel intermediate frequency signal processing circuit can process the multi-channel intermediate frequency signals to obtain the corresponding modulation signals and field intensity signals, other peripheral chips are not needed, the circuit structure is simple, the linearity accuracy of the modulation signals output by the intermediate frequency processing circuits is high, and the diversity sensitivity can be improved. And the control circuit is used for weighting the modulation signal and the field intensity signal, so that the receiving diversity of the signal can be realized. Therefore, the utility model can realize the receiving diversity of the signals and can improve the sensitivity of the diversity.

Drawings

For a clearer description of the technical solutions of the embodiments of the present utility model, the drawings that are needed in the description of the embodiments will be briefly introduced below, it being obvious that the drawings in the description below are only some embodiments of the present utility model, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art, wherein:

fig. 1 is a schematic diagram of a receive diversity circuit according to an embodiment of the utility model;

fig. 2 is a schematic diagram of another embodiment of a receive diversity circuit of the present utility model;

fig. 3 is a schematic diagram of a further embodiment of a receive diversity circuit according to the utility model;

fig. 4 is a schematic diagram of a further embodiment of a receive diversity circuit according to the utility model;

fig. 5 is a schematic diagram of a further embodiment of a receive diversity circuit according to the utility model;

fig. 6 is a schematic diagram of a further embodiment of a receive diversity circuit according to the utility model;

fig. 7 is a schematic diagram of a further embodiment of a receive diversity circuit according to the utility model;

FIG. 8 is a schematic diagram of a specific circuit configuration of the intermediate frequency processing circuit in the embodiment of FIG. 1;

fig. 9 is a schematic diagram of a portion of the circuit configuration of the receive diversity circuit of the embodiment of fig. 5;

fig. 10 is a schematic structural view of an embodiment of the communication device of the present utility model.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

In order to solve the above-mentioned problems, the present utility model first proposes a receive diversity circuit, as shown in fig. 1, fig. 1 is a schematic diagram of an embodiment of the receive diversity circuit of the present utility model, and the receive diversity circuit 1 of the present embodiment includes a plurality of front-end circuits 10, a plurality of intermediate frequency processing circuits 20 and a control circuit 30. Each front-end circuit 10 is configured to receive a radio frequency signal and convert the radio frequency signal into an intermediate frequency signal; the intermediate frequency processing circuits 20 are connected with the front-end circuits 10 in a one-to-one correspondence manner, and the intermediate frequency processing circuits 20 are used for processing corresponding intermediate frequency signals to obtain corresponding modulation signals and field intensity signals; the control circuit 30 is connected to the multiple intermediate frequency processing circuits 20, and is configured to perform weighting processing on multiple modulated signals and field strength signals to obtain a received signal, so as to implement multiple diversity reception of the signal.

In this way, the multiple intermediate frequency processing circuits 20 can process multiple intermediate frequency signals to obtain corresponding modulation signals and field intensity signals, no other peripheral chips are needed, the circuit structure is simple, the linearity accuracy of the modulation signals output by the intermediate frequency processing circuits 20 is high, and the sensitivity of diversity can be improved. And the control circuit 30 performs weighting processing on the modulated signal and the field strength signal, so that signal reception diversity can be realized. Therefore, the present embodiment can realize reception diversity of signals, and can improve sensitivity of diversity.

Further, each front-end circuit 10 receives a corresponding rf signal and outputs the rf signal to the corresponding if processing circuit 20, so that the consistency of multiple paths can be ensured, and independent operation of each path can be ensured. The method ensures that other paths can be used for receiving diversity continuously when any path or paths have problems, and improves the reliability of the receiving diversity circuit 1.

Optionally, as shown in fig. 1, the receive diversity circuit 1 further comprises a shield 40. The shielding case 40 is disposed outside the front-end circuits 10 and the intermediate frequency processing circuits 20, and is used for increasing the anti-interference capability of the front-end circuits 10 and the intermediate frequency processing circuits 20 to improve the communication quality.

The shield case 40 is disposed outside the front-end circuits 10 and the intermediate frequency processing circuits 20, and can strengthen upper isolation between the front-end circuits 10 and the intermediate frequency processing circuits 20 and other circuits, prevent possible interference problems, and improve the interference resistance between the paths of the receive diversity circuit 1. And can also increase aluminum hull apron and cover simultaneously and establish outside a plurality of front-end circuits 10 and a plurality of intermediate frequency processing circuit 20, shield cover 40 and aluminum hull apron carry out double-shielded to a plurality of front-end circuits 10 and a plurality of intermediate frequency processing circuit 20, can further improve the interference killing feature of receiving diversity circuit 1.

In other embodiments, a shielding case can be separately provided for each path of front-end circuit and intermediate frequency processing circuit, so as to improve signal crosstalk between multiple paths and ensure independent operation of each path.

It should be noted that the above-described shield can also be provided in the following embodiments.

Alternatively, as shown in fig. 2, fig. 2 is a schematic diagram of another embodiment of the receive diversity circuit of the present utility model. The intermediate frequency processing circuit 20 in this embodiment includes a signal processing circuit 201 and a second oscillating circuit 202. The signal processing circuit 201 is connected with the front-end circuit 10 and is used for processing the intermediate frequency signal to obtain a modulation signal and a field intensity signal; the second oscillating circuit 202 is connected to the signal processing circuit 201 for generating an internal frequency signal to the signal processing circuit 201.

The modulation signal comprises an In-phase Quadrature (IQ) signal, and the IQ signal is a mapping of a continuous signal In a two-dimensional rectangular coordinate system and is used for conversion and reconstruction of a baseband signal. The second oscillation circuit 202 receives the control voltage CV of the signal processing circuit 201, oscillates based on the control voltage CV, generates an internal frequency signal, and feeds back the internal frequency signal to the signal processing circuit 201, so that the frequencies of the modulation signal and the field intensity signal output from the signal processing circuit 201 are stabilized.

Optionally, the signal processing circuit 201 includes an AD9864 chip.

The high dynamic range of the AD9864 chip and the anti-aliasing function inherent in the bandpass sigma-delta converter enable the chip to handle blocking signals 95dB higher than the target signal strength, reduce intermediate frequency filtering requirements, support multimode radios with different channel bandwidths, and enable the front-end circuit 10 to have the maximum nominal channel bandwidth. The sigma-delta ADC inside the AD9864 reduces noise through sampling to improve dynamic range, improves linearity accuracy of IQ signals output by the AD9864 chip, further improves accuracy of calculated received signal strength indication (Received Signal Strength Indicator, RSSI), and can directly read RSSI, so that a linear field strength value is obtained, weight can be calculated more accurately, further a better receive diversity effect is achieved, diversity sensitivity can be improved, and phase synchronization of the intermediate frequency processing circuit 20 can be achieved.

Optionally, as shown in fig. 3, fig. 3 is a schematic structural diagram of a further embodiment of the receive diversity circuit of the present utility model. The receive diversity circuit 1 in this embodiment further comprises a frequency source 50. The frequency source 50 is connected to the plurality of intermediate frequency processing circuits 20, respectively, for providing external frequency signals to the plurality of intermediate frequency processing circuits 20, respectively.

The frequency source 50 may also be connected to the control circuit 30, and the control circuit 30 may selectively control the frequency source 50 to provide external frequency signals for the plurality of intermediate frequency processing circuits 20 according to the usage requirement of the application scenario. The plurality of intermediate frequency processing circuits 20 provide the frequency signal through the same frequency source 50, so that the problem that the plurality of intermediate frequency processing circuits 20 generate co-frequency interference can be solved, and the consistency of the phases of the plurality of intermediate frequency processing circuits 20 can be ensured.

Alternatively, as shown in fig. 4, fig. 4 is a schematic diagram of a structure of a further embodiment of the receive diversity circuit of the present utility model. The frequency source 50 in this embodiment includes a first oscillating circuit 501 and a phase locked loop 502. The first oscillation circuits 501 are respectively connected with the plurality of intermediate frequency processing circuits 20 and are used for outputting external frequency signals; the phase-locked loop 502 is connected to the first oscillating circuit 501, and is configured to receive and control an external frequency signal of the first oscillating circuit 501, and feed back the controlled external frequency signal to the first oscillating circuit 501.

The pll 502 receives an external frequency signal, and controls a pump current of the external frequency signal to vibrate out a required frequency through the first oscillating circuit 501, so that co-frequency interference can be prevented, and phase consistency can be ensured.

Alternatively, as shown in fig. 5, fig. 5 is a schematic diagram of a structure of a further embodiment of the receive diversity circuit of the present utility model. The receive diversity circuit 1 in this embodiment further comprises a power divider 60. The power divider 60 is connected to the frequency source 50 and the plurality of intermediate frequency processing circuits 20, and is configured to divide the external frequency signal into a plurality of frequency sub-signals, and output the plurality of frequency sub-signals to the plurality of intermediate frequency processing circuits 20, respectively.

The power divider 60 may divide the external frequency signal equally, so that the external frequency signal is divided equally into a plurality of frequency sub-signals corresponding to the plurality of intermediate frequency processing circuits 20. The power divider 60 outputs each frequency sub-signal to a corresponding one of the intermediate frequency processing circuits 20.

When the plurality of intermediate frequency processing circuits 20 includes at least three intermediate frequency processing circuits 20, the power divider 60 may include two power dividers 60. A power divider 60 receives the external frequency signal of the frequency source 50, equally divides the external frequency signal into two frequency sub-signals, wherein the two frequency sub-signals comprise a first frequency sub-signal and a second frequency sub-signal, and outputs the first frequency sub-signal to an intermediate frequency processing circuit 20; the other power divider 60 receives the second frequency sub-signal, divides the second frequency sub-signal again to obtain a third frequency sub-signal and a fourth frequency sub-signal, and outputs the third frequency sub-signal and the fourth frequency sub-signal to the two intermediate frequency processing circuits 20 respectively.

Alternatively, as shown in fig. 6, fig. 6 is a schematic diagram of a structure of a further embodiment of the receive diversity circuit of the present utility model. The receive diversity circuit 1 further includes a receive board 70, a control board 80, a first terminal 71, and a second terminal 81. A plurality of front-end circuits 10 and a plurality of intermediate frequency processing circuits 20 are provided on the receiving board 70; the control circuit 30 is provided on the control board 80; the first terminal 71 is provided on a side of the receiving board 70 close to the control board 80; the second terminal 81 is provided on a side of the control board 80 close to the receiving board 70 and is connected to the first terminal 71, and the intermediate frequency processing circuit 20 is connected to the control circuit 30 through the first terminal 71 and the second terminal 81.

The first terminal 71 and the second terminal 81 are electrically connected, and the plurality of intermediate frequency processing circuits 20 are connected to the control circuit 30 via the first terminal 71 and the second terminal 81.

Optionally, the plurality of intermediate frequency processing circuits 20 includes three intermediate frequency processing circuits 20, and the plurality of front-end circuits 10 includes three front-end circuits 10.

The control circuit 30 is connected to the three intermediate frequency processing circuits 20, and weights the three modulated signals and the field intensity signals output by the three intermediate frequency processing circuits 20 to obtain a received signal, so that three-way diversity reception of the signal can be realized.

In an application scenario, as shown in fig. 7, fig. 7 is a schematic structural diagram of a receiving diversity circuit according to another embodiment of the present utility model. The receive diversity circuit 1 in this embodiment includes the front-end circuit 10, the intermediate frequency processing circuit 20, the control circuit 30, the receiving board 70, the control board 80, the first terminal 71, and the second terminal 81. The control circuit 30 is connected to the front-end circuit 10 and the intermediate frequency processing circuit 20, and is capable of controlling the front-end circuit 10 and diversity of the modulation signal and the field intensity signal outputted from the intermediate frequency processing circuit 20.

The front-end circuit 10 includes two band-pass filters (Berkeley Packet Filter, BPF), a Low-pass Filter (LPF), a Low noise amplifier SKY (LNA), an intermediate frequency Filter IF-Filter, and an intermediate frequency amplifier IF-AMP (& ACG). The low noise amplifier SKY (LNA) is connected to 5VA, and the intermediate frequency amplifier IF-AMP (& ACG) is connected to R5V. The intermediate frequency processing circuit 20 includes three ADs 9864 and three vco_2los (i.e., the second oscillating circuit 202). Each AD9864 is connected to 3V3A, 3V3D and 5va_if, and each vco_2LO is connected to 5va_if. The control circuit 30 includes programmable array logic (Field Programmable Gate Array, FPGA), an open multimedia application platform (Open Multimedia Application Platform, OMAP), a MAX3072 level shifter, an asynchronous transceiver Transmitter (Universal Asynchronous Receiver/Transmitter, UART), UART3, RS485 bus, STM32F100 (32 bit single chip microcomputer), and an op-amp (i.e., operational amplifier) NGM2904M. The op-amp may be NGM2904M. STM32F100 (32 bit SCM) is connected with MCU_3.3V, NGM2904M is connected with 9V1A. The control signal output by STM32F100 (32-bit single chip microcomputer) is amplified by NGM2904M and then output to the first BPF and the second BPF of front-end circuit 10.

The first end of the first BPF is connected with a radio frequency signal RF, the second end of the first BPF is connected with one end of the NGM2904M, the third end of the first BPF is connected with one end of the LPF, and the radio frequency signal is filtered and then output to one end of the LPF under the control of a control signal output by the NGM 2904M; the other end of the LPF is connected with the first end of the SKY (LNA); the second end of the SKY (LNA) is connected to 5VA, and the third end of the SKY (LNA) is connected with the first end of the second BPF; a second end of the second BPF is connected with one end of the NGM2904M, and a third end of the second BPF is connected with the first end of the mixer; the second end of the mixer is connected with the LO signal, and the third end of the mixer is connected with one end of the IF-Filter; the other end of the IF-Filter is connected with the first end of the IF-AMP (& ACG), the second end of the IF-AMP (& ACG) is connected with R5V, and the third end of the IF-AMP (& ACG) is connected with the AD9864 so as to output a radio frequency signal.

The AD9864 receives the radio frequency signal and outputs the chip select signal CS, the indication signal DO, the synchronous clock signal SCK, the rail signal DIN through the SPI interface under the action of the vco_2lo, and outputs the digital IQ signal (i.e., the above-mentioned modulated signal), the field strength signal, and the clock signal through the SSI interface. The FPGA performs weighting and combining and other processing on signals output by the SPI interface and the SSI interface of the three paths of AD9864 to realize three diversity, transmits the data after diversity completion to an OMAP for communication transmission, and transmits the data to an STM32F100 (32-bit singlechip) through a UART, a MAX3072 level converter, an RS485 and a UART3 to realize writing, storage, resetting, setting and the like of diversity data. The signal crosstalk between the paths of the reception diversity circuit 1 can be suppressed, the reception diversity of the signal can be realized, and the sensitivity of the diversity can be improved.

In an application scenario, as shown in fig. 8, fig. 8 is a schematic diagram of a specific circuit structure of the intermediate frequency processing circuit in the embodiment of fig. 1. The intermediate frequency processing circuit 20 in this embodiment includes three ADs 9864, three local oscillator voltage controlled oscillators (Voltage Controlled Oscillator, VCO), and three 18MHz clock synthesizers.

Wherein the pins of each AD9864 comprise IFIN, CLKP, CLKN, LOP, LON, PE, PD, PC, SYNCB, FS, DOUTA, CLKOUT, FREF, IOUTL, IOUTC. Each AD9864 has a IFIN, CLKP, CLKN connected to an 18MHz clock synthesizer, LOP and IOUTL connected to a local oscillator VCO, LON grounded, PE, PD, PC, SYNCB being the four pins of the SPI interface, FS, DOUTA, CLKOUT being the three pins of the SSI interface, and FREF connected to a crystal oscillator (i.e., the frequency source 50). SYNCB is a frame synchronization enable signal.

The same reference source ensures that the clock frequency remains consistent so that three ADs 9864 share the same reference clock. Each AD9864 uses an 18MHz clock independently, and local oscillator VCOs of the paths also remain independent, so that each AD9864 can be used independently. When three frame synchronization enabling signals SYNCB are output to the FPGA, one pin of the FPGA is used for controlling the same, and the SPI interface of the three paths of AD9864 is also controlled by using the same pin of the FPGA, so that the output signal frames can be kept synchronous, and the consistency of AD9864 configuration is further ensured. Stable reception diversity can be achieved.

In an application scenario, as shown in fig. 9, fig. 9 is a schematic diagram of a part of the circuit structure of the receive diversity circuit in the embodiment of fig. 5. The receive diversity circuit 1 of the present embodiment includes the front-end circuit 10, the intermediate frequency processing circuit 20, the control circuit 30, the frequency source 50, and the two power dividers 60. The frequency source 50 includes a VCO and a phase locked loop (Phase Locked Loop, PLL) chip. The intermediate frequency processing circuit 20 includes three ADs 9864.

The VCO is connected to one power divider 60 and the PLL chip, one power divider 60 is also connected to one AD9864 and the other power divider 60, and the other power divider 60 is also connected to the other two ADs 9864. The PLL chip provides the external frequency signal required for the pump current to oscillate out through the VCO, which is distributed to three ADs 9864 for use by the two power splitters 60. The co-channel interference problem of the receiving diversity can be improved, and the phase consistency can be ensured. The control circuit 30 can selectively control the frequency source 50 and the two power dividers 60 to provide external frequency signals for the three ADs 9864 according to the usage requirements of the application. When an external frequency signal is needed to be accessed, the control circuit 30 controls the frequency source 50 and the two power dividers 60 to be communicated with the three AD 9864; when external frequency signal access is not needed, the control circuit 30 controls the frequency source 50 and the two power dividers 60 to stop working.

In order to solve the above-mentioned technical problem, the present utility model further provides a communication device, as shown in fig. 10, and fig. 10 is a schematic structural diagram of an embodiment of the communication device of the present utility model. The communication apparatus 90 in this embodiment includes the above-described reception diversity circuit 1. The receive diversity circuit 1 is provided on the communication device 90.

Wherein the communication device 90 may comprise a printed circuit board (Printed Circuit Board, PCB) on which the receive diversity circuit 1 may be integrated. The adoption of the receiving diversity circuit 1 can improve the overall integration level, reduce the layout area of the PCB and reduce the cost.

In an application scenario, the communication device 90 is used on a CPCI U1/U3/V channel machine. Compact PCI (Compact Peripheral Component Interconnect, CPCI) is a bus interface standard. Taking CPCI U3 as an example, CPCI U3 was adjusted under the condition of a power supply voltage of 13.6V at normal temperature of 25 degrees before the experiment, and the 5% sensitivity of the three paths of reception and diversity in the reception diversity circuit 1 of the communication device 90 was tested. The front-end circuit 10 of the receiving diversity circuit 1 is input by using a radio frequency line in the test process, so that the consistency of signal sources is ensured. The receiving diversity circuit 1 of this embodiment is a new scheme, the existing implementation of tri-diversity by using the SA616D intermediate frequency processing chip is an old scheme, and the new scheme and the old scheme are tested respectively to obtain the following table 1.

The three paths are path a, path B, and path C, respectively, and the path at the time of double diversity is path AB combining path a and path B, path AC combining path a and path C, and path BC combining path B and path C. After the receiving diversity circuit 1 of the embodiment is tested by experiments, the corresponding sensitivity difference values of the new scheme and the old scheme are calculated, so that the receiving diversity circuit 1 of the embodiment can obtain about 1dB improvement of 5% diversity sensitivity under three-diversity reception. The sensitivity and effect of the reception diversity can be improved.

In describing embodiments of the present utility model, it should be noted that, unless explicitly stated and limited otherwise, the terms "coupled," "coupled," and "connected" should be construed broadly, and may be either a fixed connection, a removable connection, or an integral connection, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium. The specific meaning of the above terms in embodiments of the present utility model will be understood in detail by those of ordinary skill in the art.

In embodiments of the utility model, unless expressly specified and limited otherwise, a first feature "up" or "down" on a second feature may be that the first and second features are in direct contact, or that the first and second features are in indirect contact via an intervening medium. Moreover, a first feature being "above," "over" and "on" a second feature may be a first feature being directly above or obliquely above the second feature, or simply indicating that the first feature is level higher than the second feature. The first feature being "under", "below" and "beneath" the second feature may be the first feature being directly under or obliquely below the second feature, or simply indicating that the first feature is less level than the second feature.

In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the embodiments of the present utility model. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, the different embodiments or examples described in this specification and the features of the different embodiments or examples may be combined and combined by those skilled in the art without contradiction. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present utility model, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise.

The foregoing description is only illustrative of the present utility model and is not intended to limit the scope of the utility model, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present utility model.

Claims (10)

1. A receive diversity circuit comprising:

each front-end circuit is used for receiving one path of radio frequency signal and converting the radio frequency signal into an intermediate frequency signal;

the intermediate frequency processing circuits are connected with the front-end circuits in a one-to-one correspondence manner and are used for processing the corresponding intermediate frequency signals to obtain corresponding modulation signals and field intensity signals;

and the control circuit is connected with the intermediate frequency processing circuits and is used for carrying out weighting processing on the multipath modulation signals and the field intensity signals to obtain received signals so as to realize multipath diversity reception of the signals.

2. The receive diversity circuit of claim 1, further comprising:

and the shielding cover is arranged outside the front-end circuits and the intermediate frequency processing circuits and used for increasing the anti-interference capacity of the front-end circuits and the intermediate frequency processing circuits.

3. The receive diversity circuit of claim 1, further comprising:

and the frequency sources are respectively connected with the intermediate frequency processing circuits and are used for respectively providing external frequency signals for the intermediate frequency processing circuits.

4. The receive diversity circuit of claim 3, wherein the receive diversity circuit further comprises:

and the power divider is respectively connected with the frequency source and the intermediate frequency processing circuits, and is used for dividing the external frequency signal into a plurality of frequency sub-signals and respectively outputting the plurality of frequency sub-signals to the plurality of intermediate frequency processing circuits.

5. A receive diversity circuit as recited in claim 3, wherein said frequency source comprises:

the first oscillating circuit is respectively connected with the intermediate frequency processing circuits and is used for outputting the external frequency signals;

the phase-locked loop is connected with the first oscillating circuit and is used for receiving and controlling the external frequency signal of the first oscillating circuit and feeding the controlled external frequency signal back to the first oscillating circuit.

6. The receive diversity circuit of claim 1 wherein the intermediate frequency processing circuit comprises:

the signal processing circuit is connected with the front-end circuit and is used for processing the intermediate frequency signal to obtain the modulation signal and the field intensity signal;

and the second oscillating circuit is connected with the signal processing circuit and is used for generating an internal frequency signal to the signal processing circuit.

7. The receive diversity circuit of claim 6 wherein the signal processing circuit comprises an AD9864 chip.

8. The receive diversity circuit of claim 1 wherein said plurality of intermediate frequency processing circuits comprises three of said intermediate frequency processing circuits and said plurality of front-end circuits comprises three of said front-end circuits.

9. The receive diversity circuit of claim 1, further comprising:

the receiving board is provided with a plurality of front-end circuits and a plurality of intermediate frequency processing circuits;

the control circuit is arranged on the control board;

a first terminal provided on a side of the receiving plate close to the control board;

the second terminal is arranged on one side of the control board, which is close to the receiving board, and is connected with the first terminal, and the intermediate frequency processing circuit is connected with the control circuit through the first terminal and the second terminal.

10. A communication device, comprising:

a receive diversity circuit as claimed in any one of claims 1 to 9.