CN219872324U - Power management circuit of chip tester and chip tester - Google Patents
Power management circuit of chip tester and chip tester Download PDFInfo
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- CN219872324U CN219872324U CN202321298456.1U CN202321298456U CN219872324U CN 219872324 U CN219872324 U CN 219872324U CN 202321298456 U CN202321298456 U CN 202321298456U CN 219872324 U CN219872324 U CN 219872324U
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Abstract
The utility model relates to the field of semiconductor automation test, in particular to a power management circuit of a chip tester and the chip tester, wherein the chip tester comprises a computer module and a memory, and the circuit comprises: a power supply circuit connected to the computer module and the memory for supplying power to the computer module and the memory module; the first switch circuit is connected between the output end of the power supply circuit and the common ground, and the computer module clears the configuration information of the memory under the condition that the first switch circuit is conducted. The technical scheme has the following technical effects: the configuration information of the memory can be cleared through the conduction control of the first switch circuit, and the clearing mode is more convenient.
Description
Technical Field
The present utility model relates to the field of semiconductor automated testing, and in particular, to a power management circuit of a chip tester and a chip tester.
Background
The automatic semiconductor test includes utilizing the tester to detect the parameters of the tested device and eliminating defective products to control the quality of the semiconductor device. The tester comprises a computer module, a memory and the like.
When the computer module is abnormal, the BIOS needs to be entered through the computer module to reset the configuration information of the memory, and the clearing mode is complex.
Disclosure of Invention
Accordingly, it is desirable to provide a power management circuit of a chip tester and a chip tester for solving the above-mentioned problems.
In a first aspect, an embodiment of the present utility model provides a power management circuit of a chip tester, where the chip tester includes a computer module and a memory, and the circuit includes:
a power supply circuit connected to the computer module and the memory for supplying power to the computer module and the memory module;
the first switch circuit is connected between the output end of the power supply circuit and the common ground, and the computer module clears the configuration information of the memory under the condition that the first switch circuit is conducted.
In an embodiment, the first switching circuit includes: a first switch sub-circuit connected between an output terminal of the power supply circuit and a common ground; a second switch sub-circuit connected between the output terminal of the power supply circuit and the common ground;
the power management circuit further includes: a processor connected with the first switch sub-circuit and used for controlling the on or off of the first switch sub-circuit;
and under the condition that the first switch circuit or the second switch sub-circuit is conducted, the computer module clears the configuration information of the memory.
In an embodiment, the first switching sub-circuit comprises: the first MOS tube and the first resistor;
the grid electrode of the first MOS tube is connected with the processor, and the drain electrode of the first MOS tube is connected with the output end of the power supply circuit; the first resistor is connected between the grid electrode of the first MOS tube and the common ground.
In an embodiment, the second switch sub-circuit comprises: a key switch;
the key switch is connected between the output end of the power supply circuit and the public ground.
In one embodiment, the power supply circuit includes:
the input end of the first power supply sub-circuit is connected with a first system power supply, and the output end of the first power supply sub-circuit is connected with the computer module and the memory;
and the input end of the second power supply sub-circuit is connected with a standby power supply, and the output end of the second power supply sub-circuit is connected with the computer module and the memory.
In an embodiment, the first power supply sub-circuit includes: a first diode and a fourth resistor; the first diode and the fourth resistor are connected in series to the output end of the first system power supply;
the second power supply sub-circuit includes: a second diode and a fifth resistor; the second diode and the fifth resistor are connected in series to the output end of the standby power supply.
In an embodiment, the circuit further comprises:
a second switching circuit connected between the standby power supply and a common ground;
the input end of the signal acquisition circuit is connected with the second switch circuit, and the output end of the signal acquisition circuit is connected with the processor;
the second switch circuit is conducted under the condition that the first system power supply supplies power; in the case of the backup power supply, the second switching circuit is opened.
In an embodiment, the second switching circuit includes: the second MOS tube and the seventh resistor;
the drain electrode of the second MOS tube is connected with the standby power supply, the source electrode of the second MOS tube is connected with the signal acquisition circuit, and the grid electrode of the second MOS tube is connected with a second system power supply; the seventh resistor is connected between the source electrode of the second MOS tube and the common ground.
In one embodiment, the signal acquisition circuit comprises:
the non-inverting input end of the voltage follower is connected with the second switching circuit;
and the input end of the analog-to-digital converter is connected with the voltage follower, and the output end of the analog-to-digital converter is connected with the processor.
In a second aspect, an embodiment of the present utility model provides a chip tester, including the power management circuit according to the first aspect.
Compared with the prior art, the technical scheme has the following technical effects:
1. the clearing of the configuration information of the memory can be realized through the conduction control of the first switch circuit, and the clearing mode is more convenient;
2. under the condition that the first system power supply is normally electrified, the first switch sub-circuit can be controlled to be conducted through a control instruction sent by the processor, or the second switch sub-circuit can be controlled to be conducted through a manual triggering mode, under the condition that the first system power supply is powered off, the second switch sub-circuit can be controlled to be conducted through a manual triggering mode, and the two modes can control the computer module to be grounded, so that the configuration information can be cleared;
3. through second switch circuit and signal acquisition circuit, realize stand-by power supply's electric quantity monitoring, and under stand-by power supply's circumstances, second switch circuit disconnection to avoid stand-by power supply's electric leakage.
Drawings
FIG. 1 is a schematic diagram illustrating a power management circuit according to an embodiment of the present utility model;
fig. 2 is a schematic connection diagram of a first switch circuit according to an embodiment of the utility model;
FIG. 3 is a schematic diagram illustrating connection of a power supply circuit according to an embodiment of the present utility model;
FIG. 4 is a schematic diagram illustrating the overall connection of a source management circuit according to an embodiment of the present utility model;
fig. 5 is a schematic circuit diagram of a source management circuit according to an embodiment of the present utility model.
10, a computer module; 20. a memory; 30. a power supply circuit; 40. a first switching circuit; 50. a processor; 60. a standby power supply; 70. a first system power supply; 80. a second switching circuit; 90. a signal acquisition circuit; 100. a second system power supply; 301. a first power supply electronic circuit; 302. a second power supply circuit; 401. a first switch sub-circuit; 402. a second switching sub-circuit.
Detailed Description
The present utility model will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present utility model more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
It is apparent that the drawings in the following description are only some examples or embodiments of the present utility model, and it is possible for those of ordinary skill in the art to apply the present utility model to other similar situations according to these drawings without inventive effort. Moreover, it should be appreciated that while such a development effort might be complex and lengthy, it would nevertheless be a routine undertaking of design, fabrication, or manufacture for those of ordinary skill having the benefit of this disclosure, and thus should not be construed as having the benefit of this disclosure.
Reference in the specification to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the utility model. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is to be expressly and implicitly understood by those of ordinary skill in the art that the described embodiments of the utility model can be combined with other embodiments without conflict.
Unless defined otherwise, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this utility model belongs. The terms "a," "an," "the," and similar referents in the context of the utility model are not to be construed as limiting the quantity, but rather as singular or plural. The terms "comprising," "including," "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, article, or apparatus that comprises a list of steps or modules (elements) is not limited to only those steps or elements but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus. The terms "connected," "coupled," and the like in connection with the present utility model are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The term "plurality" as used herein means two or more. "and/or" describes an association relationship of an association object, meaning that there may be three relationships, e.g., "a and/or B" may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. The terms "first," "second," "third," and the like, as used herein, are merely distinguishing between similar objects and not representing a particular ordering of objects.
As shown in fig. 1, the present embodiment provides a power management circuit of a chip tester, the chip tester including a computer module 10 and a memory 20, the power management circuit comprising: a power supply circuit 30 connected to the computer module 10 and the memory 20 for supplying power to the computer module 10 and the memory 20; the first switch circuit 40 is connected between the output terminal of the power supply circuit 30 and the common ground, and the computer module 10 clears the configuration information of the memory 20 when the first switch circuit 40 is turned on.
The computer module 10 is connected to the common ground through the first switching circuit 40 in the case where the first switching circuit 40 is turned on, and the computer module 10 can clear the configuration information of the memory 20 in the case where the computer module 10 is grounded. In this embodiment, the configuration information of the memory 20 can be cleared by conducting control of the first switch circuit 40, which is more convenient than the prior art.
In one embodiment, as shown in fig. 2, the first switching circuit 40 includes: a first switching sub-circuit 401 connected between the output of the power supply circuit 30 and the common ground; a second switch sub-circuit 402 connected between the output of the power supply circuit 30 and the common ground; the power management circuit further includes: a processor 50 connected to the first switch sub-circuit 401 for controlling on or off of the first switch sub-circuit 401; in the case where the first switch circuit 40 or the second switch sub-circuit 402 is turned on, the computer module 10 clears the configuration information of the memory 20.
In the case that the first system power supply 70 is powered off, the first switch sub-circuit 401 may be controlled to be turned on remotely by a control instruction sent by the processor 50, or the second switch sub-circuit 402 may be controlled to be turned on by a manual triggering manner, in the case that the first system power supply 70 is powered off, the second switch sub-circuit 402 may be controlled to be turned on by a manual triggering manner, and both the above two manners may control the computer module 10 to be grounded, so as to implement clearing of configuration information.
In one embodiment, as shown in fig. 3, the power supply circuit 30 includes: the first power supply sub-circuit 301 has an input terminal connected to the first system power supply 70 and an output terminal connected to the computer module 10 and the memory 20; the second power supply sub-circuit 302 has an input terminal connected to the standby power supply 60 and an output terminal connected to the computer module 10 and the memory 20.
The power supply voltage of the first system power supply 70 is greater than the power supply voltage of the standby power supply 60, the first power supply sub-circuit 301 is turned on and the second power supply sub-circuit 302 is turned off under the condition that the first system power supply 70 is normally powered on, and the first system power supply supplies power to the computer module 10 and the memory 20 by default, so that the electric quantity of the standby power supply 60 is not consumed; in the event that the first system power supply 70 is powered down, the first power supply sub-circuit 301 is turned off and the second power supply sub-circuit 302 is turned on, and the standby power supply 60 supplies power to the computer module 10 and the memory 20, thereby ensuring that the computer module 10 and the memory 20 can operate normally.
The backup power source 60 is, for example, a button cell.
As shown in fig. 4, to implement power monitoring of the backup power source 60, the power management circuit further includes: a second switching circuit 80 connected between the standby power supply 60 and the common ground; the input end of the signal acquisition circuit 90 is connected with the second switch circuit 80, and the output end of the signal acquisition circuit is connected with the processor 50.
In the case where the first system power supply 70 is supplied with power through the first power supply sub-circuit 301, the second switching circuit 80 is turned on; in the case where the standby power supply 60 is supplied with power through the second power supply electronic circuit 302, the second switching circuit 80 is turned off, thereby avoiding leakage of the standby power supply 60.
The structure of the power management circuit is specifically described below with reference to fig. 5.
Wherein the first switch sub-circuit 401 comprises: the MOS transistor comprises a first MOS transistor Q1, a first resistor R1 and optionally a second resistor R2; the grid electrode of the first MOS tube is connected with the processor 50, and the drain electrode of the first MOS tube is connected with the output end of the power supply circuit 30; the first resistor R1 is connected between the grid electrode of the first MOS tube and the public ground and is used for providing a default low level so as to ensure that the first MOS tube is in an off state when the processor 50 does not send a control instruction; the second resistor R2 is connected between the source electrode of the first MOS tube and the common ground and used for limiting current during discharging and protecting a circuit.
The second switch sub-circuit 402 includes: the key switch S1, optionally, further includes a third resistor R3; the key switch S1 is connected between the output end of the power supply circuit 30 and the common ground, and is used for controlling the on-off between the computer module 10 and the memory 20 and the common ground; the third resistor R3 is connected in series between the output terminal of the power supply circuit 30 and the common ground, and is used for limiting current during discharging and protecting the circuit.
The first power supply electronic circuit 301 includes: a first diode D1 and a fourth resistor R4; the first diode D1 and the fourth resistor R4 are connected in series to the output terminal of the first system power supply 70, the positive electrode of the first diode D1 is connected to the first system power supply 70, and the fourth resistor R4 is used for limiting current when power is supplied to provide protection for the circuit.
The second power supply electronic circuit 302 includes: a second diode D2 and a fifth resistor R5; the second diode D2 is connected in series with the fifth resistor R5 at the output end of the standby power supply 60, the positive electrode of the second diode D2 is connected with the standby power supply 60, and the fifth resistor R5 is used for limiting current during power supply, so as to provide protection for the circuit.
The voltage of the first system power supply 70 is VDD and the voltage of the standby power supply 60 is VBAT. When the board is normally powered on, VDD is greater than VBAT, at this time, the first diode D1 is turned on, the second diode D2 is turned off, and the first system power supply 70 supplies power to the computer module 10 and the memory 20; when the board is powered off, VBAT is greater than VDD, at this time, the first diode D1 is turned off, and the second diode D2 is turned on, and the standby power supply 60 supplies power to the computer module 10 and the memory 20.
The second switching circuit 80 includes: the second MOS transistor Q2 and the seventh resistor R7, and optionally, a sixth resistor R6 and a first capacitor C1; the drain electrode of the second MOS tube is connected with the standby power supply 60, and the source electrode of the second MOS tube Q2 is connected with the signal acquisition circuit 90; the sixth resistor R6 is connected between the grid electrode of the second MOS tube Q2 and the second system power supply 100, the voltage of the second system power supply 100 is VCC, and the difference value between VCC and VBAT is larger than VGSth of the second MOS tube Q2; the sixth resistor R6 is used for protecting the grid electrode of the second MOS transistor Q2; the seventh resistor R7 is connected between the source electrode of the second MOS tube Q2 and the common ground and is used for ensuring that the source electrode level of the second MOS tube Q2 is low level before the second MOS tube Q2 is started; the first capacitor C1 is connected between the grid electrode of the second MOS tube Q2 and the public ground and used for slow start, and the reliability of the circuit is improved.
The signal acquisition circuit includes: a voltage follower U1, the non-inverting input end of which is connected with the second switch circuit 80; the analog-to-digital converter ADC has an input connected to the voltage follower U1 and an output connected to the processor 50.
The operation principle of the power management circuit is specifically described below with reference to fig. 5.
Since the power supply voltage of the first system power supply 70 is greater than the power supply voltage of the standby power supply 60, when the first system power supply 70 is powered up normally, VDD is greater than VBAT, and the first system power supply 70 supplies power to the computer module 10 and the memory 20 by default, so that the electric quantity of the standby power supply 60 is not consumed; when the tester is powered down, VBAT is greater than VDD, and power is supplied to the computer module 10 and memory 20 by the backup power source 60. Wherein the first diode D1 and the second diode D2 are used to gate the first system power supply 70 or the standby power supply 60 and prevent the reverse current flow.
Under the condition that the first system power supply 70 is normally powered on, a control instruction can be issued to the processor 50 through the upper computer, the processor 50 controls the first MOS tube Q1 to be conducted, the configuration information of the memory 20 is remotely cleared, and a single board of the testing machine does not need to be taken down, so that the maintenance efficiency is greatly improved.
Under the condition that the first system power supply 70 is powered on normally, the key switch S1 can be directly pressed to manually clear the configuration information of the memory 20, but at this time, the power supply of the computer module 10 and the memory 20 is the first system power supply 70, so that the power of the standby power supply 60 is not consumed when the key switch S1 is pressed.
Under the condition that the first system power supply 70 is powered off, the power supply of the computer module 10 and the memory 20 is the standby power supply 60, at this time, the key S1 can be directly pressed to manually clear the configuration information of the memory 20, at this time, due to the current limiting effect of the second resistor R2, the key time is shorter, the power consumption of the standby power supply 60 caused by the clearing operation is smaller, and the influence is negligible.
To improve the maintainability of the whole testing machine, the electric quantity of the standby power supply 60 needs to be continuously monitored, and when the electric quantity is lower than a preset threshold value, an alarm is given to prompt maintenance personnel to replace in time. The on-off of the second MOS transistor Q2 is controlled by the second system power supply 100. Under the condition that the first system power supply 70 is normally powered on, the second system power supply 100 controls the second MOS transistor Q2 to be conducted, the voltage of the standby power supply 60 is isolated by the voltage follower U1 and then is sent to the signal acquisition circuit 90ADC for acquisition and monitoring, continuous monitoring of the electric quantity of the standby power supply 60 can be achieved, and the input impedance of the voltage follower U1 is high enough, so that the electric quantity consumption of the standby power supply 60 is small in the electric quantity monitoring process, and the influence is negligible. When the board card is powered down, the voltage VDD of the first system power supply 70 is 0V, the voltage VCC of the second system power supply 100 is also 0V, and at this time, the second MOS transistor Q2 is not turned on, so that the standby power supply 60 can be prevented from leaking to the second system power supply 100, and the service life of the standby power supply 60 is ensured.
In an embodiment, a chip tester is further provided, including the above power management circuit.
It should be noted that, the power management circuit has been described in detail in the above embodiments, so that the description is omitted in this embodiment. Since the chip tester includes the power management circuit in the above embodiment, the same technical effects are achieved.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the utility model, which are described in detail and are not to be construed as limiting the scope of the utility model. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the utility model, which are all within the scope of the utility model. Accordingly, the scope of protection of the present utility model is to be determined by the appended claims.
Claims (10)
1. A power management circuit for a chip tester, the chip tester including a computer module and a memory, the circuit comprising:
a power supply circuit connected to the computer module and the memory for supplying power to the computer module and the memory module;
the first switch circuit is connected between the output end of the power supply circuit and the common ground, and the computer module clears the configuration information of the memory under the condition that the first switch circuit is conducted.
2. The power management circuit of a chip tester of claim 1, wherein the first switching circuit comprises: a first switch sub-circuit connected between an output terminal of the power supply circuit and a common ground; a second switch sub-circuit connected between the output terminal of the power supply circuit and the common ground;
the power management circuit further includes: a processor connected with the first switch sub-circuit and used for controlling the on or off of the first switch sub-circuit;
and under the condition that the first switch circuit or the second switch sub-circuit is conducted, the computer module clears the configuration information of the memory.
3. The power management circuit of the chip tester of claim 2, wherein the first switch sub-circuit comprises: the first MOS tube and the first resistor;
the grid electrode of the first MOS tube is connected with the processor, and the drain electrode of the first MOS tube is connected with the output end of the power supply circuit; the first resistor is connected between the grid electrode of the first MOS tube and the common ground.
4. The power management circuit of the chip tester of claim 2, wherein the second switch sub-circuit comprises: a key switch;
the key switch is connected between the output end of the power supply circuit and the public ground.
5. The power management circuit of a chip tester according to claim 2, wherein the power supply circuit comprises:
the input end of the first power supply sub-circuit is connected with a first system power supply, and the output end of the first power supply sub-circuit is connected with the computer module and the memory;
and the input end of the second power supply sub-circuit is connected with a standby power supply, and the output end of the second power supply sub-circuit is connected with the computer module and the memory.
6. The power management circuit of a chip tester of claim 5, wherein the first power supply sub-circuit comprises: a first diode and a fourth resistor; the first diode and the fourth resistor are connected in series to the output end of the first system power supply;
the second power supply sub-circuit includes: a second diode and a fifth resistor; the second diode and the fifth resistor are connected in series to the output end of the standby power supply.
7. The power management circuit of a chip tester of claim 5, wherein the circuit further comprises:
a second switching circuit connected between the standby power supply and a common ground;
the input end of the signal acquisition circuit is connected with the second switch circuit, and the output end of the signal acquisition circuit is connected with the processor;
the second switch circuit is conducted under the condition that the first system power supply supplies power; in the case of the backup power supply, the second switching circuit is opened.
8. The power management circuit of a chip tester according to claim 7, wherein the second switching circuit comprises: the second MOS tube and the seventh resistor;
the drain electrode of the second MOS tube is connected with the standby power supply, the source electrode of the second MOS tube is connected with the signal acquisition circuit, and the grid electrode of the second MOS tube is connected with a second system power supply; the seventh resistor is connected between the source electrode of the second MOS tube and the common ground.
9. The power management circuit of the chip tester according to claim 7, wherein the signal acquisition circuit comprises:
the non-inverting input end of the voltage follower is connected with the second switching circuit;
and the input end of the analog-to-digital converter is connected with the voltage follower, and the output end of the analog-to-digital converter is connected with the processor.
10. A chip tester comprising the power management circuit of any one of claims 1-9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202321298456.1U CN219872324U (en) | 2023-05-24 | 2023-05-24 | Power management circuit of chip tester and chip tester |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202321298456.1U CN219872324U (en) | 2023-05-24 | 2023-05-24 | Power management circuit of chip tester and chip tester |
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| CN219872324U true CN219872324U (en) | 2023-10-20 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118430634A (en) * | 2024-07-05 | 2024-08-02 | 珠海妙存科技有限公司 | EMMC chip aging test circuit, control method thereof and test system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118430634A (en) * | 2024-07-05 | 2024-08-02 | 珠海妙存科技有限公司 | EMMC chip aging test circuit, control method thereof and test system |
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