CN219778280U - Automatic identification access equipment circuit of cash register - Google Patents

Abstract

The utility model discloses an automatic identification access equipment circuit of a cash register, which is characterized in that: the device comprises a connection interface CN1, a processor U0, a level detection circuit, a cashbox control circuit and a serial port level conversion circuit; the level detection circuit is used for detecting the level of an RX pin of the connection interface CN 1; if the level of the RX pin of the connection interface CN1 is zero, the level detection circuit controls the cashbox control circuit to respond to the signal sent by the processor U0; if the level of the RX pin of the connection interface CN1 is not zero, the level detection circuit controls the serial level conversion circuit to respond to the signal sent by the processor U0. The utility model has the function of identifying cashboxes and other external RS232 equipment of the cashing machine, thereby leading the connection interface of the host machine of the cashing machine to be accessed into the cashbox or the external RS232 equipment according to the requirement.

Description

Automatic identification access equipment circuit of cash register

Technical Field

The utility model relates to the field of cash registers, in particular to an automatic identification access equipment circuit of a cash register.

Background

The existing host of the cash register is only provided with a connecting interface to connect with the cash box of the cash register, so that the host can control the opening and closing of the cash box. However, the main body of the cash register is sometimes connected with an external RS232 device (such as a display) according to the needs of a user, but the existing connection interface of the cash register for connecting the cash box cannot identify the external RS232 device, which results in that the cash register host provided with only one connection interface for connecting the cash box cannot be connected with the external RS232 device, and has a limitation of use.

In view of the foregoing, there is a need for an automatic identification access device circuit for a cash register, which has the function of identifying the cash register cashbox and other external RS232 devices, so that the connection interface of the cash register host can access the cashbox or the external RS232 devices as required.

Disclosure of Invention

The utility model aims to provide an automatic identification access device circuit of a cash register, which has the function of identifying the cash register cash box and other external RS232 devices, so that a connection interface of a cash register host can be accessed to the cash box or the external RS232 devices according to requirements.

In order to achieve the above object, the solution of the present utility model is:

an automatic identification access equipment circuit of a cash register comprises a connection interface CN1, a processor U0, a level detection circuit, a cashbox control circuit and a serial port level conversion circuit; the TX pin of the connection interface CN1 is connected with the cashbox control circuit and the serial port level conversion circuit, and the RX pin of the connection interface CN1 is connected with the level detection circuit and the serial port level conversion circuit; the processor U0 is connected with the cashbox control circuit and the serial port level conversion circuit; the level detection circuit is connected with the cashbox control circuit and the serial port level conversion circuit; the level detection circuit is used for detecting the level of an RX pin of the connection interface CN 1; if the level of the RX pin of the connection interface CN1 is zero, the level detection circuit controls the cashbox control circuit to respond to the signal sent by the processor U0, and meanwhile, the level detection circuit controls the serial level conversion circuit not to respond to the signal sent by the processor U0; if the level of the RX pin of the connection interface CN1 is not zero, the level detection circuit controls the cashbox control circuit not to respond to the signal sent by the processor U0, and at the same time, the level detection circuit controls the serial level conversion circuit to respond to the signal sent by the processor U0.

The level detection circuit comprises a resistor R6, a resistor R7, a resistor R8, a resistor R9, a diode D1, a diode D2, a diode D3, a triode Q4 and a triode Q5; the positive pole of diode D2 and the negative pole of diode D3 connect the input of level detection circuit, the RX foot of connection interface CN1 is connected to the input of level detection level, the negative pole of diode D2 passes through the base of triode Q5 is connected to resistance R8, the positive pole of diode D3 passes through resistance R9 and connects triode Q4's projecting pole, triode Q4's base and triode Q5's projecting pole ground, diode D1's positive pole and the first end of resistance R6 are connected to triode Q4's collecting electrode and triode Q5's collecting electrode, control power VCC is connected to resistance R6's second end, the output of level detection circuit is connected to diode D1's negative pole and the first end of resistance R7, the output of level detection circuit is connected cashbox control circuit and serial port level conversion circuit, resistance R7's second end ground.

The level detection circuit further comprises a capacitor C8, a first end of the capacitor C8 is connected with the output end of the level detection circuit, and a second end of the capacitor C8 is grounded.

The cashbox control circuit comprises a resistor R2, a resistor R3, a resistor R5, an AND gate U3, a MOS tube Q2 and a MOS tube Q3; the first input end of AND gate U3 and the first end of resistance R5 connect the input of cashbox control circuit, processor U0 is connected to cashbox control circuit's input, the output of level detection circuit is connected to cashbox control circuit's second input, MOS pipe Q3's grid is connected to AND gate U3's output, MOS pipe Q3's source and resistance R5's second ground connection, MOS pipe Q2's grid and resistance R3's first end are connected to MOS pipe Q3's drain electrode, driving power VDD is connected to MOS pipe Q2's source and resistance R3's second end, MOS pipe Q2's drain electrode passes through resistance R2 and connects cashbox control circuit's output, interface CN 1's TX foot is connected to cashbox control circuit's output.

The cashbox control circuit further comprises a capacitor C7, wherein a first end of the capacitor C7 is connected with a second end of the resistor R3 and a source electrode of the MOS tube Q2, and a second end of the capacitor C7 is grounded.

The serial port level conversion circuit comprises a resistor R1, a capacitor C3, a capacitor C5, a capacitor C6, an AND gate U2, a MOS tube Q1 and a level conversion chip U1; the first input end of the AND gate U2 is connected with the input side transmitting end of the serial level conversion circuit, the input side transmitting end of the serial level conversion circuit is connected with the processor U0, the second input end of the AND gate U2 is connected with the drain electrode of the MOS tube Q1 and the first end of the resistor R1, the second end of the resistor R1 is connected with the control power VCC, the source electrode of the MOS tube Q1 is grounded, the grid electrode of the MOS tube Q1 is connected with the control end of the serial level conversion circuit, the control end of the serial level conversion circuit is connected with the output end of the level detection circuit, the output end of the AND gate U2 is connected with the T1In pin of the level conversion chip U1, the R1Out pin of the level conversion chip U1 is connected with the input side receiving end of the serial level conversion circuit, the input side receiving end of the serial level conversion circuit is connected with the processor U0, the C2+ pin of the level conversion chip U1 is connected with the C2-pin of the level conversion chip U1 through a capacitor C5, the C1+ pin of the level conversion chip U1 is connected with the C1-pin of the level conversion chip U1 through a capacitor C3, the Vcc pin of the level conversion chip U1 and the first end of the capacitor C1 are connected with a control power VCC, the V+ pin of the level conversion chip U1 is connected with the second end of the capacitor C1, the V-pin of the level conversion chip U1 is connected with the first end of the capacitor C6, the GND pin of the level conversion chip U1 and the second end of the capacitor C6 are grounded, the T1Out pin and the R1In pin of the level conversion chip U1 are respectively connected with the output side transmitting end and the output side receiving end of the serial level conversion circuit, and the output side transmitting end and the output side receiving end of the serial level conversion circuit are respectively connected with the TX pin and the RX pin of the connection interface CN 1.

The serial port level conversion circuit further comprises a capacitor C2, a first end of the capacitor C2 is connected with a Vcc pin of the level conversion chip U1, and a second end of the capacitor C2 is grounded.

After the scheme is adopted, when the connection interface CN1 is connected with the external RS232 device, the external RS232 device can provide a level (generally +15V or-15V) which is not equal to zero for an RX pin of the connection interface CN1, and the level detection circuit detects that the level of the RX pin of the connection interface CN1 is not zero and judges that the connection interface CN1 is connected with the external RS232 device, and then the level detection circuit controls the cashbox control circuit to not respond to a signal sent by the processor U0 and simultaneously controls the serial level conversion circuit to respond to the signal sent by the processor U0, so that the processor can carry out serial port communication with the external RS232 device; when the connection interface CN1 is connected with the cashbox, the cashbox does not provide the level for the RX pin of the connection interface CN1 so that the level of the RX pin of the connection interface CN1 is zero, and the level detection circuit detects that the level of the RX pin of the connection interface CN1 is zero to judge that the connection interface CN1 is connected with the cashbox, and then the level detection circuit controls the cashbox control circuit to respond to the signal sent by the processor U0 and simultaneously controls the serial port level conversion circuit to respond to the signal sent by the processor U0, so that the processor can control the cashbox through the cashbox control circuit.

As can be seen from the above, the utility model has the function of identifying cashboxes and other external RS232 devices of the cashbox, so that the connection interface of the host machine of the cashbox can be accessed to the cashbox or the external RS232 devices according to the requirements.

Drawings

Fig. 1 is a schematic circuit diagram of the present utility model.

Detailed Description

In order to further explain the technical scheme of the utility model, the utility model is explained in detail by specific examples.

As shown in FIG. 1, the present utility model discloses an automatic identification access device circuit of a cash register, which comprises a connection interface CN1, a processor U0, a level detection circuit, a cashbox control circuit and a serial level conversion circuit; the TX pin of the connection interface CN1 is connected with the cashbox control circuit and the serial port level conversion circuit, and the RX pin of the connection interface CN1 is connected with the level detection circuit and the serial port level conversion circuit; the processor U0 is connected with the cashbox control circuit and the serial port level conversion circuit; the level detection circuit is connected with the cashbox control circuit and the serial port level conversion circuit.

In the present utility model, the level detection circuit is configured to detect a level of an RX pin of the connection interface CN 1; if the level of the RX pin of the connection interface CN1 is zero, the level detection circuit controls the cashbox control circuit to respond to the signal sent by the processor U0, and meanwhile, the level detection circuit controls the serial level conversion circuit not to respond to the signal sent by the processor U0; if the level of the RX pin of the connection interface CN1 is not zero, the level detection circuit controls the cashbox control circuit not to respond to the signal sent by the processor U0, and at the same time, the level detection circuit controls the serial level conversion circuit to respond to the signal sent by the processor U0.

The working principle of the utility model is as follows: when the connection interface CN1 is connected with the external RS232 device, the external RS232 device provides a level (generally +15V or-15V) which is not equal to zero for an RX pin of the connection interface CN1, and the level detection circuit detects that the level of the RX pin of the connection interface CN1 is not zero and judges that the connection interface CN1 is connected with the external RS232 device, and then the level detection circuit controls the cashbox control circuit not to respond to a signal sent by the processor U0 and simultaneously controls the serial level conversion circuit to respond to the signal sent by the processor U0, so that the processor can carry out serial port communication with the external RS232 device; when the connection interface CN1 is connected with the cashbox, the cashbox does not provide the level for the RX pin of the connection interface CN1 so that the level of the RX pin of the connection interface CN1 is zero, and the level detection circuit detects that the level of the RX pin of the connection interface CN1 is zero to judge that the connection interface CN1 is connected with the cashbox, and then the level detection circuit controls the cashbox control circuit to respond to the signal sent by the processor U0 and simultaneously controls the serial port level conversion circuit to respond to the signal sent by the processor U0, so that the processor can control the cashbox through the cashbox control circuit.

As can be seen from the above, the utility model has the function of identifying cashboxes and other external RS232 devices of the cashbox, so that the connection interface of the host machine of the cashbox can be accessed to the cashbox or the external RS232 devices according to the requirements.

Referring to fig. 1, the level detection circuit may include a resistor R6, a resistor R7, a resistor R8, a resistor R9, a diode D1, a diode D2, a diode D3, a transistor Q4, and a transistor Q5; the positive pole of the diode D2 and the negative pole of the diode D3 are connected with the input end of the level detection circuit, the input end of the level detection level is connected with the RX pin of the connection interface CN1, the negative pole of the diode D2 is connected with the base electrode of the triode Q5 through the resistor R8, the positive pole of the diode D3 is connected with the emitter electrode of the triode Q4 through the resistor R9, the base electrode of the triode Q4 and the emitter electrode of the triode Q5 are grounded, the collector electrode of the triode Q4 and the collector electrode of the triode Q5 are connected with the positive pole of the diode D1 and the first end of the resistor R6, the second end of the resistor R6 is connected with the control power VCC, the negative pole of the diode D1 and the first end of the resistor R7 are connected with the output end of the level detection circuit, the output end of the level detection circuit is connected with the cashbox control circuit and the serial port level conversion circuit, and the second end of the resistor R7 is grounded. The working principle of the level detection circuit is as follows: when the RX pin level of the connection interface CN1 is not zero, one of the transistor Q4 and the transistor Q5 is turned on (when the RX pin level of the connection interface CN1 is greater than zero, the transistor Q5 is turned on, and when the RX pin level of the connection interface CN1 is less than zero, the transistor Q4 is turned on), so that the output end of the level detection circuit outputs a low level signal; when the level of the RX pin of the connection interface CN1 is zero, the transistor Q4 and the transistor Q5 are not turned on, so that the output end of the level detection circuit outputs a high level signal.

With reference to fig. 1, the level detection circuit further includes a capacitor C8, a first end of the capacitor C8 is connected to the output end of the level detection circuit, a second end of the capacitor C8 is grounded, and the capacitor C8 can make the level output by the output end of the level detection circuit more stable.

With the illustration of fig. 1, the cashbox control circuit comprises a resistor R2, a resistor R3, a resistor R5, an and gate U3, a MOS transistor Q2 and a MOS transistor Q3; the first input end of the AND gate U3 and the first end of the resistor R5 are connected with the input end of the cashbox control circuit, the input end of the cashbox control circuit is connected with the processor U0, the second input end of the AND gate U3 is connected with the control end of the cashbox control circuit, the control end of the cashbox control circuit is connected with the output end of the level detection circuit, the output end of the AND gate U3 is connected with the grid electrode of the MOS tube Q3, the source electrode of the MOS tube Q3 and the second end of the resistor R5 are grounded, the drain electrode of the MOS tube Q3 is connected with the grid electrode of the MOS tube Q2 and the first end of the resistor R3, the source electrode of the MOS tube Q2 and the second end of the resistor R3 are connected with the driving power supply VDD, the drain electrode of the MOS tube Q2 is connected with the output end of the cashbox control circuit through the resistor R2, and the output end of the cashbox control circuit is connected with the TX pin of the connection interface CN 1. The cashbox control circuit has the working principle that: when the connection interface CN1 is connected with the external RS232 device, the level detection circuit detects that the level of the RX pin of the connection interface CN1 is not zero and outputs a low level signal to the cashbox control circuit, so that the level of the second input end of the and gate U3 of the cashbox control circuit is low, no matter what level signal is input by the processor U0 to the first input end of the and gate U3 of the cashbox control circuit, the output end of the and gate U3 keeps outputting a low level signal, and thus the cashbox control circuit does not respond to the signal sent by the processor U0; when the connection interface CN1 is connected with the cashbox, the level detection circuit detects that the level of the RX pin of the connection interface CN1 is zero and outputs a high level signal to the cashbox control circuit, so that the level of the second input end of the and gate U3 of the cashbox control circuit is high, and the level of the output end of the and gate U3 depends on the level of the signal input by the processor U0 to the first input end of the and gate U3 of the cashbox control circuit, so that the cashbox control circuit responds to the signal sent by the processor U0; when the cashbox control circuit responds to the signal sent by the processor U0, if the processor U0 inputs a high-level signal to the first input end of the AND gate U3 of the cashbox control circuit, the output end of the AND gate U3 outputs a high level to control the MOS tube Q3 and the MOS tube Q2 to be conducted, so that the output end of the cashbox control circuit outputs a high level, and the TX pin of the connection interface CN1 outputs a high-level signal to the cashbox to control the cashbox to be opened.

With reference to fig. 1, the cashbox control circuit further includes a capacitor C7, a first end of the capacitor C7 is connected to a second end of the resistor R3 and a source electrode of the MOS transistor Q2, a second end of the capacitor C7 is grounded, and the capacitor C7 can improve level stability of the second end of the resistor R3 and the source electrode of the MOS transistor Q2.

With reference to fig. 1, the serial port level conversion circuit includes a resistor R1, a capacitor C3, a capacitor C5, a capacitor C6, an and gate U2, a MOS transistor Q1, and a level conversion chip U1; the first input end of the and gate U2 is connected to the input side transmitting end of the serial level conversion circuit, the input side transmitting end of the serial level conversion circuit is connected to the processor U0, the second input end of the and gate U2 is connected to the drain of the MOS transistor Q1 and the first end of the resistor R1, the second end of the resistor R1 is connected to the control power VCC, the source of the MOS transistor Q1 is grounded, the gate of the MOS transistor Q1 is connected to the control end of the serial level conversion circuit, the control end of the serial level conversion circuit is connected to the output end of the level detection circuit, the output end of the and gate U2 is connected to the T1In pin of the level conversion chip U1, the R1Out pin of the level conversion chip U1 is connected to the input side receiving end of the serial level conversion circuit, the input side receiving end of the serial level conversion circuit is connected to the processor U0, the c2+ pin of the level conversion chip U1 is connected to the C2-pin of the level conversion chip U1 through the capacitor C5, the c1+ pin of the level conversion chip U1 is connected to the C1-pin of the level conversion chip U1 through the capacitor C3, the first pin of the level conversion chip U1 and the second pin of the capacitor C1 is connected to the output side receiving end of the serial level conversion circuit, the output side receiving end of the output end of the serial level conversion circuit is connected to the output end of the capacitor V1, and the output side receiving end of the output end of the serial level conversion circuit is connected to the output end of the output signal V1C 1. The serial port level conversion circuit has the working principle that: when the connection interface CN1 is connected with the external RS232 device, the level detection circuit detects that the level of the RX pin of the connection interface CN1 is not zero and outputs a low-level signal to the serial port level conversion circuit, so as to control the MOS transistor Q1 to be turned off to enable the level of the second input end of the and gate U2 of the serial port level conversion circuit to be high, and the level of the output end of the and gate U2 depends on the level of the signal input by the processor U0 to the first input end of the and gate U2 of the serial port level conversion circuit, so that the serial port level conversion circuit responds to the signal sent by the processor U0, and the processor U0 performs serial port communication with the external RS232 device through the serial port level conversion circuit; when the connection interface CN1 is connected to the cashbox, the level detection circuit detects that the level of the RX pin of the connection interface CN1 is zero and outputs a high level signal to the serial port level conversion circuit, so as to control the MOS transistor Q1 to be turned on to make the level of the second input end of the and gate U2 of the serial port level conversion circuit be a low level, no matter what level signal is input by the processor U0 to the first input end of the and gate U2 of the serial port level conversion circuit, the output end of the and gate U2 keeps outputting a low level signal, and thus the serial port level conversion circuit does not respond to the signal sent by the processor U0.

With reference to fig. 1, the serial port level conversion circuit may further include a capacitor C2, where a first end of the capacitor C2 is connected to a Vcc pin of the level conversion chip U1, a second end of the capacitor C2 is grounded, and the capacitor C2 may be capable of providing power stability to the level conversion chip U1.

In the present utility model, when the level of the RX pin of the connection interface CN1 is zero, at this time, the output end of the and gate U2 outputs a low level signal to the T1In pin of the level conversion chip U1, and because of the characteristic of the level conversion chip U1, the T1Out pin of the level conversion chip U1 outputs a high level signal, if the processor U0 inputs a high level signal to the first input end of the and gate U3 of the cashbox control circuit, the cashbox control circuit outputs a high level signal, and at this time, the level of the T1Out pin of the level conversion chip U1 is equal to the level of the output end of the cashbox control circuit, so that current will not flow into the T1Out pin of the level conversion chip U1, thereby protecting the level conversion chip U1. And under the condition that the level of the RX pin of the connection interface CN1 is zero, if the processor U0 inputs a low level signal to the first input end of the AND gate U3 of the cashbox control circuit so that the cashbox control circuit outputs a low level signal, the signal output by the T1Out pin of the level conversion chip U1 is grounded through the cashbox control circuit so that the TX pin of the connection interface CN1 outputs a low level signal.

The above examples and drawings are not intended to limit the form or form of the present utility model, and any suitable variations or modifications thereof by those skilled in the art should be construed as not departing from the scope of the present utility model.

Claims (7)

1. An automatic identification access device circuit of a cash register, which is characterized in that: the device comprises a connection interface CN1, a processor U0, a level detection circuit, a cashbox control circuit and a serial port level conversion circuit;

the TX pin of the connection interface CN1 is connected with the cashbox control circuit and the serial port level conversion circuit, and the RX pin of the connection interface CN1 is connected with the level detection circuit and the serial port level conversion circuit; the processor U0 is connected with the cashbox control circuit and the serial port level conversion circuit; the level detection circuit is connected with the cashbox control circuit and the serial port level conversion circuit;

the level detection circuit is used for detecting the level of an RX pin of the connection interface CN 1; if the level of the RX pin of the connection interface CN1 is zero, the level detection circuit controls the cashbox control circuit to respond to the signal sent by the processor U0, and meanwhile, the level detection circuit controls the serial level conversion circuit not to respond to the signal sent by the processor U0; if the level of the RX pin of the connection interface CN1 is not zero, the level detection circuit controls the cashbox control circuit not to respond to the signal sent by the processor U0, and at the same time, the level detection circuit controls the serial level conversion circuit to respond to the signal sent by the processor U0.

2. The automated identification access device circuit of a cash register of claim 1, wherein: the level detection circuit comprises a resistor R6, a resistor R7, a resistor R8, a resistor R9, a diode D1, a diode D2, a diode D3, a triode Q4 and a triode Q5;

the positive pole of diode D2 and the negative pole of diode D3 connect the input of level detection circuit, the RX foot of connection interface CN1 is connected to the input of level detection level, the negative pole of diode D2 passes through the base of triode Q5 is connected to resistance R8, the positive pole of diode D3 passes through resistance R9 and connects triode Q4's projecting pole, triode Q4's base and triode Q5's projecting pole ground, diode D1's positive pole and the first end of resistance R6 are connected to triode Q4's collecting electrode and triode Q5's collecting electrode, control power VCC is connected to resistance R6's second end, the output of level detection circuit is connected to diode D1's negative pole and the first end of resistance R7, the output of level detection circuit is connected cashbox control circuit and serial port level conversion circuit, resistance R7's second end ground.

3. The automatic identification access device circuit of a cash register of claim 2, wherein: the level detection circuit further comprises a capacitor C8, a first end of the capacitor C8 is connected with the output end of the level detection circuit, and a second end of the capacitor C8 is grounded.

4. An automatic identification access device circuit for a cash register as claimed in claim 1 or 2, wherein: the cashbox control circuit comprises a resistor R2, a resistor R3, a resistor R5, an AND gate U3, a MOS tube Q2 and a MOS tube Q3;

the first input end of AND gate U3 and the first end of resistance R5 connect the input of cashbox control circuit, processor U0 is connected to cashbox control circuit's input, the output of level detection circuit is connected to cashbox control circuit's second input, MOS pipe Q3's grid is connected to AND gate U3's output, MOS pipe Q3's source and resistance R5's second ground connection, MOS pipe Q2's grid and resistance R3's first end are connected to MOS pipe Q3's drain electrode, driving power VDD is connected to MOS pipe Q2's source and resistance R3's second end, MOS pipe Q2's drain electrode passes through resistance R2 and connects cashbox control circuit's output, interface CN 1's TX foot is connected to cashbox control circuit's output.

5. The automated identification access device circuit of claim 4, wherein: the cashbox control circuit further comprises a capacitor C7, wherein a first end of the capacitor C7 is connected with a second end of the resistor R3 and a source electrode of the MOS tube Q2, and a second end of the capacitor C7 is grounded.

6. An automatic identification access device circuit for a cash register as claimed in claim 1 or 2, wherein: the serial port level conversion circuit comprises a resistor R1, a capacitor C3, a capacitor C5, a capacitor C6, an AND gate U2, a MOS tube Q1 and a level conversion chip U1;

the first input end of the AND gate U2 is connected with the input side transmitting end of the serial level conversion circuit, the input side transmitting end of the serial level conversion circuit is connected with the processor U0, the second input end of the AND gate U2 is connected with the drain electrode of the MOS tube Q1 and the first end of the resistor R1, the second end of the resistor R1 is connected with the control power VCC, the source electrode of the MOS tube Q1 is grounded, the grid electrode of the MOS tube Q1 is connected with the control end of the serial level conversion circuit, the control end of the serial level conversion circuit is connected with the output end of the level detection circuit, the output end of the AND gate U2 is connected with the T1In pin of the level conversion chip U1, the R1Out pin of the level conversion chip U1 is connected with the input side receiving end of the serial level conversion circuit, the input side receiving end of the serial level conversion circuit is connected with the processor U0, the C2+ pin of the level conversion chip U1 is connected with the C2-pin of the level conversion chip U1 through a capacitor C5, the C1+ pin of the level conversion chip U1 is connected with the C1-pin of the level conversion chip U1 through a capacitor C3, the Vcc pin of the level conversion chip U1 and the first end of the capacitor C1 are connected with a control power VCC, the V+ pin of the level conversion chip U1 is connected with the second end of the capacitor C1, the V-pin of the level conversion chip U1 is connected with the first end of the capacitor C6, the GND pin of the level conversion chip U1 and the second end of the capacitor C6 are grounded, the T1Out pin and the R1In pin of the level conversion chip U1 are respectively connected with the output side transmitting end and the output side receiving end of the serial level conversion circuit, and the output side transmitting end and the output side receiving end of the serial level conversion circuit are respectively connected with the TX pin and the RX pin of the connection interface CN 1.

7. The automated identification access device circuit of claim 6, wherein: the serial port level conversion circuit further comprises a capacitor C2, a first end of the capacitor C2 is connected with a Vcc pin of the level conversion chip U1, and a second end of the capacitor C2 is grounded.