CN219760642U - Intelligent bus voltage filtering device applicable to terminal power plant for restraining higher harmonic - Google Patents
Intelligent bus voltage filtering device applicable to terminal power plant for restraining higher harmonic Download PDFInfo
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Abstract
The utility model provides an intelligent bus voltage filtering device applicable to restraining higher harmonic waves of a terminal power plant, which is characterized in that a synchronous satellite second pulse-based timing interval data sampling is adopted, spectrum leakage caused by DFT calculation under the condition of 50HZ of power system frequency deviation and dynamic condition is reduced by a general term filtering method, so that measurement accuracy is improved, the running state of the power system is truly reflected, the attenuation speed is slower than that of other types of filters by adopting a Butterworth filter fourth-order filtering method, but the attenuation speed is quite flat and has no amplitude change, thus the output amplitude of 10 milliseconds can filter the output of interference noise to a great extent, a solid foundation is laid for converting the current rough curve running mode into the whole network optimizing mode for carrying out automatic voltage control operation, and the running of the whole network optimizing mode is beneficial to the improvement of power factors of the power plant and the stability of bus voltage is also improved.
Description
Technical Field
The utility model relates to the field of computer monitoring systems of hydropower plants, in particular to an intelligent bus voltage filtering device applicable to terminal power plants and used for restraining higher harmonics.
Background
At present, a conventional measuring and controlling device transmitter, an alternating current acquisition meter and a comprehensive self-device are mainly adopted for collecting bus voltages of a transformer substation, a convertor station, a hydropower station, a thermal power plant, a new energy power plant and the like, the line bus voltages are collected, higher harmonics generated by power electronic devices in the direct current convertor station are easy to mix into buses for a power plant at the tail end of a direct current transmission line, the conventional measuring and controlling device measures that the first-order filtering is generally adopted by a front-end filter due to low measured sampling rate, so that the bus voltage fluctuation is larger due to interference of higher harmonic signal components, the application of an on-site voltage automatic regulating and controlling device cannot be met, the automatic regulation of the system voltage is extremely unfavorable, the whole reactive power regulation level of a power grid is deeply known by the power plant is influenced, and therefore, the intelligent bus voltage filtering device suitable for suppressing the higher harmonics of the tail end power plant is improved.
Disclosure of Invention
The utility model aims at: aiming at the problems of the prior art, the utility model provides the following technical proposal for realizing the purpose of the utility model: the utility model provides an be suitable for intelligent busbar voltage filter equipment of terminal power plant's suppression higher harmonic, includes the inboard of filter equipment shell body is equipped with embedded processor subassembly, embedded processor subassembly includes circuit motherboard, embedded processor, butterworth filter, median filter, data average filter, circuit motherboard center right side electric connection embedded processor, embedded processor's lower right side electric connection Butterworth filter, butterworth filter's lower surface electric connection median filter, median filter's left surface electric connection data average filter, embedded processor subassembly's surface is equipped with the FPGA subassembly, the front end of filter equipment shell body is equipped with control assembly, the tail end of filter equipment shell body is equipped with signal import subassembly.
As a preferable technical scheme of the utility model, the circuit main board is electrically connected to the inner surface of the filter device outer shell.
As a preferable technical scheme of the utility model, the FPGA component comprises a hardware low-pass filter, a constant interval sampling controller, a pulse signal import port, a time information decoder and a pulse signal export port, wherein the left side of the front end of the circuit main board is electrically connected with the hardware low-pass filter, the lower surface of the hardware low-pass filter is electrically connected with the constant interval sampling controller, the left surface of the hardware low-pass filter is electrically connected with the pulse signal import port, the lower surface of the pulse signal import port is electrically connected with the time information decoder, and the lower surface of the time information decoder is electrically connected with the pulse signal export port.
As a preferable technical scheme of the utility model, the control assembly comprises a control panel, a voltage filtering wave frequency display, a voltage filtering control button, a voltage filtering indicator lamp and a voltage filtering control knob, wherein the front end of the outer shell of the filtering device is electrically connected with the control panel, the upper part of the front end of the control panel is electrically connected with the voltage filtering wave frequency display, the lower surface of the voltage filtering wave frequency display is provided with the voltage filtering control button, the lower surface of the voltage filtering control button is electrically connected with the voltage filtering indicator lamp, and the lower right part of the voltage filtering indicator lamp is electrically connected with the voltage filtering control knob.
As a preferable technical scheme of the utility model, the voltage filtering indicator lamp is provided with three, all of which are transversely arrayed at the front end of the control panel.
As a preferable technical scheme of the utility model, the front end of the voltage filtering wave frequency display is covered with a protective film for protecting the display screen.
As a preferable technical scheme of the utility model, the signal lead-in assembly comprises a voltage system voltage signal lead-in port, a higher harmonic bus connector and a connecting bolt, wherein the tail end of the outer shell of the filtering device is electrically connected with the voltage system voltage signal lead-in port, the left surface of the voltage system voltage signal lead-in port is electrically connected with the higher harmonic bus connector, and the connecting bolt is arranged on the outer surface of the higher harmonic bus connector.
Compared with the prior art, the utility model has the beneficial effects that:
in the scheme of the utility model:
1. by adopting timing interval data sampling based on synchronous satellite second pulse, the spectrum leakage caused by DFT calculation under the condition of 50HZ frequency deviation of the power system and dynamic condition is reduced by using a method of filtering the pass term, so that the measurement accuracy is improved, and the running state of the power system is truly reflected.
2. By using the butterworth filter fourth order filtering method, the attenuation speed is slower than other types of filters, but is quite flat, and no amplitude change exists, so that the amplitude of the output of 10 milliseconds will filter the output of interference noise to a great extent.
3. The average value filtering is carried out on every 10 milliseconds of data, a three-point sliding filtering method is adopted on every minute of data, the sampling precision of bus voltage is greatly improved through the subsequent twice filtering treatment, the processed bus voltage curve is much less in burrs compared with the traditional telemechanical measurement and control system, the curve is smoother, the actual system running condition is more met, a solid foundation is laid for carrying out automatic voltage control operation and converting a current rough curve running mode into a full-network optimizing mode, and the running of the full-network optimizing mode is favorable for improving power factors of a power plant and also improves the stability of the bus voltage.
Description of the drawings:
FIG. 1 is a schematic diagram of a structure provided by the present utility model;
FIG. 2 is a schematic diagram of the structure provided by the present utility model;
FIG. 3 is a schematic view of a partial structure provided by the present utility model;
FIG. 4 is a schematic view of a partial structure provided by the present utility model;
FIG. 5 is a front view of the present utility model;
FIG. 6 is a rear view of the present utility model;
FIG. 7 is a side view of the present utility model;
FIG. 8 is a block flow diagram provided by the present utility model;
fig. 9 is a flowchart provided by the present utility model.
The figures indicate:
1. a filter device housing;
2. an embedded processor component; 201. a circuit motherboard; 202. an embedded processor; 203. butterworth filter; 204. a median filter; 205. a data average filter;
3. an FPGA component; 301. hardware low pass filtering; 302. a fixed-interval sampling controller; 303. a pulse signal introduction port; 304. a time information decoder; 305. a pulse signal derivation port;
4. a control assembly; 401. a control panel; 402. a voltage filtered wave frequency display; 403. a voltage filtering control button; 404. a voltage filtering indicator lamp; 405. a voltage filtering control knob;
5. a signal importing component; 501. a voltage system voltage signal input port; 502. a higher harmonic bus joint; 503. and (5) connecting bolts.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present utility model more clear, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings. It will be apparent that the described embodiments are some, but not all, embodiments of the utility model.
Thus, the following detailed description of the embodiments of the utility model is not intended to limit the scope of the utility model, as claimed, but is merely representative of some embodiments of the utility model. All other embodiments obtained by those skilled in the art without making any creative effort based on the embodiments of the present utility model are within the protection scope of the present utility model, and it should be noted that the embodiments of the present utility model and features and technical solutions of the embodiments of the present utility model may be combined with each other without collision: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
Example 1: referring to fig. 1-9, an intelligent bus voltage filtering device suitable for suppressing higher harmonics in an end power plant includes an embedded processor 202 assembly 2 disposed on an inner side of a filtering device housing 1, the embedded processor 202 assembly 2 includes a circuit board 201, an embedded processor 202, a butterworth filter 203, a median filter 204, and a data mean filter 205, a center right side of the circuit board 201 is electrically connected to the embedded processor 202, a lower right side of the embedded processor 202 is electrically connected to the butterworth filter 203, a lower surface of the butterworth filter 203 is electrically connected to the median filter 204, a left surface of the median filter 204 is electrically connected to the data mean filter 205, an FPGA assembly 3 is disposed on a surface of the embedded processor 202 assembly 2, a control assembly 4 is disposed at a front end of the filtering device housing 1, a signal introducing assembly 5 is disposed at a tail end of the filtering device housing 1, and the circuit board 201 is electrically connected to an inner surface of the filtering device housing 1.
The FPGA component 3 includes a hardware low-pass filter 301, a constant-interval sampling controller 302, a pulse signal input port 303, a time information decoder 304, and a pulse signal output port 305, where the left side of the front end of the circuit board 201 is electrically connected to the hardware low-pass filter 301, the lower surface of the hardware low-pass filter 301 is electrically connected to the constant-interval sampling controller 302, the left surface of the hardware low-pass filter 301 is electrically connected to the pulse signal input port 303, the lower surface of the pulse signal input port 303 is electrically connected to the time information decoder 304, and the lower surface of the time information decoder 304 is electrically connected to the pulse signal output port 305.
The control assembly 4 comprises a control panel 401, a voltage filtering wave frequency display 402, a voltage filtering control button 403, a voltage filtering indicator light 404 and a voltage filtering control knob 405, wherein the front end of the filtering device shell body 1 is electrically connected with the control panel 401, the upper part of the front end of the control panel 401 is electrically connected with the voltage filtering wave frequency display 402, the lower surface of the voltage filtering wave frequency display 402 is provided with the voltage filtering control button 403, the lower surface of the voltage filtering control button 403 is electrically connected with the voltage filtering indicator light 404, and the lower right part of the voltage filtering indicator light 404 is electrically connected with the voltage filtering control knob 405.
The voltage filtering indicator lamp 404 is provided with three uniform transverse linear arrays at the front end of the control panel 401, the front end of the voltage filtering wave frequency display 402 is covered with a protective film for protecting the display screen, the signal guiding-in assembly 5 comprises a voltage system voltage signal guiding-in port 501, a higher harmonic bus joint 502 and a connecting bolt 503, the tail end of the filtering device shell body 1 is electrically connected with the voltage system voltage signal guiding-in port 501, the left surface of the voltage system voltage signal guiding-in port 501 is electrically connected with the higher harmonic bus joint 502, the outer surface of the higher harmonic bus joint 502 is provided with the connecting bolt 503, and the front end utilizes a low-pass filter adopting FPGA module hardware to carry out passband low-pass filtering on original voltage data;
a windowing filtering method aiming at DFT through items is adopted to keep the real low-frequency fluctuation condition of a system bus, so that the interference of higher harmonics is avoided;
wherein w (n) adopts a Blackman window, and h (n) is a low-pass filter coefficient;
sampling at fixed intervals, and analyzing a clock synchronizing signal by an FPGA module based on a second pulse signal of a synchronous satellite; meanwhile, the FPGA module controls the sampling module to synchronously sample according to the clock synchronous signal and the synchronous second pulse.
The data is re-filtered every 10 milliseconds using the butterworth filter fourth order filtering method. The filter adopts an iterative operation mode to filter the sampling value, so that the filtering output value is calculated by using not only the sampling data, but also the filtering result obtained by the previous iterative operation.
The data is subjected to mean value filtering every 10 milliseconds, and a three-point sliding filtering method is adopted for the data every minute, and the data is subjected to subsequent two times of filtering treatment.
The device supports direct 0-20 mA output and IEC61850 protocol output externally, is convenient to access to an automatic voltage regulating system and is also convenient to access to automatic bus voltage regulating software.
Example 2: the bus voltage high-order harmonic filtering device comprises a voltage transformer, a secondary voltage transmitter, a hardware low-pass filter in an FPGA module, a time decoding and sampling module and a triple filtering processing module in an embedded processor, wherein the voltage transformer respectively acquires voltage signals; transmitting the voltage signal to a secondary voltage transmitter, and converting the voltage signal into a measurement signal by the secondary voltage transmitter; the FPGA module carries out low-pass filtering on the measurement signal, analyzes the clock synchronous signal, analyzes the time signal and the synchronous second pulse signal, and synchronously samples at fixed intervals under the control of the synchronous second pulse signal according to the clock synchronous signal; the sampling module adopts an embedded acquisition system and is controlled by the FPGA module. After sampling, the FPGA module sends a signal every 10ms to inform the embedded processor to read sampling data; and the embedded processor performs triple filtering calculation on the sampled data, performs Butterworth filtering calculation on the sampled data once every 10ms to obtain a data point, performs average filtering on 100 data points every 1s to obtain a data point, performs smooth filtering on 3s data points, finally forms a data point every second, and sends the data point to the automatic voltage control system.
The bus voltage higher harmonic filtering method comprises the following steps: step one, initializing related variables in the embedded processor. Initialization of relevant variables inside an embedded processor, comprising: the number of sampling points N of each week wave is selected to be 96 according to the requirements of industry specifications in the example; a voltage scaling factor; primary voltage transformer transformation ratio (220 Kv/0.1Kv in the example); secondary voltage transmitter specification (100V/3V in the example); internal transformation ratio (1 code value represents 0.000030518V); DFT transform coefficients, etc., buffer the prepared sample data, save fixed coefficients of the filter, and obtain other relevant configurations.
And step two, sampling and processing the voltage signals. First, a voltage signal is collected by a voltage transformer at a high-voltage bus of a transformer substation or a power plant.
Then, the collected signals are sent to a secondary voltage transmitter of a busbar voltage filtering system, and the signals are converted into measurement signals of the internal range of the measurement system; the measuring signal range is determined according to the selected hardware, such as + -5V, the FPGA module carries out low-pass filtering on the measuring signal obtained by conversion, and meanwhile, clock synchronization information is analyzed, and a time signal and a synchronous second pulse signal are obtained by analysis;
under the control of synchronous pulse per second signals, the sampling module synchronously samples at a certain time interval, after sampling is completed, the FPGA module sends an interrupt signal to the embedded processor, the embedded processor is informed of acquiring the latest bus voltage sampling data every 10ms, and the embedded processor reads the acquired bus voltage sampling data to perform filtering calculation.
Setting a sampling process: the sampling rate is not lower than 2400Hz; setting N as the number of alternating current sampling points per cycle, N as an integer greater than 48, selecting the sampling rate according to industry specifications, wherein the general rate selection range is greater than 1200Hz, and selecting 2400Hz, wherein the value is comprehensive in consideration of calculated amount and measurement precision in the selection process and meets the requirements of the industry specifications.
The FPGA module controls the sampling module to sample at a certain interval time, the interval time is selected to be 10ms in the embodiment, and the interval time is selected on the basis of considering the transmission speed required by the industry specification and the bus voltage filtering precision, namely, the data filtering is required to be completed for 100 times per second at most; the latest bus voltage must be calculated once within 10 MS.
And step three, filtering treatment. The method specifically comprises the following steps: determination of Butterworth filter order from attenuation
Transfer function
Wherein:
n: filter order
wc: cut-off frequency
wp: passband edge frequency
The amplitude and frequency relationship of the n-order butterworth low-pass filter can be expressed as follows:
wherein: g: the filter amplification; h: a transfer function; j: imaginary units; n: filter order w: signal angular frequency; wc: cut-off frequency.
If wc=1, the above formula is transformed into normalized form as:
determining the order of the filter according to the attenuation
Let 1/a=gn (w)
According to the following:
if w=2, gn (w) =0.005
A=200, n=7.6, taking the integer one greater, i.e. an 8 th order butterworth filter is required;
the method adopts a fourth-order Butterworth filtering method
The filter used for outputting every 10 milliseconds adopts an iterative operation mode to filter the sampling value, so that the filtering output value is calculated by using not only the sampling data, but also the filtering result obtained by the previous iterative operation.
The filter equation is:
F n ＝a 0 X n +a 1 X n-1 +a 2 X n-2 +b 1 F n-1 +b 2 F n-2
wherein:
fn represents the current filtering calculation result
Xn-2 represent real-time sampling data sequence, xn is the latest sampling value
Fn-1 to Fn-2 represent the filtering result sequence obtained by previous operation
a0 to a2 and b1 to b2 represent filter coefficients
The method comprises the steps of outputting 1 data average value filtering every 10 milliseconds, outputting 1 data every 10 milliseconds, performing average value filtering on the calculated data, wherein the calculating function of the device is relatively strong because only 1 second is required to output 1 data, performing bubbling sequencing on 100 output data points, removing the first 10 big data and the first 10 small data of 100 data, performing median filtering on the remaining 80 data points, performing sliding filtering on the output data every 1 second, considering that bus voltage is relatively slow change, performing 3-point sliding filtering on the last step by using the processed data, specifically, outputting data with different weights for three data of the first 2 seconds and the current 1 second, and adopting an IEC61850 communication protocol mode to directly forward bus voltage sampling to an automatic voltage control system.
Working principle: in the using process, the method comprises the steps of initializing related variables in the embedded processor. Initialization of relevant variables inside an embedded processor, comprising: the number of sampling points N of each week wave is selected to be 96 according to the requirements of industry specifications in the example; a voltage scaling factor; primary voltage transformer transformation ratio (220 Kv/0.1Kv in the example); secondary voltage transmitter specification (100V/3V in the example); internal transformation ratio (1 code value represents 0.000030518V); DFT transform coefficients, etc., buffer the prepared sample data, save fixed coefficients of the filter, and obtain other relevant configurations. And step two, sampling and processing the voltage signals. First, a voltage signal is collected by a voltage transformer at a high-voltage bus of a transformer substation or a power plant. Then, the collected signals are sent to a secondary voltage transmitter of a busbar voltage filtering system, and the signals are converted into measurement signals of the internal range of the measurement system; the measuring signal range is determined according to the selected hardware, such as + -5V, the FPGA module carries out low-pass filtering on the measuring signal obtained by conversion, and meanwhile, clock synchronization information is analyzed, and a time signal and a synchronous second pulse signal are obtained by analysis; under the control of synchronous pulse per second signals, the sampling module synchronously samples at a certain time interval, after sampling is completed, the FPGA module sends an interrupt signal to the embedded processor, the embedded processor is informed of acquiring the latest bus voltage sampling data every 10ms, and the embedded processor reads the acquired bus voltage sampling data to perform filtering calculation. Setting a sampling process: the sampling rate is not lower than 2400Hz; setting N as the number of alternating current sampling points per cycle, N as an integer greater than 48, selecting the sampling rate according to industry specifications, wherein the general rate selection range is greater than 1200Hz, and selecting 2400Hz, wherein the value is comprehensive in consideration of calculated amount and measurement precision in the selection process and meets the requirements of the industry specifications. The FPGA module controls the sampling module to sample at a certain interval time, the interval time is selected to be 10ms in the embodiment, and the interval time is selected on the basis of considering the transmission speed required by the industry specification and the bus voltage filtering precision, namely, the data filtering is required to be completed for 100 times per second at most; the latest bus voltage must be calculated once within 10 MS. And step three, filtering treatment. The method specifically comprises the following steps: the butterworth filter order transfer function is determined from the attenuation degree.
Wherein:
n: filter order wc: cut-off frequency wp: passband edge frequency
The amplitude and frequency relationship of the n-order butterworth low-pass filter can be expressed as follows:
wherein:
g: filter magnification H: transfer function j: imaginary unit n: filter order w: signal angular frequency wc: cut-off frequency
If wc=1, the above formula is transformed into normalized form as:
determining the order of the filter according to the attenuation
Let 1/a=gn (w)
According to the following:
if w=2, gn (w) =0.005
A=200, n=7.6, taking the integer one greater, i.e. an 8 th order butterworth filter is required;
the method adopts a fourth-order Butterworth filtering method
The filter used for outputting every 10 milliseconds adopts an iterative operation mode to filter the sampling value, so that the filtering output value is calculated by using not only the sampling data, but also the filtering result obtained by the previous iterative operation.
The filter equation is:
F n ×a 0 X n +a 1 X n-1 +a 2 X n-2 +b 1 F n-1 +b 2 F n-2
wherein: fn represents the current filtering calculation result; xn-2 represent real-time sampling data sequences, xn is the latest sampling value; fn-1 to Fn-2 represent the filtering result sequence obtained by previous operation; a0 to a2 and b1 to b2 represent filter coefficients; the method comprises the steps of outputting 1 data average value filtering every 10 milliseconds, outputting 1 data every 10 milliseconds, performing average value filtering on the calculated data, wherein the calculating function of the device is relatively strong because only 1 second is required to output 1 data, performing bubbling sequencing on 100 output data points, removing the first 10 big data and the first 10 small data of 100 data, performing median filtering on the remaining 80 data points, performing sliding filtering on the output data every 1 second, considering that bus voltage is relatively slow change, performing 3-point sliding filtering on the last step by using the processed data, specifically, outputting data with different weights for three data of the first 2 seconds and the current 1 second, and adopting an IEC61850 communication protocol mode to directly forward bus voltage sampling to an automatic voltage control system.
The above embodiments are only for illustrating the present utility model and not for limiting the technical solutions described in the present utility model, and although the present utility model has been described in detail in the present specification with reference to the above embodiments, the present utility model is not limited to the above specific embodiments, and thus any modifications or equivalent substitutions are made to the present utility model; all technical solutions and modifications thereof that do not depart from the spirit and scope of the utility model are intended to be included in the scope of the appended claims.
Claims (7)
1. The utility model provides an intelligent busbar voltage filter device suitable for terminal power plant suppresses higher harmonic, includes filter device shell body (1), its characterized in that, the inboard of filter device shell body (1) is equipped with embedded processor (202) subassembly (2), embedded processor (202) subassembly (2) include circuit motherboard (201), embedded processor (202), butterworth filter (203), median filter (204), data mean filter (205), circuit motherboard (201) center right side electric connection embedded processor (202), the lower right side electric connection of embedded processor (202) butterworth filter (203), the lower surface electric connection of butterworth filter (203) median filter (204), the left surface electric connection of median filter (204) data mean filter (205), the surface of embedded processor (202) subassembly (2) is equipped with FPGA subassembly (3), the front end of filter device shell body (1) is equipped with control assembly (4), tail end device shell body (1) is equipped with signal lead-in subassembly 5.
2. The intelligent busbar voltage filtering device applicable to terminal power plant for restraining higher harmonics according to claim 1, wherein the circuit board (201) is electrically connected to the inner surface of the filtering device outer shell (1).
3. The intelligent bus voltage filtering device applicable to terminal power plant suppression higher harmonic according to claim 2, wherein the FPGA component (3) comprises a hardware low-pass filter (301), a fixed-interval sampling controller (302), a pulse signal input port (303), a time information decoder (304) and a pulse signal output port (305), the left side of the front end of the circuit board (201) is electrically connected with the hardware low-pass filter (301), the lower surface of the hardware low-pass filter (301) is electrically connected with the fixed-interval sampling controller (302), the left surface of the hardware low-pass filter (301) is electrically connected with the pulse signal input port (303), the lower surface of the pulse signal input port (303) is electrically connected with the time information decoder (304), and the lower surface of the time information decoder (304) is electrically connected with the pulse signal output port (305).
4. The intelligent bus voltage filtering device applicable to terminal power plant suppression higher harmonic according to claim 3, wherein the control component (4) comprises a control panel (401), a voltage filtering wave frequency display (402), a voltage filtering control button (403), a voltage filtering indicator lamp (404) and a voltage filtering control knob (405), the front end of the filtering device shell body (1) is electrically connected with the control panel (401), the upper part of the front end of the control panel (401) is electrically connected with the voltage filtering wave frequency display (402), the lower surface of the voltage filtering wave frequency display (402) is provided with the voltage filtering control button (403), the lower surface of the voltage filtering control button (403) is electrically connected with the voltage filtering indicator lamp (404), and the lower right part of the voltage filtering indicator lamp (404) is electrically connected with the voltage filtering control knob (405).
5. The intelligent bus voltage filtering device applicable to suppression of higher harmonics in an end power plant according to claim 4, wherein three voltage filtering indicator lamps (404) are arranged, and all the voltage filtering indicator lamps are transversely arrayed at the front end of the control panel (401).
6. The intelligent bus voltage filtering device applicable to suppression of higher harmonics in a terminal power plant according to claim 5, wherein a protective film is covered on the front end of the voltage filtering wave frequency display (402) for protecting a display screen.
7. The intelligent bus voltage filtering device applicable to terminal power plants for restraining higher harmonics according to claim 6, wherein the signal introduction component (5) comprises a voltage system voltage signal introduction port (501), a higher harmonic bus connector (502) and a connecting bolt (503), the tail end of the filtering device shell body (1) is electrically connected with the voltage system voltage signal introduction port (501), the left surface of the voltage system voltage signal introduction port (501) is electrically connected with the higher harmonic bus connector (502), and the outer surface of the higher harmonic bus connector (502) is provided with the connecting bolt (503).
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