CN219759613U

CN219759613U - Chip welding structure

Info

Publication number: CN219759613U
Application number: CN202320248198.XU
Authority: CN
Inventors: 赵云飞
Original assignee: Wingtech Communication Co Ltd
Current assignee: Wingtech Communication Co Ltd
Priority date: 2023-02-06
Filing date: 2023-02-06
Publication date: 2023-09-26
Anticipated expiration: 2033-02-06

Abstract

The present disclosure relates to the technical field of electronic devices, and in particular, to a die bonding structure, which includes a die assembly and a pad assembly; the chip assembly comprises a first adhesive layer and a chip arranged on the same side as the first adhesive layer, the bonding pad assembly comprises a second adhesive layer and a bonding pad arranged on the same side as the second adhesive layer, the chip is arranged on one side close to the bonding pad, and the bonding pad corresponds to the chip in position; the chip component and the bonding pad component are adhered through the first adhesive layer and the second adhesive layer to form a butt joint state, a packaging gap is formed between the chip component and the bonding pad component in the butt joint state, and the first adhesive layer and the second adhesive layer are completely filled in the packaging gap.

Description

Chip welding structure

Technical Field

The disclosure relates to the technical field of electronic equipment, and in particular relates to a chip welding structure.

Background

With the progressive development of display technology, micro-LED technology is increasingly applied. Micro-LEDs are small LED chips, and the manufacturing and production process comprises the steps of chip preparation, chip transfer and chip welding.

The chip is generally manufactured by adopting a flip-chip bonding technology to make a chip substrate provided with the chip and a bonding pad substrate provided with a bonding pad butt-joint the chip and the bonding pad, after the butt-joint is finished, the metal electrode on the chip and the bonding pad on the driving plate are welded and connected through hot pressing, and then filling glue is injected into a gap between the array sheet and the driving plate to realize fixation. However, since the voids are small, the flow of the filling compound is limited, so that the voids are difficult to fill, and the risk of dropping out the welding spots between the metal electrode and the bonding pad is greatly increased.

Disclosure of Invention

In order to solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a die bonding structure.

The present disclosure provides a die bonding structure including a die assembly and a pad assembly;

the chip assembly comprises a first adhesive layer and a chip arranged on the same side as the first adhesive layer, the bonding pad assembly comprises a second adhesive layer and a bonding pad arranged on the same side as the second adhesive layer, the chip is arranged on one side close to the bonding pad, and the bonding pad corresponds to the chip in position;

the chip assembly is adhered to the bonding pad assembly through the first adhesive layer and the second adhesive layer to form a butt joint state, a packaging gap is formed between the chip assembly and the bonding pad assembly in the butt joint state, and the first adhesive layer and the second adhesive layer are completely filled in the packaging gap.

Optionally, the chip assembly includes a chip substrate, the chip is disposed on an inner side of the chip substrate, and the first adhesive layer is at least disposed on a portion of the inner side of the chip substrate where the chip is not disposed;

the pad assembly comprises a pad substrate, the pad is arranged on the inner side of the pad substrate, and the second adhesive layer is at least arranged on the part, which is not provided with the pad, of the inner side of the pad substrate.

Optionally, the package gap is formed between the chip substrate and the pad substrate, and the sum of the thicknesses of the first adhesive layer and the second adhesive layer is equal to the thickness of the package gap along the direction of the chip substrate towards the pad substrate.

Optionally, the thickness of the first adhesive layer is higher than the height of the chip, and the thickness of the second adhesive layer is lower than the height of the bonding pad.

Optionally, the number of the chips is at least two, and all the chips are arranged at intervals on the inner side of the chip substrate;

the number of the bonding pads is at least two, and all the bonding pads are distributed on the inner side of the bonding pad substrate at intervals.

Optionally, on the inner side of the chip substrate, gaps among all the chips form a first gap, and on the inner side of the pad substrate, gaps among all the pads form a second gap;

the chips and the bonding pads are arranged in one-to-one correspondence, so that the first gaps and the second gaps are communicated under the butt joint state of the chip assembly and the bonding pad assembly, and the packaging gaps are formed.

Optionally, the chip substrate is a PCB board, a silicon substrate or a glass substrate;

and/or the bonding pad substrate is a PCB, a silicon substrate or a glass substrate.

Optionally, the first adhesive layer and the second adhesive layer are both formed by hydrophilic colloid, or the first adhesive layer and the second adhesive layer are both formed by hydrophobic colloid.

Optionally, the first adhesive layer is formed by heating and curing the hydrophilic colloid or the hydrophobic colloid coated on the chip component;

and/or, the second adhesive layer is formed by heating and curing the hydrophilic colloid or the hydrophobic colloid coated on the pad assembly.

Optionally, the sum of the thicknesses of the first adhesive layer and the second adhesive layer is not more than 25 μm;

wherein the thickness of the first adhesive layer is 10-15 mu m.

Compared with the prior art, the technical scheme provided by the disclosure has the following advantages:

according to the chip welding structure, the first adhesive layer and the second adhesive layer are respectively covered on the corresponding sides of the chip assembly and the bonding pad assembly, after the chip on the chip assembly is in butt joint with the bonding pad on the bonding pad assembly to form a butt joint state, the first adhesive layer of the chip assembly and the second adhesive layer of the bonding pad assembly are mutually adhered, and the packaging gap between the chip assembly and the bonding pad assembly is completely filled, compared with the mode of glue injection after the chip assembly and the bonding pad are in butt joint, the complete filling of glue is effectively ensured, the fixing effect of the chip assembly and the bonding pad assembly is further ensured, loosening is prevented, and the operation is more convenient.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.

In order to more clearly illustrate the embodiments of the present disclosure or the solutions in the prior art, the drawings that are required for the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.

FIG. 1 is a schematic view of a portion of a die assembly of a die bond structure according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a die assembly of a die bond structure according to an embodiment of the present disclosure;

fig. 3 is a schematic view of a part of a pad assembly of a die bonding structure according to an embodiment of the present disclosure;

fig. 4 is a schematic structural view of a pad assembly of a die bonding structure according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of the interfacing of a die assembly and a pad assembly of a die bond structure according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of a die-bonding structure according to an embodiment of the disclosure;

fig. 7 is a flow chart of a method of die bonding of a die bonding structure according to an embodiment of the present disclosure.

1, a chip assembly; 11. a chip; 12. a first adhesive layer; 13. a chip substrate; 2. a pad assembly; 21. a bonding pad; 22. a second adhesive layer; 23. and a pad substrate.

Detailed Description

In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the disclosure.

As shown in fig. 1 to 7, the present embodiment provides a die bonding structure, which includes a die assembly 1 and a pad assembly 2, the die assembly 1 includes a first adhesive layer 12 and a die 11 disposed on the same side as the first adhesive layer 12, the pad assembly 2 includes a second adhesive layer 22 and a pad 21 disposed on the same side as the second adhesive layer 22, and the pad corresponds to the die.

The chip assembly 1 and the pad assembly 2 are adhered by the first adhesive layer 12 and the second adhesive layer 22 to form a butt joint state, and a packaging gap is formed between the chip assembly 1 and the pad assembly 2 in the butt joint state, and the first adhesive layer 12 and the second adhesive layer 22 are completely filled in the packaging gap.

Wherein, the surface of the chip 11 facing the pad assembly 2 is provided with a chip electrode for butting against the pad 21 on the pad assembly 2, specifically, in the butting state, the chip electrode is contacted with the pad 21 after butting the chip assembly 1 and the pad assembly 2, and then the electric connection between the chip 11 and the pad 21 is realized by heating and pressing the whole. The electrodes on the chip 11 may be formed by vapor deposition of metal on the surface of the chip 11.

According to the chip welding structure provided by the embodiment, the first adhesive layer 12 and the second adhesive layer 22 are respectively covered on the corresponding sides of the chip assembly 1 and the bonding pad assembly 2, after the chip 11 on the chip assembly 1 is in butt joint with the bonding pad 21 on the bonding pad assembly 2 to form a butt joint state, the first adhesive layer 12 of the chip assembly 1 and the second adhesive layer 22 of the bonding pad assembly 2 are mutually adhered, and the packaging gap between the chip assembly 1 and the bonding pad assembly 2 is completely filled.

In some embodiments, both the first adhesive layer 12 and the second adhesive layer 22 may be formed by a hydrocolloid. Hydrophilic colloid refers to a colloid that is hydrophilic, i.e., has affinity for water, and is capable of attracting water molecules or dissolving in water. When the first adhesive layer 12 and the second adhesive layer 22 are both hydrophilic colloids, the first adhesive layer 12 and the second adhesive layer 22 can be mutually affinitive, so that intermolecular forces of mutual attraction are generated, and the two adhesive layers can be more easily mixed at the joint, so that a better adhesive effect is achieved. In this embodiment, as the hydrophilic colloid, for example, an aqueous acrylate gel, a polyurethane gel, a polyvinyl alcohol gel, or the like may be used.

In other embodiments, the first adhesive layer 12 and the second adhesive layer 22 may each also be formed by a hydrophobic gel. Hydrophobic colloid means that the colloid is hydrophobic, i.e. the molecules repel water, e.g. a majority of lipid substances. When both the first adhesive layer 12 and the second adhesive layer 22 are hydrophobic colloids, the same effect as that of the first adhesive layer 12 and the second adhesive layer 22 are hydrophilic colloids is obtained. In this embodiment, the hydrophobic colloid may be, for example, an oily acrylate colloid, a silicone colloid, or a shadowless colloid.

As shown in fig. 5, when the first adhesive layer 12 and the second adhesive layer 22 are disposed, the glue of the first adhesive layer 12 and the glue of the second adhesive layer 22 are guaranteed to be of the same kind, so that the glue coated on the surface of the chip 11 or the bonding pad 21 can be attracted and moved to the side of the chip 11 or the bonding pad 21 along the direction 30 of the attractive force of the glue by utilizing the mutual affinity of the two glue, thereby further guaranteeing the connection reliability between the chip 11 and the bonding pad 21.

Since the gel is liquid before forming the adhesive layer, its morphology is unstable, which is unfavorable for flip-chip of the chip assembly 1 and the pad assembly 2. Accordingly, the first adhesive layer 12 may be formed by a hydrophilic or hydrophobic gel coated on the chip assembly 1 and/or the second adhesive layer 22 may be formed by a hydrophilic or hydrophobic gel coated on the pad assembly 2.

The flip-chip method requires one of the chip assembly 1 and the pad assembly 2 to be folded so that the chip 11 can be aligned with the pad 21, and in general, the chip assembly 1 is inverted to be located above the pad assembly 2, and then subjected to butt-joint hot pressing, so that in this embodiment, at least the first adhesive layer 12 needs to be formed by glue heating and curing. The second adhesive layer 22 may be in a liquid state or may be heated to be cured.

In other realizable modes, the adhesive layer can be cured by heating, or can be cured by normal temperature or ultraviolet, so long as the finally formed adhesive layer is ensured to be in a solid state.

In some embodiments, the chip assembly 1 specifically includes a chip substrate 13, the chip 11 is disposed on the inner side of the chip substrate 13, and the first adhesive layer is at least disposed on a portion of the inner side of the chip substrate 13 where no chip is disposed. The pad assembly 2 specifically includes a pad substrate 23, the pad 21 being disposed on the inner side of the pad substrate, and the second adhesive layer being disposed at least on a portion of the inner side of the pad substrate 23 where the pad 21 is not disposed.

On the basis of this, a package gap between the chip assembly 1 and the pad assembly 2 is formed by a gap between the chip substrate 13 and the pad substrate 23.

Illustratively, in order to further ensure that no gap exists in the gap between the chip assembly 1 and the pad assembly 2 after the chip assembly 1 and the pad assembly 2 are bonded by the first adhesive layer 12 and the second adhesive layer 22, the sum of the thicknesses of the first adhesive layer 12 and the second adhesive layer 22 may be equal to the thickness of the package gap in the direction of the chip substrate 13 toward the pad substrate 23. Specifically, regarding the first adhesive layer 12 and the second adhesive layer 22, the volume between the gaps of the chip assembly 1 and the pad assembly 2 can be obtained by calculating the surface areas of the chip assembly 1 and the pad assembly 2 and the total height added after butt-welding the chip 11 and the pad 21, and the required gel volume can be dispensed through the gap volume.

In one implementation, the thickness of the first adhesive layer 12 may be made higher than the height of the chip 11, and the thickness of the second adhesive layer 22 may be made lower than the height of the bonding pad 21. In this way, after the chip assembly 1 is turned over, the colloid on the surface of the chip assembly 1 can naturally flow due to the attractive force between colloid molecules, and the surface of the chip 11 can be protected before bonding.

Illustratively, after the chip assembly 1 and the pad assembly 2 are butted to form a butted state, the sum of the thicknesses of the first adhesive layer 12 and the second adhesive layer 22, i.e., the thickness of the package gap between the chip assembly 1 and the pad assembly 2 is maintained within a range of not more than 25 μm, for example, 20 μm. Wherein the thickness of the first adhesive layer 12 may be maintained between 10 μm and 15 μm, and likewise the thickness of the second adhesive layer 22 may be maintained between 10 μm and 15 μm.

After the chip assembly 1 is inverted over the pad assembly 2, the first adhesive layer 12 and the second adhesive layer 22 may be bonded by thermal compression. Specifically, the first adhesive layer 12 and the second adhesive layer 22 can be melted by the external pressing force and the heating action by means of the hot pressing operation table, so that the adhesion and fusion between the two layers can be better realized. At the same time, the thermal compression also makes the connection between the chip 11 and the pads 21.

In some embodiments, the chip assembly 1 specifically includes at least two chips 11, and all the chips 11 are arranged at intervals on the inner side of the chip substrate 13. Correspondingly, the pad assembly 2 includes at least two pads 21, and all of the pads 21 are arranged at intervals inside the pad substrate 23 and correspond to the positions of the chips 11. The chip 11 corresponds to the size of the bonding pad 21, so that the chip 11 and the bonding pad 21 are conveniently in butt joint.

When at least two chips are provided on the chip substrate 13, a first gap is formed between all the chips 11 inside the chip substrate 13. When at least two pads 21 are provided on the pad substrate 23, gaps between all the pads 23 form a second gap inside the pad substrate 23.

The chips 11 are disposed in one-to-one correspondence with the pads 21 so that the first and second voids communicate with each other in the butted state of the chip assembly 1 and the pad assembly 2 to form a package void.

In some embodiments, the chip substrate 13 may alternatively be a PCB board, a silicon substrate or a glass substrate, and likewise, the pad substrate 23 is a PCB board, a silicon substrate or a glass substrate. Specifically, the device is flexibly selected according to the requirements of operators.

As shown in fig. 7, corresponding to the arrangement of the above-mentioned die bonding structure, the present embodiment further provides a die bonding method, which specifically includes the following steps:

step 101, at least dripping colloid into a gap between every two adjacent chips of a chip substrate, and heating and solidifying to form a first adhesive layer;

step 102, at least dripping colloid into the gap between every two adjacent bonding pads of the bonding pad substrate to form a second adhesive layer;

and 103, inverting the chip substrate above the bonding pad substrate, enabling all the chips to be in counterpoint and butt joint with the bonding pad to form a butt joint state, and then carrying out hot pressing on the chip substrate and the bonding pad substrate to enable the chips to be in welding connection with the bonding pad, and bonding and fusing the first adhesive layer and the second adhesive layer.

In step 102 and step 103, the chip substrate 13 is inverted above the pad substrate 23, so that the first adhesive layer 12 needs to be heated and cured, so that the first adhesive layer 12 is prevented from flowing during the butt joint process, and the uniformity of the colloid distribution is prevented from being affected. In other embodiments, the first adhesive layer 12 may be cured without heating, and the second adhesive layer 22 may be cured with heating, and correspondingly, the pad substrate 23 may be inverted above the chip substrate 13.

It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing is merely a specific embodiment of the disclosure to enable one skilled in the art to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A die bonding structure characterized by comprising a die assembly (1) and a pad assembly (2);

the chip assembly (1) comprises a first adhesive layer (12) and a chip (11) arranged on the same side as the first adhesive layer (12), the bonding pad assembly (2) comprises a second adhesive layer (22) and a bonding pad (21) arranged on the same side as the second adhesive layer (22), the chip (11) is arranged on one side close to the bonding pad (21), and the bonding pad (21) corresponds to the chip (11);

the chip assembly (1) and the bonding pad assembly (2) are adhered by the first adhesive layer (12) and the second adhesive layer (22) to form a butt joint state, a packaging gap is formed between the chip assembly (1) and the bonding pad assembly (2) in the butt joint state, and the first adhesive layer (12) and the second adhesive layer (22) are completely filled in the packaging gap.

2. The die bonding structure according to claim 1, wherein the die assembly (1) includes a die substrate (13), the die (11) is disposed inside the die substrate (13), and the first adhesive layer (12) is disposed at least on a portion of the inside of the die substrate (13) where the die (11) is not disposed;

the bonding pad assembly (2) comprises a bonding pad substrate (23), the bonding pad (21) is arranged on the inner side of the bonding pad substrate (23), and the second adhesive layer (22) is at least arranged on the part, which is on the inner side of the bonding pad substrate (23) and is not provided with the bonding pad (21).

3. The die bonding structure according to claim 2, wherein the package void is formed between the die substrate (13) and the pad substrate (23), and a sum of thicknesses of the first adhesive layer (12) and the second adhesive layer (22) is equal to a thickness of the package void in a direction of the die substrate (13) toward the pad substrate (23).

4. A die bonding structure according to claim 3, wherein the thickness of the first adhesive layer (12) is higher than the height of the die (11), and the thickness of the second adhesive layer (22) is lower than the height of the bonding pad (21).

5. The die bonding structure according to claim 2, wherein the number of the die (11) is at least two, and all the die (11) are arranged at intervals inside the die substrate (13);

the number of the bonding pads (21) is at least two, and all the bonding pads (21) are arranged on the inner side of the bonding pad substrate (23) at intervals.

6. The die bonding structure according to claim 5, wherein gaps between all the dies (11) form a first void inside the die substrate (13), and gaps between all the pads (21) form a second void inside the pad substrate (23);

the chips (11) are arranged in one-to-one correspondence with the bonding pads (21), so that the first gaps and the second gaps are communicated in a butt joint state of the chip assembly (1) and the bonding pad assembly (2) to form the packaging gaps.

7. The die bonding structure according to claim 2, wherein the die substrate (13) is a PCB board, a silicon substrate or a glass substrate;

and/or the pad substrate (23) is a PCB, a silicon substrate or a glass substrate.

8. The die bonding structure according to any one of claims 1 to 7, wherein the first adhesive layer (12) and the second adhesive layer (22) are each formed by a hydrophilic colloid, or the first adhesive layer (12) and the second adhesive layer (22) are each formed by a hydrophobic colloid.

9. The die bonding structure according to claim 8, wherein the first adhesive layer (12) is formed by thermal curing of the hydrophilic colloid or the hydrophobic colloid coated on the die assembly (1);

and/or, the second adhesive layer (22) is formed by heating and curing the hydrophilic colloid or the hydrophobic colloid coated on the pad assembly (2).

10. The die bonding structure according to any one of claims 1 to 7, wherein a sum of thicknesses of the first adhesive layer (12) and the second adhesive layer (22) is not more than 25 μm;

wherein the thickness of the first adhesive layer (12) is 10-15 mu m.