CN219716076U - Computer starting circuit and terminal equipment - Google Patents
Computer starting circuit and terminal equipment Download PDFInfo
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- CN219716076U CN219716076U CN202320768709.0U CN202320768709U CN219716076U CN 219716076 U CN219716076 U CN 219716076U CN 202320768709 U CN202320768709 U CN 202320768709U CN 219716076 U CN219716076 U CN 219716076U
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- 230000000694 effects Effects 0.000 claims abstract description 89
- 239000003990 capacitor Substances 0.000 claims description 9
- 238000000034 method Methods 0.000 abstract description 11
- 239000012636 effector Substances 0.000 description 26
- 238000010586 diagram Methods 0.000 description 6
- 238000004891 communication Methods 0.000 description 3
- 230000005669 field effect Effects 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
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- 238000005516 engineering process Methods 0.000 description 1
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Abstract
The utility model relates to the technical field of computer starting circuits and discloses a computer starting circuit and terminal equipment. The computer starting circuit comprises: the first pin of the logic gate module is connected with the first interface of the control module; the second pin of the logic gate module is connected with the second interface of the control module through the effect module, the output end of the logic gate module is connected with the effect module, and the effect module is connected with the key module. The utility model avoids the phenomenon of randomly pressing the power key in the starting process of the computer so as to ensure that the starting process of the computer can normally run.
Description
Technical Field
The present utility model relates to the field of computer booting circuits, and more particularly, to a computer booting circuit and a terminal device.
Background
At present, along with the continuous progress of technology, computers have become an indispensable part of daily life work of people, and users have put forward higher demands on the starting process of the computers.
At present, the computer is started slowly after the system is activated for the first time or is placed for a long time, namely, logo (mark) can appear only when the screen of the computer is slow, and some Logo can appear only when the screen is about 20-30 s. Therefore, after the computer screen is not bright after the start key is pressed, the user can take actions of clicking the computer power key for a plurality of times or pressing the computer power key for a long time. However, there are great drawbacks in these two ways, and these two ways may cause EC (Embedded Chip)/BIOS (Basic Input Output System, basic input/output system) codes to be disordered, so that the computer system cannot be started or the computer system tamper (i.e. the system stops in a certain state and does not respond to the input/output instruction at all), and referring to fig. 1, fig. 1 is a schematic circuit diagram of the prior art scheme, in which the prior art scheme adopts a power key to connect with EC, when the power key is pressed, there is a low pulse to notify EC to realize the starting action, but this technical scheme cannot solve the above phenomenon that the EC/BIOS codes are disordered due to multiple times of clicking the power key or long pressing the power key, so that the computer system cannot be started or the computer system tamper.
In summary, the existing power key mode is easy to cause code false triggering due to the fact that the power key is pressed randomly, so that the technical problem of computer starting failure exists.
Disclosure of Invention
The utility model mainly aims to provide a computer starting circuit and terminal equipment, which aim to avoid the phenomenon of randomly pressing a power key in the starting process of a computer so as to ensure that the starting process of the computer can normally run.
In order to achieve the above objective, the present utility model provides a computer startup circuit, wherein a first pin of the logic gate module is connected with a first interface of the control module;
the second pin of the logic gate module is connected with the second interface of the control module through the effect module, the output end of the logic gate module is connected with the effect module, and the effect module is connected with the key module.
Optionally, the first interface of the control module is a first end of an APU controller in the control module, and the second interface of the control module is a first end of an embedded chip in the control module.
Optionally, the effect module includes a first effect transistor;
the first pin of the first effect tube is connected with the first end of the embedded chip, the second pin of the first effect tube is grounded, and the third pin of the first effect tube is connected with the second pin of the logic gate module.
Optionally, the effect module further comprises a second effect tube;
the first pin of the second effect tube is connected with the output end of the logic gate module, the second pin of the second effect tube is connected with the key module, and the third pin of the second effect tube is connected with the second end of the embedded chip.
Optionally, the first and second effect transistors are MOSFET devices.
Optionally, the key module is a power key;
the second pin of the power button is connected with the second pin of the second effect tube, and the third pin of the power button and the fourth pin of the power button are respectively grounded.
Optionally, the computer startup circuit further includes: a first resistor, a second resistor, and a third resistor;
an intersection point connected between the third pin of the first effect tube and the second pin of the logic gate module is connected with the first end of the first resistor;
the intersection point connected between the second end of the embedded chip and the third pin of the second effect tube is connected with the first end of the second resistor;
the intersection point connected between the second pin of the power button and the second pin of the second effect tube is connected with the first end of the third resistor;
the second end of the first resistor, the second end of the second resistor and the second end of the third resistor are respectively connected with a preset power supply end.
Optionally, the computer startup circuit further includes: a capacitor;
the second end of the capacitor is connected with the power supply end and the fifth pin of the logic gate module respectively;
the first end of the capacitor is grounded.
Optionally, the logic gate module is an or gate.
In addition, to achieve the above object, the present utility model provides a terminal device including the computer power-on circuit as described above.
In summary, in the present utility model, an effect module and a logic gate module are added, and a first pin of the logic gate module is connected with a first interface of the control module; the second pin of the logic gate module is connected with the second interface of the control module through the effect module, the output end of the logic gate module is connected with the effect module, and the effect module is connected with the key module.
Compared with the prior art, in the starting-up process, the utility model firstly utilizes the first pin of the logic gate module to be connected with the first interface of the control module to obtain a low-level signal input to the logic gate module, then utilizes the second pin of the logic gate module to be connected with the second interface of the control module through the effect module, after the effect module receives the high-level signal output by the second interface of the control module, the other low-level signal input to the logic gate module can be further determined according to the conduction characteristic of the effect module, so that the logic gate module also outputs the low-level signal, then the effect module is determined to be not conducted through the connection between the logic gate module and the effect module, and further, whether the control module is not connected with the key module through the circuit connected with the effect module through the effect module or the key module is adopted, in other words, the control module does not receive the action electric signal of the key module through the effect module, namely, the situation that the computer starting-up code is disturbed or not started up is caused by false triggering due to the fact that the action electric signal of the key module is frequently received in the process of running computer code, the computer starting-up process is effectively avoided, and the normal starting-up process of the computer is effectively ensured through the added effect gate module and the logic gate module.
Drawings
FIG. 1 is a schematic circuit diagram of a prior art solution;
FIG. 2 is a schematic diagram of the overall structure of the computer booting circuit according to the present utility model;
FIG. 3 is a schematic circuit diagram of a computer power-on circuit according to an embodiment of the present utility model;
reference numerals illustrate:
the achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the utility model.
The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present utility model are merely used to explain the relative positional relationship, movement, etc. between the components in a particular posture (as shown in the drawings), and if the particular posture is changed, the directional indicator is changed accordingly.
In the present utility model, unless specifically stated and limited otherwise, the terms "connected," "affixed," and the like are to be construed broadly, and for example, "affixed" may be a fixed connection, a removable connection, or an integral body; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.
Furthermore, descriptions such as those referred to as "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying an order of magnitude of the indicated technical features in the present disclosure. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.
The utility model provides a computer starting circuit.
In an embodiment of the present utility model, referring to fig. 2, fig. 2 is a schematic diagram of a general structure of a computer booting circuit according to the present utility model, the computer booting circuit includes: the device comprises a control module, a logic gate module, a key module and an effect module;
a first pin of the logic gate module 30 is connected to a first interface of the control module 20;
the second pin of the logic gate module 30 is connected with the second interface of the control module 20 through the effect module 10, the output end of the logic gate module 30 is connected with the effect module 10, and the effect module 10 is connected with the key module 40.
In this embodiment, the first interface of the control module 20 is connected to the first pin of the logic gate module 30, and the second interface of the control module 20 is connected to the second pin of the logic gate module 30 through the first effector 101 of the effector module 10; in addition, the fourth pin of the logic gate module 30 (i.e., the fourth pin of the logic gate module 30) is connected to the second effector 102 of the effect module 10, and the Embedded Chip (i.e., EC, embedded Chip) of the control module 20 is connected to the key module 40 through the second effector 102 of the effect module 10.
It should be noted that, the first interface of the control module 20 may be understood as a GPIO terminal of the APU (Accelerated processor unit, AMD platform central processor) controller 201 of the control module 20; the second interface of the control module 20 may be understood as a GPIO terminal of the embedded chip 202 of the control module 20, wherein the slp_s5 terminal of the APU controller 201 is connected with the GPIO terminal of the embedded chip 202 of the control module 20.
In addition, the connection between the first pin of the logic gate module 30 and the first interface of the control module 20 is used to receive the level signal transmitted by the APU controller 201 of the control module 20 through the first pin of the logic gate module 30.
The second pin of the logic gate module 30 is connected to the second interface of the control module 20 through the effect module 10, which can be understood as that the level signal transmitted by the embedded chip 202 of the receiving control module 20 through the effect module 10 is high or low, in other words, the first effector 101 of the effect module 10 receives the level signal of the embedded chip 202 through the connection of the second pin of the logic gate module 30 to the effect module 10, and when the level signal of the received embedded chip 202 is low, the level signal received by the second end of the logic gate module 30 can be determined to be high according to the conducting characteristic of the first effector; when the level signal of the receiving embedded chip 202 is at the high level, the level signal received by the second terminal of the logic gate module 30 may be determined to be at the low level according to the turn-on characteristics of the first transistor.
The output terminal of the logic gate module 30 is connected to the effect module 10, and is configured to send the level signal transmitted by the output terminal of the logic gate module 30 to the second effect transistor 102 of the effect module 10.
The effect module 10 is connected to the key module 40, and is configured to receive an action voltage (i.e., an action electrical signal) of the key module 40 when the level signal of the second effector 102 is at a high level; when the level signal of the second effector 102 is at a low level, the embedded chip 202 of the control module 20 cannot receive the operation voltage (i.e., the operation electrical signal) of the key module 40.
In summary, in the present utility model, the effect module 10 and the logic gate module 30 are added, and the first pin of the logic gate module 30 is connected with the first interface of the control module 20; the second pin of the logic gate module 30 is connected to the second interface of the control module 20 through the effect module 10, the output terminal of the logic gate module 30 is connected to the effect module 10, and the effect module 10 is connected to the key module 40.
Compared with the prior art, in the starting process, the utility model firstly utilizes the first pin of the logic gate module 30 to be connected with the first interface of the control module 20 to obtain a low-level signal input into the logic gate module 30, and then utilizes the second pin of the logic gate module 30 to be connected with the second interface of the control module 20 through the effect module 10, when the effect module 10 receives a high-level signal output by the second interface of the control module 20, the other low-level signal input into the logic gate module 30 can be further determined according to the conduction characteristic of the effect module 10, so that the logic gate module 30 also outputs the low-level signal, and then the effect module 10 is determined to be not conducted through the connection between the logic gate module 30 and the effect module 10, and then the fact that the control module 20 is not connected with the key module 40 through the effect module 10 can be further determined.
Further, in still another embodiment of the computer booting circuit of the present utility model, referring to fig. 3, fig. 3 is a schematic circuit diagram of an embodiment of the computer booting circuit of the present utility model.
In the present utility model, the first interface of the control module 20 is the first end of the APU controller 201 in the control module 20, and the second interface of the control module 20 is the first end of the embedded chip 202 in the control module;
a second end of the APU controller 201 is coupled to a first end of the embedded chip 202.
Further, in some possible embodiments, the effector module comprises a first effector 101;
a first pin of the first effector 101 is connected to a first end of the embedded chip 202, a second pin of the first effector 101 is grounded, and a third pin of the first effector 101 is connected to a second pin of the logic gate module 30.
In this embodiment, the first leg of the first fet 101 is also called the G-terminal (i.e., gate) of the first fet 101; the second leg of the first tube 101 is also known as the S-terminal (i.e., source) of the first tube 101; the third leg of the first transistor 101 is also known as the D-terminal (i.e., drain) of the first transistor 101.
Further, in other possible embodiments, the effector module 10 further includes a second effector 102;
the first pin of the second effector 102 is connected to the output end of the logic gate module 30, the second pin of the second effector 102 is connected to the key module 40, and the third pin of the second effector 103 is connected to the second end of the embedded chip 202.
In this embodiment, the first leg of the second transistor 102 is also called the G-terminal (i.e., gate) of the second transistor 102; the second leg of the second transistor 102 is also known as the S-terminal (i.e., source) of the second transistor 102; the third leg of the second transistor 102 is also known as the D-terminal (i.e., drain) of the second transistor 102.
Further, in some possible embodiments, the first and second effectors 101 and 102 are MOSFET devices.
In this embodiment, a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device can be understood as a Metal-Oxide semiconductor field effect transistor, abbreviated as a Metal-Oxide semiconductor field effect transistor.
Further, in other possible embodiments, the key module 40 is a power key;
in this embodiment, the power button may be represented by a power button.
The second pin of the power button is connected with the second pin of the second effect tube, and the third pin of the power button and the fourth pin of the power button are respectively grounded.
Further, in some possible embodiments, the computer booting circuit further includes: a first resistor, a second resistor, and a third resistor;
an intersection point connected between the third pin of the first effect tube and the second pin of the logic gate module is connected with the first end of the first resistor;
the intersection point connected between the second end of the embedded chip and the third pin of the second effect tube is connected with the first end of the second resistor;
the intersection point connected between the second pin of the power button and the second pin of the second effect tube is connected with the first end of the third resistor;
the second end of the first resistor, the second end of the second resistor and the second end of the third resistor are respectively connected with a preset power supply end.
In this embodiment, the first resistor, the second resistor and the third resistor are used for current limiting in the computer startup circuit of the present utility model.
Further, in other possible embodiments, the computer booting circuit further includes: a capacitor;
the second end of the capacitor is connected with the power supply end and the fifth pin of the logic gate module respectively;
the first end of the capacitor is grounded.
Further, in some possible embodiments, the logic gate module is an or gate.
In the present embodiment, the logic gate module 30 is an or gate, which has a plurality of input terminals and an output terminal, and outputs a high level (logic "1") whenever one of the input terminals is a high level (logic "1"); the output is low (logic "0") only if all inputs are low (logic "0").
In summary, in the present embodiment, when the computer is in the power-off state, the first pin of the first effector 101 is connected to the second interface of the control module 20, so that it can be determined that slp_s5# is output at the GPIO terminal of the embedded chip 202 (i.e., the first terminal of the embedded chip 202), that is, after the first effector 101 receives the slp_s5# signal at the low level, the slp_s5# signal received at the second pin of the logic gate module 30 is at the high level (i.e., the second pin of the logic gate module 30 receives the high level signal) according to the on characteristic of the first effector 101, and in addition, the first pin of the logic gate module 30 is connected to the first interface of the control module 20, so that it can be determined that the apu_gpio transmitted from the GPIO terminal of the APU controller to the first pin of the logic gate module 30 in the control module 20 is at the low level. Thus, after determining that the second pin of the logic gate module 30 receives the high level signal and the first pin of the logic gate module 30 receives the low level signal, the pwr_ctl transmitted by the fourth pin of the logic gate module 30 (i.e., the output terminal of the logic gate module 30) can be determined to be the high level signal according to the characteristics that the logic gate module is an or gate. The output end of the logic gate module 30 is connected with the effect module 10, and after the second effect tube 102 of the effect module 10 receives the pwr_ctl as the high level signal, the second effect tube 102 is in an on state, so that it can be determined that the embedded chip 202 of the control module 20 can receive the action electric signal of the key module 40.
In yet another embodiment, when the computer is in the power-on operation process, i.e., after the user clicks the button module 40, the button module has an action voltage, the embedded chip 202 in the control module 20 obtains a high level signal, so that the GPI O end of the embedded chip 202 outputs the level signal of slp_s5# from low to high (i.e., slp_s5# is a high level signal), and then the slp_s5 output through the third pin of the first effector 101 can be determined to be a low level signal according to the conduction characteristic of the first effector 101 (i.e., the second pin of the logic gate module 30 receives the low level signal), and in addition, the apu_gpio transmitted from the GP IO end of the embedded chip 202 to the first pin of the logic gate module 30 in the control module 20 is a low level signal through the connection of the second pin of the logic gate module 30 and the control module 20. In other words, after it is determined that the second pin of the logic gate module 30 receives the low level signal and the first pin of the logic gate module 30 receives the low level signal, the pwr_ctl transmitted by the fourth pin of the logic gate module 30 (i.e., the output terminal of the logic gate module 30) may be determined as the low level signal according to the characteristics that the logic gate module is an or gate. The output end of the logic gate module 30 is connected with the effect module 10, after the second effect tube 102 of the effect module 10 receives the pwr_ctl as the low level signal, the second effect tube 102 will not be turned on, so that it can be determined that the embedded chip 202 of the control module 20 cannot receive the action electric signal of the key module 40, that is, how to click the key module 40 at this time will not notify the embedded chip 202 of the control module 20 that the action voltage occurs in the key module 40 through the branch connected with the second effect tube 102, in other words, no communication exists between the embedded chip 202 and the key module 40. The computer system continues to run the boot code until the Logo appears on the computer screen. When the Logo appears on the computer screen, at this time, the computer is in a system running state, the APU controller 201 transmits an apu_gpio high level signal to the first pin of the logic gate module 30, so as to determine that the pwr_ctl output by the fourth pin of the logic gate module 30 (i.e., the fourth pin of the logic gate module 30) is pulled up (i.e., the high level signal), so that it is determined that the second effector 102 of the effector module 10 is changed from a non-conducting state to an open state according to the pwr_ctl being high level, that is, the communication between the embedded chip 202 and the key module 40 is implemented, and normal use of the key module 40 under the system can be ensured.
In addition, the utility model also provides terminal equipment. The terminal equipment of the embodiment of the utility model can be applied to the computer starting circuit of any one of the above.
The foregoing description is only of the preferred embodiments of the present utility model and is not intended to limit the scope of the utility model, and all equivalent structural changes made by the description of the present utility model and the accompanying drawings or direct/indirect application in other related technical fields are included in the scope of the utility model.
Claims (10)
1. A computer boot circuit, the computer boot circuit comprising: the device comprises a control module, a logic gate module, a key module and an effect module;
the first pin of the logic gate module is connected with the first interface of the control module;
the second pin of the logic gate module is connected with the second interface of the control module through the effect module, the output end of the logic gate module is connected with the effect module, and the effect module is connected with the key module.
2. The computer startup circuit of claim 1, wherein the first interface of the control module is the first end of an APU controller in the control module, and the second interface of the control module is the first end of an embedded chip in the control module;
the second end of the APU controller is connected with the first end of the embedded chip.
3. The computer boot circuit of claim 2, wherein the effect module comprises a first effect transistor;
the first pin of the first effect tube is connected with the first end of the embedded chip, the second pin of the first effect tube is grounded, and the third pin of the first effect tube is connected with the second pin of the logic gate module.
4. The computer boot circuit of claim 3, wherein the effect module further comprises a second effect transistor;
the first pin of the second effect tube is connected with the output end of the logic gate module, the second pin of the second effect tube is connected with the key module, and the third pin of the second effect tube is connected with the second end of the embedded chip.
5. The computer power-on circuit of claim 4, wherein the first and second transistors are MOSFET devices.
6. The computer boot-up circuit of claim 4, wherein the key module is a power key;
the second pin of the power button is connected with the second pin of the second effect tube, and the third pin of the power button and the fourth pin of the power button are respectively grounded.
7. The computer boot circuit as recited in claim 6 wherein said computer boot circuit further comprises: a first resistor, a second resistor, and a third resistor;
an intersection point connected between the third pin of the first effect tube and the second pin of the logic gate module is connected with the first end of the first resistor;
the intersection point connected between the second end of the embedded chip and the third pin of the second effect tube is connected with the first end of the second resistor;
the intersection point connected between the second pin of the power button and the second pin of the second effect tube is connected with the first end of the third resistor;
the second end of the first resistor, the second end of the second resistor and the second end of the third resistor are respectively connected with a preset power supply end.
8. The computer boot circuit as recited in claim 7 wherein said computer boot circuit further comprises: a capacitor;
the second end of the capacitor is connected with the power supply end and the fifth pin of the logic gate module respectively;
the first end of the capacitor is grounded.
9. The computer boot circuit of claim 1, wherein the logic gate module is an or gate.
10. A terminal device, characterized in that it comprises a computer power-on circuit according to any of claims 1-9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320768709.0U CN219716076U (en) | 2023-04-04 | 2023-04-04 | Computer starting circuit and terminal equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202320768709.0U CN219716076U (en) | 2023-04-04 | 2023-04-04 | Computer starting circuit and terminal equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219716076U true CN219716076U (en) | 2023-09-19 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202320768709.0U Active CN219716076U (en) | 2023-04-04 | 2023-04-04 | Computer starting circuit and terminal equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219716076U (en) |
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2023
- 2023-04-04 CN CN202320768709.0U patent/CN219716076U/en active Active
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