CN219697720U - Multi-path CAMLINK input/output interface device based on FPGA control - Google Patents

Abstract

The utility model discloses a multipath CAMLINK input/output interface device based on FPGA control, comprising: the first CAMLINK signal input port and the first CAMLINK signal output port are simultaneously connected with the first storage unit; the second CAMLINK signal input port and the second CAMLINK signal output port are simultaneously connected with the second storage unit; the first storage unit and the second storage unit are connected with the FPGA main control unit; the first CAMLINK signal input port and the second CAMLINK signal input port are externally connected with a camera; the first CAMLINK signal output port is externally connected with an image acquisition card and is connected with a PC; the second CAMLINK signal output port is externally connected with an image data storage box; the FPGA main control unit is connected with the serial port communication interface; the FPGA main control unit controls the starting and the power-off of the camera through the first CAMLINK signal input port and the second CAMLINK signal input port. The utility model realizes the independent display and storage of four paths of output data, reduces the research and development cost and is more beneficial to the development of an image data transmission research and development system.

Description

Multi-path CAMLINK input/output interface device based on FPGA control

Technical Field

The utility model belongs to the technical field of digital electronic circuits, and relates to a multipath CAMLINK input/output interface device based on FPGA control.

Background

The common real-time transmission of image data generally only integrates 1 path of CAMLINK input/output interface, when the multi-path Camera image data needs to be processed, a plurality of CAMLINK input/output interface devices are needed to be combined for use, the combination mode has low efficiency, the problems of occupied space and the like exist, the functions of real-time switching, storage and the like of the multi-path data cannot be realized in a limited space, for example, in a 1 path MIPI standard Camera interface, only 1 path of external device input can be supported, if the multi-path data input/output only increases the device cost, and the output of the image data cannot be effectively controlled.

Disclosure of Invention

The utility model aims to solve the problems that the prior equipment has low combination mode efficiency and large occupied space and cannot realize real-time switching of multiple paths of data in a limited space when multiple paths of data are input and output in the prior art, and provides a multiple paths of CAMLINK input and output interface device based on FPGA control.

In order to achieve the purpose, the utility model is realized by adopting the following technical scheme:

a multi-path CAMLINK input-output interface device based on FPGA control, comprising: the device comprises a signal input port, a signal output port, a power supply interface, an FPGA main control unit, a first storage unit and a second storage unit;

the signal input port comprises a first CAMLINK signal input port and a second CAMLINK signal input port; the signal output port comprises a first CAMLINK signal output port and a second CAMLINK signal output port; the first CAMLINK signal input port and the first CAMLINK signal output port are simultaneously connected with the first storage unit; the second CAMLINK signal input port and the second CAMLINK signal output port are simultaneously connected with the second storage unit; the first storage unit and the second storage unit are respectively connected with the FPGA main control unit; the first CAMLINK signal input port and the second CAMLINK signal input port are externally connected with a camera; the first CAMLINK signal output port is externally connected with an image acquisition card and is connected with a PC; the second CAMLINK signal output port is externally connected with an image data storage box; the FPGA main control unit is connected with the serial port communication interface and receives external instructions through the serial port communication interface; the power supply interface is externally connected with an independent power supply and supplies power to the FPGA main control unit, the signal input port and the signal output port; the FPGA main control unit controls the starting and the power-off of the camera through the first CAMLINK signal input port and the second CAMLINK signal input port.

The utility model further improves that:

further, the first CAMLINK signal input port includes CAMLINK interface 1 and CAMLINK interface 2, and the second CAMLINK signal input port includes CAMLINK interface 3 and CAMLINK interface 4; the CAMLINK interface 1, CAMLINK interface 2, CAMLINK interface 3 and CAMLINK interface 4 are respectively externally connected with a camera.

Further, the first CAMLINK signal output port includes a CAMLINK interface 5 and a CAMLINK interface 6; the second CAMLINK signal output port comprises a CAMLINK interface 7 and a CAMLINK interface 8; the CAMLINK interface 5 and the CAMLINK interface 6 are externally connected with an image acquisition card and are connected with a PC; the CAMLINK interface 7 and CAMLINK interface 8 are externally connected to an image data storage box.

Furthermore, each of the CAMLINK interface 1, the CAMLINK interface 2, the CAMLINK interface 3 and the CAMLINK interface 4 comprises a CAMLINK interface chip; the model of the CAMLINK interface chip is MIPI CSI.

Further, the CAMLINK interface chips in the CAMLINK interface 1 and the CAMLINK interface 2 receive image data output by cameras corresponding to the CAMLINK interface 1 and the CAMLINK interface 2 and store the image data in the first storage unit; the CAMLINK interface chips in the CAMLINK interface 3 and the CAMLINK interface 4 receive the image data output by the cameras corresponding to the CAMLINK interface 3 and the CAMLINK interface 4 and store the image data in the second storage unit.

Further, the first storage unit sends image data collected by the camera corresponding to the first CAMLINK signal input port to the image collection card through the CAMLINK interface 5 and the CAMLINK interface 6 under the control of the FPGA main control unit; and the second storage unit sends the image data acquired by the camera corresponding to the second CAMLINK signal input port to the image data storage box through the CAMLINK interface 7 and the CAMLINK interface 8 under the control of the FPGA main control unit.

Further, the first memory cell and the second memory cell use MT41J64M16JT-125.

Further, the serial communication interface employs RS422.

Further, the model of the FPGA is XC7K325T-1FBG900I.

Compared with the prior art, the utility model has the following beneficial effects:

the utility model respectively connects the image data received by the first CAMLINK signal input port and the second CAMLINK signal input port to the first storage unit and the second storage unit through the FPGA main control unit, and the FPGA main control unit realizes real-time output or storage of the image data input by different interfaces. The four paths of data are not affected mutually, the four paths of output data can be independently displayed and stored, the research and development cost is reduced, and the development of an image data transmission research and development system is improved.

Drawings

For a clearer description of the technical solutions of the embodiments of the present utility model, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present utility model and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of the structure of a multi-channel CAMLINK input/output interface device based on FPGA control of the present utility model;

fig. 2 is a block diagram of the structure of the multi-path CAMLINK input/output interface device based on FPGA control according to the present utility model.

Wherein, 9-FPGA main control unit; 10-a power supply interface; 11-a first memory cell; 12-a second storage unit; 13-serial communication interface.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments of the present utility model. The components of the embodiments of the present utility model generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the utility model, as presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.

In the description of the embodiments of the present utility model, it should be noted that, if the terms "upper," "lower," "horizontal," "inner," and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present utility model and simplifying the description, and does not indicate or imply that the apparatus or element to be referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present utility model. Furthermore, the terms "first," "second," and the like, are used merely to distinguish between descriptions and should not be construed as indicating or implying relative importance.

Furthermore, the term "horizontal" if present does not mean that the component is required to be absolutely horizontal, but may be slightly inclined. As "horizontal" merely means that its direction is more horizontal than "vertical", and does not mean that the structure must be perfectly horizontal, but may be slightly inclined.

In the description of the embodiments of the present utility model, it should also be noted that, unless explicitly specified and limited otherwise, the terms "disposed," "mounted," "connected," and "connected" should be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

The utility model is described in further detail below with reference to the attached drawing figures:

referring to fig. 1, the utility model discloses a multipath CAMLINK input/output interface device based on FPGA control, comprising: the device comprises a signal input port, a signal output port, a power supply interface 10, an FPGA main control unit 9, a first storage unit 11 and a second storage unit 12;

the signal input port comprises a first CAMLINK signal input port and a second CAMLINK signal input port; the signal output port comprises a first CAMLINK signal output port and a second CAMLINK signal output port; the first CAMLINK signal input port and the first CAMLINK signal output port are simultaneously connected to the first storage unit 11; the second CAMLINK signal input port and the second CAMLINK signal output port are simultaneously connected to the second storage unit 12; the first storage unit 11 and the second storage unit 12 are respectively connected with the FPGA main control unit 9; the first CAMLINK signal input port and the second CAMLINK signal input port are externally connected with a camera; the first CAMLINK signal output port is externally connected with an image acquisition card and is connected with a PC; the second CAMLINK signal output port is externally connected with an image data storage box; the FPGA main control unit 9 is connected with the serial port communication interface 13, and the FPGA main control unit 9 receives external instructions through the serial port communication interface 13; the power supply interface 10 is externally connected with an independent power supply and supplies power to the FPGA main control unit 9, the signal input port and the signal output port; the FPGA master control unit 9 controls the start and power off of the camera through the first CAMLINK signal input port and the second CAMLINK signal input port.

The first CAMLINK signal input port comprises a CAMLINK interface 1 and a CAMLINK interface 2, and the second CAMLINK signal input port comprises a CAMLINK interface 3 and a CAMLINK interface 4; the CAMLINK interface 1, CAMLINK interface 2, CAMLINK interface 3 and CAMLINK interface 4 are respectively externally connected with a camera.

The first CAMLINK signal output port comprises a CAMLINK interface 5 and a CAMLINK interface 6; the second CAMLINK signal output port comprises a CAMLINK interface 7 and a CAMLINK interface 8; the CAMLINK interface 5 and the CAMLINK interface 6 are externally connected with an image acquisition card and are connected with a PC; the CAMLINK interface 7 and CAMLINK interface 8 are externally connected to an image data storage box.

The CAMLINK interface 1, the CAMLINK interface 2, the CAMLINK interface 3 and the CAMLINK interface 4 all comprise CAMLINK interface chips; the model of the CAMLINK interface chip is MIPI CSI.

The CAMLINK interface chips in the CAMLINK interface 1 and the CAMLINK interface 2 receive the image data output by the cameras corresponding to the CAMLINK interface 1 and the CAMLINK interface 2 and store the image data in the first storage unit 11; the CAMLINK interface chips in CAMLINK interface 3 and CAMLINK interface 4 receive image data output from cameras corresponding to CAMLINK interface 3 and CAMLINK interface 4 and store the image data in second storage unit 12.

Under the control of the FPGA main control unit 9, the first storage unit 11 sends image data acquired by a camera corresponding to the first CAMLINK signal input port to an image acquisition card through the CAMLINK interface 5 and the CAMLINK interface 6; the second storage unit 12 sends the image data collected by the camera corresponding to the second CAMLINK signal input port to the image data storage box through the CAMLINK interface 7 and the CAMLINK interface 8 under the control of the FPGA main control unit 9.

The first storage unit 11 and the second storage unit 12 adopt MT41J64M16JT-125; the serial port communication interface 13 adopts RS422; the model of the FPGA is XC7K325T-1FBG900I.

The four-way Camera input interface and output interface 12226-5150-00FR input and output adopt a Camera Link Base mode, the CAMLINK Link interface is mainly used for an interface between a digital Camera and an image acquisition card, has uniform physical plug-in and cable definition, can be physically interconnected as long as the Camera and the image card accord with the CAMLINK Link standard, has three modes, namely BASE, MEDIUM, FULL modes, mainly adopts a BASE mode, has no other design defects, and can use other interface modes as long as the design requirement meets the requirement.

The first memory unit 11 and the second memory unit 12 adopt DDR3 (MT 41J64M16 JT-125), DDR3 is a common computer memory specification, the performance and memory performance of the DDR3 are far superior to those of other memory units, the energy consumption is lower than those of other memory units while the performance is ensured, the transmission rate is high, and the memory can meet the design requirement.

The FPGA model in the FPGA control unit is not XC7K325T-1FBG900I, the main control unit selected by design has high-end performance, and compared with the previous generations of FPGAs, the power consumption is reduced by half, the performance is improved by at least 2 times, and the requirements of the performance, serial connection function and advanced storage interface of the system design can be met.

In the design scheme, the FPGA is used as a main control unit, multiple paths of CAMLINK input data are transmitted to a storage unit for storage through a CAMLINK interface unit by controlling a first storage unit 11 and a second storage unit 12, four paths of image data are stored in the storage unit at the same time, the four paths of image data are controlled by the FPGA according to design requirements, two paths of image data are connected to an image data acquisition card, real-time display is performed by using a PC, and the other two paths of image data are connected to an image data storage box, so that the storage of the image data is completed.

The serial port communication interface 13 adopts RS422, RS422 has standard digital interface circuit characteristics, adopts independent sending and receiving channels, does not need to control directions, has a maximum transmission distance of 1219 meters and a maximum transmission rate of 10M/BS, has better performance than RS232, and belongs to common communication interface units.

Camera 1, camera 2, camera 3 and camera 4 are connected to the CAMLINK input interface, respectively, wherein camera 1 and camera 2 are connected to CAMLINK interface 1 and CAMLINK interface 2, respectively, two sets of data are connected to the first memory unit 11, camera 3 and camera 4 are connected to CAMLINK interface 3 and CAMLINK interface 4, respectively, and two sets of data are connected to the second memory unit 12. The first storage unit 11 and the second storage unit 12 are respectively connected with the FPGA, the first storage unit 11 and the second storage unit 12 are controlled by the FPGA to store and control four paths of data, the first storage unit 11 and the second storage unit 12 are controlled by the FPGA to process stored image data, the first storage unit 11 and the CAMLINK interface 5 are connected with the CAMLINK interface 6, the second storage unit 12 and the CAMLINK interface 7 are connected with the CAMLINK interface 8, the CAMLINK interface 5 and the CAMLINK interface 6 are connected to an image acquisition card and connected with a PC, the CAMLINK interface 7 and the CAMLINK interface 8 are connected with an image data storage box through PC real-time display, the serial communication interface 13 mainly realizes the functions of powering up and powering down a camera, and the FPGA main control unit 9 is connected with the serial communication interface 13.

As shown in fig. 2, after the whole control system is powered by an external independent power supply, the FPGA starts to work normally, a power-on instruction is sent by using the communication interface, after the FPGA receives the power-on instruction, the camera is controlled to power on, the camera starts to work normally, the FPGA controls the storage unit to start to receive the camera data, the camera transmits the image data to the storage unit, and then the image data is respectively transmitted to the PC and the acquisition card through the FPGA control.

The FPGA is a main control unit, the FPGA powers on the four-way camera by receiving a power-on instruction sent by the communication unit, receives a power-off instruction sent by the communication unit, powers off the four-way camera, controls the four-way camera independently, the FPGA controls the power-on and the power-off of the camera 1 by being connected with the CAMLINK interface 1, controls the power-on and the power-off of the camera 2 by being connected with the CAMLINK interface 2, controls the power-on and the power-off of the camera 3 by being connected with the CAMLINK interface 3, and controls the power-on and the power-off of the camera 4 by being connected with the CAMLINK interface 4, the input interface unit transmits image data to the storage unit through the CAMLINK interface, the storage unit sends the four-way image data to the acquisition card and the storage box through the output interface unit under the control of the FPGA, and after the acquisition is completed, the FPGA is used as a control unit to send the power-off instruction at the communication serial port, and the whole operation flow is completed.

The above is only a preferred embodiment of the present utility model, and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims (9)

1. A multi-path CAMLINK input-output interface device based on FPGA control, comprising: the device comprises a signal input port, a signal output port, a power supply interface (10), an FPGA main control unit (9), a first storage unit (11) and a second storage unit (12);

the signal input port comprises a first CAMLINK signal input port and a second CAMLINK signal input port; the signal output port comprises a first CAMLINK signal output port and a second CAMLINK signal output port; the first CAMLINK signal input port and the first CAMLINK signal output port are simultaneously connected with a first storage unit (11); the second CAMLINK signal input port and the second CAMLINK signal output port are simultaneously connected with a second storage unit (12); the first storage unit (11) and the second storage unit (12) are respectively connected with the FPGA main control unit (9); the first CAMLINK signal input port and the second CAMLINK signal input port are externally connected with a camera; the first CAMLINK signal output port is externally connected with an image acquisition card and is connected with a PC; the second CAMLINK signal output port is externally connected with an image data storage box; the FPGA main control unit (9) is connected with the serial port communication interface (13), and the FPGA main control unit (9) receives external instructions through the serial port communication interface (13); the power supply interface (10) is externally connected with an independent power supply and supplies power to the FPGA main control unit (9), the signal input port and the signal output port; the FPGA main control unit (9) controls the starting and the power-off of the camera through a first CAMLINK signal input port and a second CAMLINK signal input port.

2. A multi-path CAMLINK input/output interface device based on FPGA control as claimed in claim 1 wherein said first CAMLINK signal input port comprises CAMLINK interface 1 and CAMLINK interface 2 and said second CAMLINK signal input port comprises CAMLINK interface 3 and CAMLINK interface 4; the CAMLINK interface 1, the CAMLINK interface 2, the CAMLINK interface 3 and the CAMLINK interface 4 are respectively externally connected with a camera.

3. A FPGA control-based multi-path CAMLINK input/output interface device according to claim 2, wherein said first CAMLINK signal output port comprises CAMLINK interface 5 and CAMLINK interface 6; the second CAMLINK signal output port comprises a CAMLINK interface 7 and a CAMLINK interface 8; the CAMLINK interface 5 and the CAMLINK interface 6 are externally connected with an image acquisition card and are connected with a PC; the CAMLINK interface 7 and CAMLINK interface 8 are externally connected with an image data storage box.

4. A multi-path CAMLINK input/output interface device based on FPGA control as claimed in claim 3 wherein CAMLINK interface 1, CAMLINK interface 2, CAMLINK interface 3 and CAMLINK interface 4 each comprise a CAMLINK interface chip; the model of the CAMLINK interface chip is MIPI CSI.

5. A multi-path CAMLINK input/output interface device based on FPGA control as claimed in claim 4, wherein CAMLINK interface chips in CAMLINK interface 1 and CAMLINK interface 2 receive image data output from cameras corresponding to CAMLINK interface 1 and CAMLINK interface 2, and store the image data in the first storage unit (11); the CAMLINK interface chips in the CAMLINK interface 3 and the CAMLINK interface 4 receive the image data output by the cameras corresponding to the CAMLINK interface 3 and the CAMLINK interface 4, and store the image data in the second storage unit (12).

6. The multi-path CAMLINK input/output interface device based on FPGA control according to claim 5, wherein the first storage unit (11) sends the image data collected by the camera corresponding to the first CAMLINK signal input port to the image collection card through CAMLINK interface 5 and CAMLINK interface 6 under the control of the FPGA main control unit (9); the second storage unit (12) sends the image data collected by the camera corresponding to the second CAMLINK signal input port to the image data storage box through the CAMLINK interface 7 and the CAMLINK interface 8 under the control of the FPGA main control unit (9).

7. A multi-path CAMLINK input/output interface device based on FPGA control as claimed in claim 6 wherein said first memory unit (11) and second memory unit (12) employ MT41J64M16JT-125.

8. The FPGA control-based multiplexing CAMLINK input-output interface device of claim 1, wherein the serial communication interface (13) employs RS422.

9. The FPGA control-based multiplexing CAMLINK input-output interface device of claim 1, wherein the FPGA is model XC7K325T-1FBG900I.