CN219678437U

CN219678437U - Protection trigger delay latch circuit

Info

Publication number: CN219678437U
Application number: CN202320666701.3U
Authority: CN
Inventors: 李豪; 梁汝锦
Original assignee: Foshan Yinfengshike Technology Co ltd
Current assignee: Foshan Yinfengshike Technology Co ltd
Priority date: 2023-03-30
Filing date: 2023-03-30
Publication date: 2023-09-12
Anticipated expiration: 2033-03-30

Abstract

The utility model relates to the field of overcurrent protection circuits, and particularly discloses a protection trigger delay latch circuit which comprises a driving chip, wherein the driving chip is provided with a 5 th pin, when the driving chip checks a protection condition, the 5 th pin outputs a low-level instantaneous signal, a first power supply charges a first capacitor through an E-B pole of a first triode, the E-C pole of the first triode is conducted, so that the first power supply starts to charge a second capacitor, the second capacitor is conducted through filling voltage of the second capacitor, the C-E pole of the second triode is utilized to pull the level of the 5 th pin of the driving chip down, when the first capacitor is charged, the first triode stops conducting, at the moment, the second triode is continuously conducted through the second capacitor discharging, when the discharging voltage of the second capacitor is lower than the conducting voltage of the second triode, the second triode stops conducting, the latch of the 5 th pin of the driving chip can be stopped, the circuit is restored to be normal, the whole structure is simple and reliable, and the latch chip is not required to be installed, so that the cost is reduced.

Description

Protection trigger delay latch circuit

Technical Field

The utility model relates to the field of overcurrent protection circuits, in particular to a protection trigger delay latch circuit.

Background

At present, a special chip or a comparator chip is generally adopted in an overcurrent protection circuit to realize the purpose of protecting delay latch, and the corresponding chip is required to be installed in the circuit by adopting the mode, so that the corresponding chip is required to be purchased, thereby leading to higher cost and relatively complex structure.

The technical problems to be solved by the utility model are as follows: the protection trigger delay latch circuit with low cost and simple structure is designed.

Disclosure of Invention

In order to overcome the defects of the prior art, the utility model aims to provide a protection trigger delay latch circuit with low cost and simple structure.

The technical scheme adopted by the utility model is as follows: the utility model provides a protection triggers delay latch circuit, including driving chip, driving chip is equipped with the 5 th foot, the 5 th foot is equipped with the latch module who is connected with it electricity, latch module includes first input, first power, first triode and second triode all are equipped with the B utmost point, the C utmost point, the E utmost point, first power is connected with the E utmost point electricity of first triode, the B utmost point of first triode is equipped with the first electric capacity that is connected with it electricity, the C utmost point of first triode is equipped with the second electric capacity that is connected with it electricity, the B utmost point electricity of second electric capacity and second triode is connected.

In some embodiments, the 5 th leg is provided with a first output terminal electrically connected thereto, and the first output terminal is electrically connected to the first input terminal.

In some embodiments, the first output terminal is provided with a first resistor (R2) with one end electrically connected with the first resistor, and the other end of the first resistor is provided with a second power supply electrically connected with the first resistor.

In some embodiments, the first output end is provided with a third capacitor, one end of which is electrically connected with the first output end, and the other end of the third capacitor is grounded.

In some embodiments, the other end of the second capacitor is grounded, and the C-electrode of the second triode is grounded.

In some embodiments, the E pole of the second triode is provided with a second output end electrically connected with the E pole of the second triode, and the second output end is electrically connected with the first output end.

In some embodiments, the first power supply has a second resistor electrically connected thereto, and the second transistor has a third resistor electrically connected thereto at the B-pole.

In some embodiments, the driving chip is further provided with a 1 st pin, a 2 nd pin, a 3 rd pin, a 4 th pin and a 6 th pin in sequence, wherein the 1 st pin is provided with an overcurrent circuit electrically connected with the 1 st pin, the 2 nd pin is grounded, the 3 rd pin is provided with a third output end electrically connected with the 2 nd pin, the 4 th pin is provided with a third power supply electrically connected with the 4 th pin, and the 6 th pin is provided with a second input end electrically connected with the 6 th pin.

The utility model has the following technical effects: when the driving chip checks the protection condition, the 5 th pin outputs a low-level instantaneous signal, at the moment, the first power supply charges the first capacitor through the E-B pole of the first triode, at the moment, the E-C pole of the first triode is conducted, so that the first power supply starts to charge the second capacitor, the voltage of the second capacitor is full, the second triode is conducted, the C-E pole of the second triode is utilized to pull the level of the 5 th pin of the driving chip down, when the first capacitor finishes charging, the first triode stops conducting, at the moment, the second triode is continuously conducted by utilizing the discharge of the second capacitor, at the moment, the second triode stops conducting when the discharge voltage of the second capacitor is lower than the conducting voltage of the second triode, the latching of the 5 th pin of the driving chip can be stopped, the circuit is restored to be normal, the whole structure is simple and reliable, a special latch chip is not required to be installed, and the cost is reduced.

Drawings

FIG. 1 is a schematic diagram of a protection flip-flop latch circuit according to the present utility model.

The reference numbers and designations in the figures correspond to the following: 1. a driving chip; 2. a latch module; 20. a first input; VCC1, a first power supply; q1, a first triode; q2, a second triode; c4, a first capacitor; c5, a second capacitor; 3. a first output terminal; r2, a first resistor; VCC2, a second power supply; c3, a third capacitor; 4. a second output terminal; r3, a second resistor; r4, a third resistor; 5. an overcurrent circuit; 6. a third output; VCC3, third power supply; 7. a second input.

Detailed Description

The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

Referring to fig. 1, the present utility model provides a technical solution: the utility model provides a protection trigger delay latch circuit, including driver chip 1, driver chip 1 is equipped with 1 st foot, 2 nd foot, 3 rd foot, 4 th foot, 5 th foot, 6 th foot in proper order, 5 th foot is equipped with the latch module 2 with be connected electrically with it, 1 st foot is equipped with the overflow circuit 5 with be connected electrically with it, 2 nd foot ground connection, 3 rd foot is equipped with the third output 6 with be connected electrically with it, 4 th foot is equipped with the third power VCC3 with be connected electrically with it, 6 th foot is equipped with the second input 7 with be connected electrically with it, latch module 2 includes first input 20, first power VCC1, first triode Q1 and second triode Q2 all are equipped with the B utmost point, C utmost point and E utmost point, first power VCC1 is connected with the E utmost point of first triode Q1 electrically, still be equipped with the second resistance R3 with be connected electrically with it respectively on the circuit that first power VCC1 and the E utmost point of first triode Q1 are connected, the first power supply VCC1 discharges E pole of the first triode Q1 through the second resistor R3, B pole of the first triode Q1 is provided with a first capacitor C4 electrically connected with the first capacitor C4, C pole of the first triode Q1 is provided with a second capacitor C5 electrically connected with the first capacitor C5, the other end of the second capacitor C5 is grounded, C pole of the second triode Q2 is grounded, the second capacitor C5 is electrically connected with B pole of the second triode Q2, B pole of the second triode Q2 is also provided with a third resistor R4 electrically connected with the second resistor R4, a first output end 3 electrically connected with the first resistor R2 is arranged on the 5 th pin, the first output end 3 is electrically connected with the first input end 20, the other end of the first resistor R2 is provided with a second power supply VCC2 electrically connected with the first output end 3, the other end of the third capacitor C3 is grounded, the electrode E of the second transistor Q2 is provided with a second output terminal 4 electrically connected thereto, and the second output terminal 4 is electrically connected to the first output terminal 3.

When the driving chip 1 detects a protection condition, the 5 th pin of the driving chip 1 outputs a low-level transient signal, the low-level transient signal is transmitted into the latch module 2 through the first input end 20 by the first output end 3, the first power supply VCC1 starts to discharge the first triode Q1 by the second resistor R3, the E-B pole of the first triode Q1 charges the first capacitor C4, the C-E pole of the first triode Q1 is conducted, after the first triode Q1 is conducted, the first power supply VCC1 charges the second capacitor C5 by the second resistor R3 and the C-E pole of the first triode Q1, after the voltage of the second capacitor C5 reaches the B pole conducting voltage of the second triode Q2, the CE pole of the second triode Q2 starts to discharge the first triode Q1, after the first capacitor C4 is charged, the first triode Q1 is cut off, the second capacitor C5 starts to pass through the third resistor R4, the second triode Q2 is continuously discharged until the second triode Q2 is normally discharged, and the cost is reduced.

Finally, it should be noted that the foregoing description is only a preferred embodiment of the present utility model, and the present utility model is not limited to the foregoing embodiments, but may be modified or substituted for some of the features described in the foregoing embodiments. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims

1. The utility model provides a protection triggers delay latch circuit, includes driver chip (1), driver chip (1) is equipped with the 5 th foot, its characterized in that, the 5 th foot is equipped with latch module (2) of being connected with it electricity, latch module (2) are including first input (20), first power (VCC 1), first triode (Q1) and second triode (Q2) all are equipped with B utmost point, C utmost point, E utmost point, the E utmost point electricity of first power (VCC 1) and first triode (Q1) is connected, the B utmost point of first triode (Q1) is equipped with first electric capacity (C4) of being connected with it electricity, the C utmost point of first triode (Q1) is equipped with second electric capacity (C5) of being connected with it electricity, the B utmost point electricity of second electric capacity (C5) and second triode (Q2) is connected.

2. The protection trigger delay latch of claim 1 wherein the 5 th leg has a first output (3) electrically connected thereto, the first output (3) being electrically connected to a first input (20).

3. The protection trigger delay latch circuit according to claim 2, wherein the first output terminal (3) is provided with a first resistor (R2) having one end electrically connected thereto, and the other end of the first resistor (R2) is provided with a second power supply (VCC 2) electrically connected thereto.

4. The protection trigger delay latch circuit according to claim 2, wherein the first output terminal (3) is provided with a third capacitor (C3) having one end electrically connected thereto, and the other end of the third capacitor (C3) is grounded.

5. The protection trigger delay latch of claim 1 wherein the other end of the second capacitor (C5) is grounded and the C-pole of the second transistor (Q2) is grounded.

6. The protection trigger delay latch circuit according to claim 1, characterized in that the E pole of the second transistor (Q2) is provided with a second output terminal (4) electrically connected thereto, the second output terminal (4) being electrically connected to the first output terminal (3).

7. The protection trigger delay latch circuit of claim 1, wherein the first power supply (VCC 1) is provided with a second resistor (R3) electrically connected thereto, and the second transistor (Q2) is provided with a third resistor (R4) electrically connected thereto at the B-pole.

8. The protection triggering delay latch circuit according to claim 1, wherein the driving chip (1) is further provided with a 1 st pin, a 2 nd pin, a 3 rd pin, a 4 th pin and a 6 th pin in sequence, the 1 st pin is provided with an overcurrent circuit (5) electrically connected with the 1 st pin, the 2 nd pin is grounded, the 3 rd pin is provided with a third output end (6) electrically connected with the 2 nd pin, the 4 th pin is provided with a third power supply (VCC 3) electrically connected with the 4 th pin, and the 6 th pin is provided with a second input end (7) electrically connected with the 6 th pin.