CN219678186U - Uninterruptible power supply based on asymmetric half-bridge flyback converter - Google Patents
Uninterruptible power supply based on asymmetric half-bridge flyback converter Download PDFInfo
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Abstract
The utility model discloses an uninterruptible power supply based on an asymmetric half-bridge flyback converter, which comprises an asymmetric flyback converter circuit, an auxiliary power supply, an auxiliary battery circuit, a logic control circuit, a protection circuit, a photovoltaic cell, a first control loop and an output port, wherein the first control loop is connected with the output port; the photovoltaic cell supplies power to the output port through the asymmetric flyback converter circuit, and a protection circuit is arranged between the asymmetric flyback converter circuit and the output port; the auxiliary power supply, the auxiliary battery circuit, the logic control circuit and the first control loop are respectively connected with the asymmetric flyback converter circuit.
Description
Technical Field
The utility model relates to an uninterruptible power supply based on an asymmetric half-bridge flyback converter, and belongs to the technical field of switching power supplies.
Background
Solar energy is considered as an inexhaustible clean energy source, and how to collect solar energy radiated to the ground surface and convert the solar energy into directly usable energy becomes a focus of attention of researchers, so that solar photovoltaic cells are one effective utilization means. However, the electric energy of the photovoltaic cell depends in part on the illumination intensity of the sun, and when the illumination intensity of the sun is weakened, the output of the photovoltaic cell may not meet the requirements of electric equipment, so that a series of serious consequences such as important data loss, equipment failure and the like are caused. The use of Uninterruptible Power Supplies (UPS) can solve these problems well. The uninterrupted power supply can still keep a period of power supply time when the power supply stops supplying, so that people can have time to finish the actions of storing important data or controlling equipment to be closed and the like. It is an important device capable of providing a stable, uninterrupted power supply.
At present, uninterruptible power supplies can be divided into two main types, namely a backup type and an online type according to the working principle. The back-up UPS has simple technology and low cost. Because the utility power directly supplies power to the load, electrical pollution such as surge, peak and the like existing on the utility power grid cannot be eliminated, and the method is only suitable for a plurality of occasions with low requirements on voltage stability. The online UPS can not only stabilize the output voltage and prevent electromagnetic interference, but also can charge the storage battery in a floating way through the charging circuit. But the technology is relatively complex and the cost is relatively high, so the method is suitable for occasions with relatively high requirements on power supply. In order to use the uninterruptible power supply on the photovoltaic cell, the photovoltaic cell is applied to low-power electricity utilization occasions such as illumination, mobile phone charging and the like, and the two types of uninterruptible power supplies are not applicable to the low-power electricity utilization occasions. The uninterrupted power supply which is designed by adopting a proper DC-DC converter and applied to the photovoltaic cell has certain feasibility. The traditional flyback converter is widely applied in power supply design due to the characteristics of simple structure, low cost and the like, however, the switching element of the flyback converter works in a hard switching state, so that the switching element has large on-off loss and lower efficiency.
Disclosure of Invention
In order to solve the defects of the prior art, the utility model aims to provide an uninterruptible power supply based on an asymmetric half-bridge flyback converter, which solves the problems of high on-off loss of a switching element and low utilization rate of electric energy of a photovoltaic cell in the prior art.
In order to achieve the above object, the present utility model adopts the following technical scheme:
an uninterruptible power supply based on an asymmetric half-bridge flyback converter comprises an asymmetric flyback converter circuit, an auxiliary power supply, an auxiliary battery circuit, a logic control circuit, a protection circuit, a photovoltaic cell, a first control loop and an output port;
the photovoltaic cell supplies power to the output port through the asymmetric flyback converter circuit, and a protection circuit is arranged between the asymmetric flyback converter circuit and the output port; the auxiliary power supply, the auxiliary battery circuit, the logic control circuit and the first control loop are respectively connected with the asymmetric flyback converter circuit.
Further, the asymmetric flyback converter circuit comprises resistors R1, R2, R3, R4, R5, R6, an output capacitor C1, a resonant capacitor Cr, a transformer T2, a diode D1, an N-MOS transistor S2, a capacitor Cs1, a capacitor Cs2, an inductance Lr, an inductance Lm, and a second control loop;
the resistors R2 and R3 are sequentially connected between the input voltage Vin+ and the input voltage Vin-, and a voltage sampling end Vin for sampling is arranged between the resistors R2 and R3;
the transformer T2 comprises windings W1, W2 and W3, the winding W1 is connected with an inductor Lm in parallel, two ends of the winding W1 are respectively connected with an inductor Lr and a resonant capacitor Cr, the other end of the inductor Lr is connected with the drain electrode of an N-MOS tube S1, the drain electrode of the N-MOS tube S1 is connected with an input voltage vin+ through a resistor R1, the other end of the resonant capacitor Cr is connected with the source electrode of the N-MOS tube S1, the grid electrode of the N-MOS tube S1 is connected with a complementary PWM control end of a second control loop, and two ends of the capacitor Cs1 are respectively connected with the source electrode and the drain electrode of the N-MOS tube S1;
the drain electrode of the N-MOS tube S2 is connected with the source electrode of the N-MOS tube S1, the source electrode of the N-MOS tube S1 is connected with the input voltage Vin-through a resistor R4, the source electrode of the N-MOS tube S2 is connected with the current sampling end of the second control loop, and the grid electrode of the N-MOS tube S2 is connected with the second control loop;
one end of the winding W2 is connected with the anode of the diode D1, the cathode of the diode D1 is connected with the output voltage Vo, the other end of the winding W2 is connected with the output voltage Vo through a resistor R6 and a resistor R5, the output capacitor C1 is connected with two ends of the resistor R5 in parallel, and the voltage sampling end of the second control loop is connected with the output voltage Vo.
Further, the auxiliary power circuit includes resistors R7, R8, filter capacitors C2, C3, C4, C5, a transformer T1, diodes D2, D3, and an N-MOS transistor S1;
the transformer T1 comprises windings W4, W5 and W6, one end of the winding W4 is connected with voltage Vbus+, and the other end is connected with the drain electrode of the N-MOS tube S1; the source electrode of the N-MOS tube S1 is connected with a voltage Vbus-; one end of the winding W5 is connected with the anode of the diode D2, and the other end is grounded; the cathode of the diode D2 is connected with a 15V power supply; one end of the filter capacitor C3 is connected with the cathode of the diode D2, and the other end of the filter capacitor C is grounded; one end of the filter capacitor C2 is connected with the anode of the diode D2, and the other end of the filter capacitor C is connected with the cathode of the diode D2 through a resistor R7; one end of the winding W6 is grounded, the other end of the winding W is connected with the anode of the diode D3, and the cathode of the diode D3 is connected with a 5V power supply; one end of the filter capacitor C4 is connected with the anode of the diode D3, and the other end is connected with the cathode of the diode D3 through a resistor R8; one end of the filter capacitor C5 is connected with a 5V power supply, and the other end of the filter capacitor C is grounded.
Further, the auxiliary battery circuit includes resistors R9, R10, a capacitor C6, diodes D4, D5, D6, a regulator DW1, a battery bank and a normally open relay RY1;
one end of the resistor R10 is connected with the cathode of the diode D4, the other end of the resistor R10 is connected with the anode of the diode D5, the cathode of the diode D5 is connected with the anode of the diode D6 through the normally open relay RY1, and the cathode of the diode D6 is connected with the asymmetric flyback converter circuit; one end of the capacitor C6 is connected with the cathode of the diode D4, and the other end of the capacitor C is grounded; one end of the resistor R9 is connected with the cathode of the diode D4, and the other end of the resistor R is grounded; one end of the battery pack battery is connected with the normally open relay RY1, and the other end of the battery pack is grounded; the voltage stabilizing tube DW1 is connected in parallel with the two ends of the battery pack battery.
Further, the logic control circuit includes resistors R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, a photo resistor RL1, a diode D8, an op-amp U1A, U1B, U1C, U1D, N-MOS Q1 and an OR gate OR1;
the anode of the diode D8 is connected with the reverse end of the operational amplifier U1A, and the cathode of the diode D8 is connected with the output voltage Vo; one end of the resistor R11 is connected with the reverse end of the operational amplifier U1A, and the other end of the resistor R is connected with a 15V auxiliary power supply; one end of the resistor R12 is connected with the same-direction end of the operational amplifier U1A, and the other end is grounded; one end of the resistor R13 is connected with the same direction end of the operational amplifier U1A, and the other end is connected with a 15V auxiliary power supply. The reverse end of the operational amplifier U1B is connected with an output current Io; one end of the resistor R14 is connected with the homodromous end of the operational amplifier U1B, and the other end of the resistor R is grounded; one end of the resistor R15 is connected with the same direction end of the operational amplifier U1B, and the other end of the resistor R is connected with a 15V auxiliary power supply; the reverse end of the operational amplifier U1C is connected with Vin sampling; one end of the resistor R16 is connected with the same-direction end of the operational amplifier U1C, and the other end of the resistor R is grounded; one end of the resistor R17 is connected with the same direction end of the operational amplifier U1C, and the other end of the resistor R is connected with a 15V auxiliary power supply; the reverse end of the operational amplifier U1D is connected with an input voltage Vin through a photoresistor RL 1; one end of the resistor R18 is connected with the same-direction end of the operational amplifier U1D, and the other end of the resistor R is grounded; one end of the resistor R19 is connected with the same direction end of the operational amplifier U1D, and the other end of the resistor R is connected with a 15V auxiliary power supply; the output end of the operational amplifier U1A, U1B, U1C, U1D is connected with a resistor R20 through an OR gate OR1, and the other end of the resistor R20 is connected with the grid electrode of the N-MOS tube Q1.
Further, the protection circuit includes resistors R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, a photo resistor RL1, diodes D8, D9, an operational amplifier U1E, U F, an N-MOS Q2, OR gate OR2, a BUZZER, and a normally-closed relay RY2;
one end of the resistor R21 is connected with the same-phase end of the operational amplifier U1E, and the other end of the resistor R is connected with the output voltage Vo; one end of the resistor R22 is connected with the same-phase end of the operational amplifier U1E, and the other end of the resistor R is grounded; one end of the resistor R23 is connected with the same-phase end of the operational amplifier U1F, and the other end of the resistor R is connected with the output current Io; one end of the resistor R24 is connected with the same-phase end of the operational amplifier U1F, and the other end of the resistor R is grounded; one end of the resistor R25 is connected with the inverting end of the operational amplifier U1E, and the other end of the resistor R is connected with a 5V power supply; one end of the resistor R26 is connected with the inverting end of the operational amplifier U1F, and the other end of the resistor R is connected with the inverting end of the operational amplifier U1E; one end of the resistor R27 is connected with the inverting end of the operational amplifier U1F, and the other end of the resistor R is grounded; one end of the resistor R28 is connected with the output end of the operational amplifier U1E, and the other end of the resistor R is connected with the input end of the OR gate OR 2; one end of the resistor R29 is connected with the output end of the operational amplifier U1F, and the other end of the resistor R29 is connected with the input end of the OR gate OR 2; the output end of the OR gate OR2 is connected with the grid electrode of the N-MOS tube Q2 through a resistor R30; one end of the BUZZER BUZZZER is connected with a 5V power supply, and the other end of the BUZZER BUZZZER is connected with the drain electrode of the N-MOS tube Q2; the anode of the diode D9 is connected with the drain electrode of the N-MOS tube Q2, and the cathode is connected with a 5V power supply; one end of the normally-closed relay RY2 is connected with a 5V power supply, and the other end is connected with the drain electrode of the N-MOS tube Q2.
The utility model has the beneficial effects that:
1. the uninterrupted power supply adopts the asymmetric flyback converter circuit, so that a circuit switching element works in a soft switching state, the switching loss is reduced, the utilization rate of the electric energy of the photovoltaic cell is improved, and the electric energy is saved.
2. The uninterruptible power supply can detect parameters such as illumination intensity, input voltage and the like, and when the electric energy supply of the photovoltaic battery is insufficient, the auxiliary battery is automatically started to assist in outputting power supply, so that the power supply can still stably and uninterruptedly maintain a period of power supply time.
3. The uninterrupted power supply has overvoltage and overcurrent protection function. Under the abnormal output state, the protection load is automatically disconnected with the output port, so that the safety is high.
Drawings
FIG. 1 is a schematic diagram of the overall architecture of the present utility model;
FIG. 2 is a schematic diagram of an asymmetric half-bridge flyback circuit of the present utility model;
FIG. 3 is a schematic diagram of an auxiliary power circuit of the present utility model;
FIG. 4 is a schematic diagram of an auxiliary battery circuit of the present utility model;
FIG. 5 is a schematic diagram of a logic control circuit of the present utility model;
fig. 6 is a schematic diagram of a protection circuit of the present utility model.
Detailed Description
The utility model is further described below with reference to the accompanying drawings. The following examples are only for more clearly illustrating the technical aspects of the present utility model, and are not intended to limit the scope of the present utility model.
The embodiment discloses an uninterruptible power supply based on an asymmetric half-bridge flyback converter, which comprises an asymmetric flyback converter circuit, an auxiliary power supply, an auxiliary battery circuit, a logic control circuit, a protection circuit, a photovoltaic cell, a first control loop and an output port as shown in figure 1. The photovoltaic cell supplies power to the output port through the asymmetric flyback converter circuit, and a protection circuit is arranged between the asymmetric flyback converter circuit and the output port. The auxiliary power supply, the auxiliary battery circuit and the first control loop of the logic control circuit are respectively connected with the asymmetric flyback converter circuit.
As shown in fig. 2, after the electric energy of the photovoltaic cell is converted by the asymmetric flyback converter circuit, a part of the electric energy is output outwards, and the other part of the electric energy charges the auxiliary battery circuit. The asymmetric flyback converter circuit comprises resistors R1, R2, R3, R4, R5 and R6, an output capacitor C1, a resonant capacitor Cr, a transformer T2, a diode D1, an N-MOS tube S2, a capacitor Cs1, a capacitor Cs2, an inductor Lr, an inductor Lm and a second control loop, wherein the capacitor Cs1 and the capacitor Cs2 are junction capacitors of the two power switching tubes N-MOS tubes S1 and S2, the inductor Lr is leakage inductance of the transformer T2, and the inductor Lm is excitation inductance of the transformer T2.
Resistors R2 and R3 are arranged between the input voltage Vin+ and the input voltage Vin-, and a voltage sampling end Vin is arranged between the resistors R2 and R3 for sampling. The transformer T2 comprises windings W1, W2 and W3, the winding W1 is connected with an inductor Lm in parallel, two ends of the winding W1 are respectively connected with an inductor Lr and a resonant capacitor Cr, the other end of the inductor Lr is connected with a drain electrode of an N-MOS tube S1, the drain electrode of the N-MOS tube S1 is connected with an input voltage vin+ through a resistor R1, the other end of the resonant capacitor Cr is connected with a source electrode of the N-MOS tube S1, a grid electrode of the N-MOS tube S1 is connected with a complementary PWM control end of a second control loop, and two ends of the capacitor Cs1 are respectively connected with the source electrode and the drain electrode of the S1. The drain electrode of the N-MOS tube S2 is connected with the source electrode of the N-MOS tube S1, the source electrode of the N-MOS tube S1 is connected with the input voltage Vin-through a resistor R4, the source electrode of the N-MOS tube S2 is connected with the current sampling end of the second control loop, and the grid electrode of the N-MOS tube S2 is connected with the second control loop. One end of the winding W2 is connected with the anode of the diode D1, and the cathode of the diode D1 is connected with the output voltage Vo; the other end of the winding W2 is connected with the output voltage Vo through a resistor R6 and a resistor R5; the output capacitor C1 is connected in parallel across the resistor R5. The second control loop voltage sampling end is connected with the output voltage Vo.
In order to enable the whole circuit to stably and effectively operate, two paths of auxiliary voltages are generated through the auxiliary source circuit, and stable 15V and 5V supply voltages are provided for an LM5025A chip and other circuits in the control loop circuit, so that the circuits can work normally. The auxiliary power supply circuit comprises resistors R7 and R8, filter capacitors C2 and C3, C4 and C5, a transformer T1, diodes D2 and D3 and an N-MOS tube S1.
The transformer T1 comprises windings W4, W5 and W6, one end of the winding W4 is connected with voltage Vbus+, the other end is connected with the drain electrode of the N-MOS tube S1, and the source electrode of the N-MOS tube S1 is connected with voltage Vbus-; one end of the winding W5 is connected with the anode of the diode D2, the other end of the winding W is grounded, and the cathode of the diode D2 is connected with a 15V power supply; one end of the filter capacitor C3 is connected with the cathode of the diode D2, and the other end of the filter capacitor C is grounded; one end of the filter capacitor C2 is connected with the anode of the diode D2, and the other end of the filter capacitor C is connected with the cathode of the diode D2 through a resistor R7; one end of the winding W6 is grounded, the other end of the winding W is connected with the anode of the diode D3, and the cathode of the diode D3 is connected with a 5V power supply; one end of the filter capacitor C4 is connected with the anode of the diode D3, and the other end is connected with the cathode of the diode D3 through a resistor R8; one end of the filter capacitor C5 is connected with a 5V power supply, and the other end of the filter capacitor C is grounded.
As shown in fig. 4, the photovoltaic cell power charges the battery pack therein via the asymmetric flyback converter circuit, and the logic control circuit controls whether the photovoltaic cell power assists in output power supply. The auxiliary battery circuit comprises resistors R9 and R10, a capacitor C6, diodes D4, D5 and D6, a voltage stabilizing tube DW1, a battery pack battery and a normally-open relay RY1.
One end of the resistor R10 is connected with the cathode of the diode D4, the other end of the resistor R10 is connected with the anode of the diode D5, the cathode of the diode D5 is connected with the anode of the diode D6 through the normally open relay RY1, and the cathode of the diode D6 is connected with the asymmetric flyback converter circuit; one end of the capacitor C6 is connected with the cathode of the diode D4, and the other end of the capacitor C is grounded; one end of the resistor R9 is connected with the cathode of the diode D4, and the other end of the resistor R is grounded; one end of the battery pack battery is connected with the normally open relay RY1, and the other end of the battery pack is grounded; the voltage stabilizing tube DW1 is connected in parallel with the two ends of the battery pack battery.
As shown in fig. 5, the illumination intensity, the input voltage Vin, the output voltage Vo, and the output current Io are detected. Once a certain value is lower than the required level, the logic control circuit can output a corresponding control signal, and auxiliary output power supply of an auxiliary battery is controlled by controlling the on of the MOS transistor Q1. The logic control circuit comprises resistors R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, a photoresistor RL1, a diode D8, an operational amplifier U1A, U1B, U1C, U1D, N-MOS transistor Q1, OR gate OR1.
The anode of the diode D8 is connected with the reverse end of the operational amplifier U1A, and the cathode of the diode D8 is connected with the output voltage Vo; one end of the resistor R11 is connected with the reverse end of the operational amplifier U1A, and the other end of the resistor R is connected with a 15V auxiliary power supply; one end of the resistor R12 is connected with the same-direction end of the operational amplifier U1A, and the other end is grounded; one end of the resistor R13 is connected with the same direction end of the operational amplifier U1A, and the other end is connected with a 15V auxiliary power supply. The reverse end of the operational amplifier U1B is connected with an output current Io; one end of the resistor R14 is connected with the homodromous end of the operational amplifier U1B, and the other end of the resistor R is grounded; one end of the resistor R15 is connected with the same direction end of the operational amplifier U1B, and the other end of the resistor R is connected with a 15V auxiliary power supply. The reverse end of the operational amplifier U1C is connected with Vin sampling; one end of the resistor R16 is connected with the same-direction end of the operational amplifier U1C, and the other end of the resistor R is grounded; one end of the resistor R17 is connected with the same direction end of the operational amplifier U1C, and the other end is connected with a 15V auxiliary power supply. The reverse end of the operational amplifier U1D is connected with an input voltage Vin through a photoresistor RL 1; one end of the resistor R18 is connected with the same-direction end of the operational amplifier U1D, and the other end of the resistor R is grounded; one end of the resistor R19 is connected with the same-direction end of the operational amplifier U1D, and the other end of the resistor R is connected with a 15V auxiliary power supply. The output end of the operational amplifier U1A, U1B, U1C, U1D is connected with a resistor R20 through an OR gate OR1, and the other end of the resistor R20 is connected with the grid electrode of the N-MOS tube Q1.
As shown in fig. 6, by sampling the output voltage Vo and the output current Io to determine whether the overvoltage protection or the overcurrent protection of the circuit is triggered, the logic operation circuit may output a corresponding control signal, and finally, the protection and the alarm effect on the circuit are realized by controlling the on and off of the MOS transistor Q2. The protection circuit comprises resistors R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, a photoresistor RL1, diodes D8 and D9, an operational amplifier U1E, U F, an N-MOS transistor Q2, an OR gate OR2, a BUZZER BUZZZER and a normally-closed relay RY2.
One end of the resistor R21 is connected with the same-phase end of the operational amplifier U1E, and the other end of the resistor R is connected with the output voltage Vo; one end of the resistor R22 is connected with the same-phase end of the operational amplifier U1E, and the other end of the resistor R is grounded; one end of the resistor R23 is connected with the same-phase end of the operational amplifier U1F, and the other end of the resistor R is connected with the output current Io; one end of the resistor R24 is connected with the same-phase end of the operational amplifier U1F, and the other end of the resistor R is grounded; one end of the resistor R25 is connected with the inverting end of the operational amplifier U1E, and the other end of the resistor R is connected with a 5V power supply; one end of the resistor R26 is connected with the inverting end of the operational amplifier U1F, and the other end of the resistor R is connected with the inverting end of the operational amplifier U1E; one end of the resistor R27 is connected with the inverting end of the operational amplifier U1F, and the other end of the resistor R is grounded; one end of the resistor R28 is connected with the output end of the operational amplifier U1E, and the other end of the resistor R is connected with the input end of the OR gate OR 2; one end of the resistor R29 is connected with the output end of the operational amplifier U1F, and the other end of the resistor R29 is connected with the input end of the OR gate OR 2; the output end of the OR gate OR2 is connected with the grid electrode of the N-MOS tube Q2 through a resistor R30; one end of the BUZZER BUZZZER is connected with a 5V power supply, and the other end of the BUZZER BUZZZER is connected with the drain electrode of the N-MOS tube Q2; the anode of the diode D9 is connected with the drain electrode of the N-MOS tube Q2, and the cathode is connected with a 5V power supply; one end of the normally-closed relay RY2 is connected with a 5V power supply, and the other end is connected with the drain electrode of the N-MOS tube Q2.
According to the given hardware architecture diagram, the circuit works generally as follows: after the electric energy of the photovoltaic cell is converted by the asymmetric flyback converter circuit, one path of electric energy is output outwards, and the other path of electric energy charges the auxiliary battery circuit. The logic control circuit detects the illumination intensity, the input voltage Vin, the output voltage Vo, and the output current Io. Under the condition that the photovoltaic cell is sufficient in electric energy, the output of the asymmetric flyback converter circuit is independently used for supplying power to the outside. Once a certain value detected by the logic control circuit is lower than a required standard, the normally open relay RY1 is controlled to be closed, so that the electric energy of the auxiliary battery circuit is fed back to the U1 end of the asymmetric flyback converter circuit, and auxiliary output power supply is realized. The two ends of the relay of the protection circuit are respectively connected to the output end Vout+ and the input end Vin+, when overcurrent or overvoltage is output, the normally closed relay RY2 is disconnected through the protection circuit so as to achieve the purpose of the protection circuit, and meanwhile, an active buzzer in the circuit sounds to give out an alarm.
The working principle of the asymmetric flyback converter circuit is as follows: the photovoltaic cell is connected with the input end of the asymmetric flyback converter circuit, after the electric energy is converted by the circuit, one path of electric energy is output by the voltage Vo, and the other path of electric energy is used for charging the auxiliary battery. The LM5025A chip is powered by an auxiliary power supply 15V, the output voltage Vo and the output current Io of the asymmetric flyback converter circuit are sampled, and the upper MOS tube S1 and the lower MOS tube S2 are controlled to be turned on and off by complementary PWM waves, so that zero-voltage switching of the MOS tubes is realized, and the switching loss is reduced. Meanwhile, when the electric energy supplied by the input end of the circuit is insufficient, the logic control circuit controls the auxiliary battery circuit to feed the electric energy of the auxiliary battery back to the U1 end, and the electric energy is outputted outwards in an auxiliary mode.
The logic circuit works as follows: the auxiliary power supply 15V voltage is divided by resistors R12, R13, R14, R15, R16, R17, R18, R19 to generate reference voltages Va, vb, vc, and Vd. The magnitude of the output voltage Vo is compared with the magnitude of Va, the magnitude of the output current Io is compared with the magnitude of Vb, and the magnitude of the input voltage Vin sampling value is compared with the magnitude of Vc. The input voltage Vin generates a value of the sampling current Is through the photoresistor RL1 to be compared with the value of Vd. When one OR a plurality of values in the detection sampling value are lower than the reference voltage value compared with the detection sampling value, the logic OR gate OR1 outputs a high level to control the MOS tube Q2 to be conducted, the normally open relay RY1 is closed, the electric energy of the auxiliary battery circuit is fed back to the U1 end of the asymmetric flyback converter circuit, and the auxiliary output is used for supplying power.
The foregoing is merely a preferred embodiment of the present utility model, and it should be noted that modifications and variations could be made by those skilled in the art without departing from the technical principles of the present utility model, and such modifications and variations should also be regarded as being within the scope of the utility model.
Claims (5)
1. An uninterruptible power supply based on an asymmetric half-bridge flyback converter is characterized by comprising an asymmetric flyback converter circuit, an auxiliary power supply, an auxiliary battery circuit, a logic control circuit, a protection circuit, a photovoltaic cell, a first control loop and an output port;
the photovoltaic cell supplies power to the output port through an asymmetric flyback converter circuit, and a protection circuit is arranged between the asymmetric flyback converter circuit and the output port; the auxiliary power supply, the auxiliary battery circuit, the logic control circuit and the first control loop are respectively connected with the asymmetric flyback converter circuit;
the asymmetric flyback converter circuit comprises resistors R1, R2, R3, R4, R5 and R6, an output capacitor C1, a resonant capacitor Cr, a transformer T2, a diode D1, an N-MOS tube S2, a capacitor Cs1, a capacitor Cs2, an inductor Lr, an inductor Lm and a second control loop;
the resistors R2 and R3 are sequentially connected between an input voltage vin+ and an input voltage Vin-, and a voltage sampling end Vin is further arranged between the resistors R2 and R3 for sampling;
the transformer T2 comprises windings W1, W2 and W3, wherein the winding W1 is connected with an inductor Lm in parallel, two ends of the winding W1 are respectively connected with an inductor Lr and a resonant capacitor Cr, the other end of the inductor Lr is connected with a drain electrode of an N-MOS tube S1, the drain electrode of the N-MOS tube S1 is connected with an input voltage vin+ through a resistor R1, the other end of the resonant capacitor Cr is connected with a source electrode of the N-MOS tube S1, a grid electrode of the N-MOS tube S1 is connected with a complementary PWM control end of a second control loop, and two ends of the capacitor Cs1 are respectively connected with the source electrode and the drain electrode of the N-MOS tube S1;
the drain electrode of the N-MOS tube S2 is connected with the source electrode of the N-MOS tube S1, the source electrode of the N-MOS tube S1 is connected with the input voltage Vin-through a resistor R4, the source electrode of the N-MOS tube S2 is connected with the current sampling end of the second control loop, and the grid electrode of the N-MOS tube S2 is connected with the second control loop;
one end of the winding W2 is connected with the anode of the diode D1, the cathode of the diode D1 is connected with the output voltage Vo, the other end of the winding W2 is connected with the output voltage Vo through a resistor R6 and a resistor R5, the output capacitor C1 is connected in parallel with two ends of the resistor R5, and the second control loop voltage sampling end is connected with the output voltage Vo.
2. The uninterruptible power supply based on an asymmetric half-bridge flyback converter according to claim 1, wherein the auxiliary power supply circuit comprises resistors R7, R8, filter capacitors C2, C3, C4, C5, a transformer T1, diodes D2, D3 and N-MOS transistors S1;
the transformer T1 comprises windings W4, W5 and W6, one end of the winding W4 is connected with voltage Vbus+, and the other end is connected with the drain electrode of the N-MOS tube S1; the source electrode of the N-MOS tube S1 is connected with a voltage Vbus-; one end of the winding W5 is connected with the anode of the diode D2, and the other end of the winding W is grounded; the cathode of the diode D2 is connected with a 15V power supply; one end of the filter capacitor C3 is connected with the cathode of the diode D2, and the other end of the filter capacitor C is grounded; one end of the filter capacitor C2 is connected with the anode of the diode D2, and the other end of the filter capacitor C is connected with the cathode of the diode D2 through a resistor R7; one end of the winding W6 is grounded, the other end of the winding W6 is connected with the anode of the diode D3, and the cathode of the diode D3 is connected with a 5V power supply; one end of the filter capacitor C4 is connected with the anode of the diode D3, and the other end of the filter capacitor C is connected with the cathode of the diode D3 through a resistor R8; one end of the filter capacitor C5 is connected with a 5V power supply, and the other end of the filter capacitor C is grounded.
3. The uninterruptible power supply based on an asymmetric half-bridge flyback converter according to claim 2, wherein the auxiliary battery circuit comprises resistors R9, R10, capacitor C6, diodes D4, D5, D6, a regulator DW1, a battery bank and a normally open relay RY1;
one end of the resistor R10 is connected with the cathode of the diode D4, the other end of the resistor R10 is connected with the anode of the diode D5, the cathode of the diode D5 is connected with the anode of the diode D6 through the normally open relay RY1, and the cathode of the diode D6 is connected with the asymmetric flyback converter circuit; one end of the capacitor C6 is connected with the cathode of the diode D4, and the other end of the capacitor C is grounded; one end of the resistor R9 is connected with the cathode of the diode D4, and the other end of the resistor R is grounded; one end of the battery pack battery is connected with the normally open relay RY1, and the other end of the battery pack battery is grounded; the voltage stabilizing tube DW1 is connected in parallel with the two ends of the battery pack battery.
4. An uninterruptible power supply based on an asymmetric half-bridge flyback converter according to claim 3, wherein the logic control circuit comprises resistors R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, a photoresistor RL1, a diode D8, an op-amp U1A, U1B, U1C, U1D, N-MOS Q1 and an OR gate OR1;
the anode of the diode D8 is connected with the reverse end of the operational amplifier U1A, and the cathode of the diode D8 is connected with the output voltage Vo; one end of the resistor R11 is connected with the reverse end of the operational amplifier U1A, and the other end of the resistor R is connected with a 15V auxiliary power supply; one end of the resistor R12 is connected with the homodromous end of the operational amplifier U1A, and the other end of the resistor R is grounded; one end of the resistor R13 is connected with the same direction end of the operational amplifier U1A, and the other end of the resistor R is connected with a 15V auxiliary power supply; the reverse end of the operational amplifier U1B is connected with an output current Io; one end of the resistor R14 is connected with the homodromous end of the operational amplifier U1B, and the other end of the resistor R is grounded; one end of the resistor R15 is connected with the same direction end of the operational amplifier U1B, and the other end of the resistor R is connected with a 15V auxiliary power supply; the reverse end of the operational amplifier U1C is connected with Vin sampling; one end of the resistor R16 is connected with the homodromous end of the operational amplifier U1C, and the other end of the resistor R is grounded; one end of the resistor R17 is connected with the same direction end of the operational amplifier U1C, and the other end of the resistor R is connected with a 15V auxiliary power supply; the reverse end of the operational amplifier U1D is connected with an input voltage Vin through a photoresistor RL 1; one end of the resistor R18 is connected with the same-direction end of the operational amplifier U1D, and the other end of the resistor R is grounded; one end of the resistor R19 is connected with the same direction end of the operational amplifier U1D, and the other end of the resistor R is connected with a 15V auxiliary power supply; the output end of the operational amplifier U1A, U1B, U1C, U D is connected with a resistor R20 through an OR gate OR1, and the other end of the resistor R20 is connected with the grid electrode of the N-MOS tube Q1.
5. The uninterruptible power supply based on an asymmetric half-bridge flyback converter according to claim 4, wherein the protection circuit comprises resistors R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, a photoresistor RL1, diodes D8, D9, an op-amp U1E, U F, an N-MOS Q2, an OR gate OR2, a BUZZER, and a normally-closed relay RY2;
one end of the resistor R21 is connected with the same-phase end of the operational amplifier U1E, and the other end of the resistor R is connected with the output voltage Vo; one end of the resistor R22 is connected with the same-phase end of the operational amplifier U1E, and the other end of the resistor R is grounded; one end of the resistor R23 is connected with the same-phase end of the operational amplifier U1F, and the other end of the resistor R is connected with the output current Io; one end of the resistor R24 is connected with the same-phase end of the operational amplifier U1F, and the other end of the resistor R is grounded; one end of the resistor R25 is connected with the inverting end of the operational amplifier U1E, and the other end of the resistor R is connected with a 5V power supply; one end of the resistor R26 is connected with the inverting end of the operational amplifier U1F, and the other end of the resistor R is connected with the inverting end of the operational amplifier U1E; one end of the resistor R27 is connected with the inverting end of the operational amplifier U1F, and the other end of the resistor R is grounded; one end of the resistor R28 is connected with the output end of the operational amplifier U1E, and the other end of the resistor R is connected with the input end of the OR gate OR 2; one end of the resistor R29 is connected with the output end of the operational amplifier U1F, and the other end of the resistor R29 is connected with the input end of the OR gate OR 2; the output end of the OR gate OR2 is connected with the grid electrode of the N-MOS tube Q2 through a resistor R30; one end of the BUZZER BUZZZER is connected with a 5V power supply, and the other end of the BUZZER BUZZZER is connected with the drain electrode of the N-MOS tube Q2; the anode of the diode D9 is connected with the drain electrode of the N-MOS transistor Q2, and the cathode of the diode D is connected with a 5V power supply; one end of the normally-closed relay RY2 is connected with a 5V power supply, and the other end of the normally-closed relay RY2 is connected with the drain electrode of the N-MOS tube Q2.
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