CN219659690U - Switch protection circuit - Google Patents
Switch protection circuit Download PDFInfo
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- CN219659690U CN219659690U CN202222886383.XU CN202222886383U CN219659690U CN 219659690 U CN219659690 U CN 219659690U CN 202222886383 U CN202222886383 U CN 202222886383U CN 219659690 U CN219659690 U CN 219659690U
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- 238000006243 chemical reaction Methods 0.000 claims abstract description 18
- 230000005669 field effect Effects 0.000 claims description 30
- 239000003990 capacitor Substances 0.000 claims description 13
- 238000000034 method Methods 0.000 abstract description 15
- 230000000694 effects Effects 0.000 abstract description 8
- 230000000630 rising effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 3
- 208000025274 Lightning injury Diseases 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000002441 reversible effect Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
The utility model discloses a switch protection circuit, comprising: the logic control unit is used for providing a switch control instruction; the conversion unit is used for converting the switch control instruction of the logic control unit into a control signal; and the switching unit is connected with the circuit input end and the circuit output end and is used for realizing slow opening and quick closing between the circuit input end and the circuit output end according to the control signal of the conversion unit. The stability of the power supply network is ensured by limiting the rising time of the output current in the starting process, so that the slow starting effect can be effectively improved; the MOS tube can be effectively prevented from being burnt out, and meanwhile, the output current can be rapidly closed in the turn-off process; the circuit design is simple and the cost is low.
Description
Technical Field
The utility model relates to the technical field of current load power supply control circuits, in particular to a switch protection circuit.
Background
At present, on electronic products, power supply control of a current load is generally realized by adopting switching devices such as a transistor, a MOS (metal oxide semiconductor) tube and a relay, but the conventional method cannot adapt to larger and larger load current, because a plurality of large-capacity capacitors are usually connected in parallel inside a large-current module. Because the capacitor charges rapidly, the current can be far greater than the steady-state input current in the starting process, and the whole power supply system is subjected to strong impact, so that the power supply network is excessively low in voltage and enters a protection state, the power supply network is interrupted, and even a switching device is burnt in severe cases, so that irreversible consequences are caused.
Disclosure of Invention
In view of the above, the present utility model provides a switch protection circuit to solve the technical problem that the power supply network is unstable due to the overlarge current of the heavy current load during the starting process, and the switch device is damaged seriously.
The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview and is intended to neither identify key/critical elements nor delineate the scope of such embodiments. Its sole purpose is to present some concepts in a simplified form as a prelude to the more detailed description that is presented later.
The utility model adopts the following technical scheme:
the utility model provides a switch protection circuit, comprising: the logic control unit is used for providing a switch control instruction;
the conversion unit is used for converting the switch control instruction of the logic control unit into a control signal;
the switching unit is connected with the circuit input end and the circuit output end and is used for realizing slow opening and quick closing between the circuit input end and the circuit output end according to the control signal of the conversion unit;
wherein the switching unit includes: a field effect transistor Q3 and a capacitor C1;
the input end is connected with the source electrode of the field effect transistor Q3;
the output end is respectively connected with the drain of the field effect transistor Q3 and one end of the capacitor C1;
the grid electrode of the field effect transistor Q3 is respectively connected with the output end of the conversion unit and the other end of the capacitor C1.
Furthermore, the conversion unit is also connected with an external power supply;
the conversion unit includes: resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, transistor Q1 and transistor Q2;
the output end of the logic control unit is respectively connected with one end of a resistor R1 and one end of a resistor R2;
the other end of the resistor R1 is connected with the grounding end;
the base electrode of the triode Q1 is connected with the other end of the resistor R2;
the emitter of the triode Q1 is connected with the grounding end;
the collector of the triode Q1 is connected with one end of a resistor R3;
the other end of the resistor R3 is connected with one end of the resistor R5 and the collector electrode of the triode Q2 respectively;
the external power supply is respectively connected with the other end of the resistor R5, the emitter of the triode Q2 and one end of the resistor R6;
the collector of the triode Q2 is respectively connected with the other end of the resistor R6 and one end of the resistor R4;
the other end of the resistor R4 is connected with the grounding end;
the collector of the triode Q2 is also connected with the grid electrode of the field effect transistor Q3 of the switching unit.
Further, the logic control unit includes: a logic control device;
and the general input/output port of the logic control device is respectively connected with one end of the resistor R1 and one end of the resistor R2.
Further, the logic control unit further includes: TVS tube D1;
one end of the TVS tube D1 is connected with a general input/output port of the logic control device;
the other end of the TVS tube D1 is connected with a grounding end.
Further, the external power supply provides the same voltage as the circuit input terminal.
Further, the external power supply is provided as the circuit input terminal.
Further, the logic control device is an MCU, an FPGA or an SoC.
Further, the voltage at the input end of the circuit is 24V, and when the general input/output port of the logic control device outputs a high level, the voltage is 3.3V.
The utility model has the beneficial effects that:
1. the stability of the power supply network is ensured by limiting the rising time of the output current in the starting process, and compared with the implementation mode in the prior art that the switching time of the power supply network is controlled by solely relying on the GPIO of the MCU, the slow starting effect can be effectively improved;
2. the stability of the power supply network in the starting process is ensured, the MOS tube can be effectively prevented from being burnt out, and meanwhile, the output current can be rapidly closed in the shutdown process;
3. the circuit design is simple and the cost is low.
Drawings
In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a block diagram of a switch protection circuit according to the present utility model
Fig. 2 is a circuit diagram of a switching unit of the present utility model;
FIG. 3 is a circuit diagram of one embodiment of a switch protection circuit of the present utility model;
FIG. 4 shows the voltage waveforms of the general purpose input/output ports of the logic control device, the drain current waveforms of the field effect transistor Q3, and the gate and source voltage waveforms of the field effect transistor Q3 when the field effect transistor Q3 is in the on process;
fig. 5 shows the test results of the voltage waveform of the general input/output port of the logic control device, the drain current waveform of the fet Q3, and the gate and source voltage waveforms of the fet Q3 when the fet Q3 is turned off.
Detailed Description
Embodiments of the present utility model will be described in detail below with reference to the accompanying drawings. It should be understood that the described embodiments are merely some, but not all, embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
As shown in fig. 1, the present utility model provides a switch protection circuit, comprising: a logic control unit 1, a conversion unit 2 and a switching unit 3. The logic control unit 1 is used for providing a switch control instruction; the conversion unit 2 is used for converting the switch control instruction of the logic control unit into a control signal; the switch unit 3 is connected with the circuit input end and the circuit output end and is used for realizing slow opening and quick closing between the circuit input end and the circuit output end according to the control signal of the conversion unit.
As shown in fig. 2, the switching unit 3 includes: a field effect transistor Q3 and a capacitor C1; the circuit input end VCC2 is connected with the source electrode of the field effect transistor Q3; the circuit output end VCC3 is respectively connected with the drain of the field effect transistor Q3 and one end of the capacitor C1; the grid electrode of the field effect transistor Q3 is respectively connected with the output end of the conversion unit 2 and the other end of the capacitor C1.
In one embodiment, as shown in fig. 3, the conversion unit 2 is further connected to an external power source, which may be another power source or a circuit input terminal, and when the external power source is connected to the other power source, the other power source preferably provides the same voltage as the circuit input terminal.
The conversion unit 2 includes: resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, transistor Q1 and transistor Q2. The output end of the logic control unit 1 is respectively connected with one end of a resistor R1 and one end of a resistor R2; the other end of the resistor R1 is connected with the grounding end; the base electrode of the triode Q1 is connected with the other end of the resistor R2; the emitter of the triode Q1 is connected with the grounding end; the collector of the triode Q1 is connected with one end of a resistor R3; the other end of the resistor R3 is connected with one end of the resistor R5 and the collector electrode of the triode Q2 respectively; the external power supply is respectively connected with the other end of the resistor R5, the emitter of the triode Q2 and one end of the resistor R6; the collector of the triode Q2 is respectively connected with the other end of the resistor R6 and one end of the resistor R4; the other end of the resistor R4 is connected with the grounding end; the collector of the transistor Q2 is also connected to the gate of the field effect transistor Q3 of the switching unit 3.
In one embodiment, as shown in fig. 3, the general input/output ports of the logic control device are connected to one end of the resistor R1 and one end of the resistor R2, respectively. Preferably, the logic control unit further includes: TVS tube D1; one end of the TVS tube D1 is connected with a general input/output port of the logic control device; the other end of the TVS tube D1 is connected with a grounding end.
Taking the voltage of the input end VCC2 as 24V, the voltage is 3.3V when the general input/output port of the logic control device outputs high level. Wherein, the logic control device is MCU, FPGA or SoC.
The GPIO port of the logic control device gives out high-low level control signals to control the on-off of the protection circuit. The GPIO port is connected to the cathode of TVS tube D1. The TVS tube D1 can clamp the voltage input to the logic control device, so that the logic control device is prevented from being damaged due to static electricity and lightning stroke, and the control of the whole power supply network is affected. When the voltage input to the GPIO port is higher than the reverse turn-off voltage of the TVS tube D1, the TVS tube D1 breaks down reversely rapidly and enters a conducting state, so that the function of protecting the logic control device is achieved.
When the GPIO port of the logic control device gives a high level, the voltage applied to the base of the triode Q1 is enabled to be larger than 0.7V through the resistor R2, meanwhile, the inflow current is not smaller than 1mA, the resistor R2 plays a role in limiting current, the triode Q1 is in a switch-on state, the collector and the emitter of the triode Q1 are completely conducted, and the input end VCC2, the resistor R5, the resistor R3, the triode Q1 and the grounding end form a loop. At this time, since the on voltage of the transistor Q1 is about 0.3V in the switch-on state, taking R3 to be equal to R5, the voltage at the base of Q2 is about 11.85V. At this time, the emitter voltage of the triode is greater than the base voltage and greater than the collector voltage, so that the conduction condition of Q2 is satisfied, and the triode Q2 is in a conduction state, and since the triode Q2 is in a conduction state, the resistor R6 is shorted by the triode Q2 at this time, so that the voltage on the resistor R4 is about the voltage of the input end VCC2, here 23.7V. At this time, the voltage of the gate and the source of the fet Q3 do not meet the on condition, so the fet Q3 is in the off state, and the voltage of VCC3 is substantially 0.
When the GPIO port of the logic control device gives a low level, the voltage applied to the base of the transistor Q1 is made to be less than 0.7V, at this time, the transistor Q1 is in a switch-off state, the input terminal VCC2, the resistor R5, and the resistor R3, the transistor Q1 and the ground terminal cannot form a loop, at this time, the voltage at the base of the transistor Q2 is about the voltage of the input terminal VCC2, and here is 24V. The transistor Q2 is non-conductive, and the voltage applied to the input terminal VCC2, where the voltage difference between the gate and the source of the field-effect transistor Q3 is negative half, is due to the voltage division effect of the resistor R6 and the resistor R4, so that the transistor Q3 is in a conductive state according to the conductive condition. The resistance values of the resistor R6 and the resistor R4 can be consistent.
The capacitor C1 mainly plays a role in delaying and reducing the current flowing through the source electrode and the drain electrode of the field effect transistor Q3. Since the fet Q3 experiences a variable resistance region during the process from start-up to full-on, if a large current flows through the source and drain of the fet Q3 during this process, the MOS may be burned out directly over the SOA curve in which the MOS operates, resulting in interruption of the entire power supply network. The larger the capacitance of the capacitor C1, the more remarkable the effect of the current hysteresis voltage is. In practical applications, it is necessary to ensure that the fet Q3 operates within the SOA region, and exceeding the limit region may cause damage to the electronic components.
As shown in fig. 4, to actually test the actual effect of this scheme in the on process of the field effect transistor Q3. Wherein, the CH1 channel is the voltage waveform of the GPIO port of the logic control device; the CH2 channel is the drain current waveform of the field effect transistor Q3; the CH3 channel is the voltage waveform of the grid electrode of the field effect transistor Q3, and the CH4 channel is the voltage waveform of the drain electrode of the field effect transistor Q3. As is apparent from fig. 4, in the process of gradually increasing the current flowing between the source and the drain of the field effect transistor Q3, the SOA curve of the MOS transistor is conformed, and meanwhile, the effect of slowly increasing the drain voltage is achieved, so that the delay effect of more than 20mS can be achieved.
As shown in fig. 5, to actually test the actual effect of this scheme in the off process of the field effect transistor Q3. Wherein, the CH1 channel is the voltage waveform of the GPIO port of the logic control device; the CH2 channel is the drain current waveform of the field effect transistor Q3; the CH3 channel is the voltage waveform of the grid electrode of the field effect transistor Q3, and the CH4 channel is the voltage waveform of the drain electrode of the field effect transistor Q3. It is obvious that when the GPIO port of the logic control device is changed from low level to high level, the source voltage of the field effect transistor Q3 is rapidly increased to 24V, and the purpose of rapid turn-off is achieved. The reason why the drain voltage waveform drain current of the fet Q3 drops slowly is due to capacitive load discharge.
The utility model adopts a switch circuit formed by MOS tubes, resistive-capacitive elements and the like and a logic control device to form a switch protection circuit, which ensures the stability of a power supply network by limiting the rising time of output current in the starting process and can effectively prevent the MOS tubes from being burnt out.
The circuit design of the utility model ensures that the power supply control circuit of the current load has the advantage of slow starting of the output current, solves the problem of unstable power supply voltage and damage to a switching device caused by overlarge current in the starting process, and simultaneously can quickly stop the output of the current when the power supply is turned off.
The foregoing is merely illustrative of the present utility model, and the present utility model is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present utility model should be included in the present utility model. Therefore, the protection scope of the utility model is subject to the protection scope of the claims.
Claims (10)
1. A switch protection circuit, comprising:
the logic control unit is used for providing a switch control instruction;
the input end of the conversion unit receives the switch control instruction sent by the logic control unit, converts the switch control instruction into a control signal and outputs the control signal;
the switching unit is connected with the circuit input end and the circuit output end and is used for realizing slow opening and quick closing between the circuit input end and the circuit output end according to the received control signal sent by the conversion unit;
wherein the switching unit includes: a field effect transistor Q3 and a capacitor C1;
the input end of the circuit is connected with the source electrode of the field effect transistor Q3;
the output end of the circuit is respectively connected with the drain electrode of the field effect transistor Q3 and one end of the capacitor C1;
the grid electrode of the field effect transistor Q3 is respectively connected with the output end of the conversion unit and the other end of the capacitor C1.
2. The switch protection circuit according to claim 1, wherein the conversion unit is further connected to an external power source;
the conversion unit includes: resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, resistor R6, transistor Q1 and transistor Q2;
the output end of the logic control unit is respectively connected with one end of a resistor R1 and one end of a resistor R2;
the other end of the resistor R1 is connected with the grounding end;
the base electrode of the triode Q1 is connected with the other end of the resistor R2;
the emitter of the triode Q1 is connected with the grounding end;
the collector of the triode Q1 is connected with one end of a resistor R3;
the other end of the resistor R3 is connected with one end of the resistor R5 and the collector electrode of the triode Q2 respectively;
the external power supply is respectively connected with the other end of the resistor R5, the emitter of the triode Q2 and one end of the resistor R6;
the collector of the triode Q2 is respectively connected with the other end of the resistor R6 and one end of the resistor R4;
the other end of the resistor R4 is connected with the grounding end;
the collector of the triode Q2 is also connected with the grid electrode of the field effect transistor Q3 of the switching unit.
3. A switch protection circuit according to claim 2, wherein the logic control unit comprises: a logic control device;
and the general input/output port of the logic control device is respectively connected with one end of the resistor R1 and one end of the resistor R2.
4. A switch protection circuit according to claim 3, wherein the logic control unit further comprises: TVS tube D1;
one end of the TVS tube D1 is connected with a general input/output port of the logic control device;
the other end of the TVS tube D1 is connected with a grounding end.
5. A switch protection circuit according to any of claims 2-4, wherein the external power supply provides the same voltage as the circuit input.
6. A switch protection circuit according to claim 3 or 4, wherein the external power supply is provided as the circuit input.
7. A switch protection circuit according to claim 3 or 4, wherein the logic control device is an MCU, FPGA or SoC.
8. The switch protection circuit of claim 6, wherein the voltage at the input of the circuit is 24V, and the voltage at the output of the general purpose input/output port of the logic control device is 3.3V.
9. A switch protection circuit according to claim 2, wherein the external power source is provided as the circuit input.
10. A switch protection circuit according to claim 9, wherein the voltage at the input of the circuit is 24V.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222886383.XU CN219659690U (en) | 2022-10-31 | 2022-10-31 | Switch protection circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222886383.XU CN219659690U (en) | 2022-10-31 | 2022-10-31 | Switch protection circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219659690U true CN219659690U (en) | 2023-09-08 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222886383.XU Active CN219659690U (en) | 2022-10-31 | 2022-10-31 | Switch protection circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219659690U (en) |
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2022
- 2022-10-31 CN CN202222886383.XU patent/CN219659690U/en active Active
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