CN219611954U - 10Gbps photoelectric conversion interconnection system based on VPX front-back IO architecture - Google Patents
10Gbps photoelectric conversion interconnection system based on VPX front-back IO architecture Download PDFInfo
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- CN219611954U CN219611954U CN202320092870.0U CN202320092870U CN219611954U CN 219611954 U CN219611954 U CN 219611954U CN 202320092870 U CN202320092870 U CN 202320092870U CN 219611954 U CN219611954 U CN 219611954U
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Abstract
The utility model relates to a 10Gbps photoelectric conversion interconnection system based on a VPX front-rear IO architecture, which comprises a chassis box body, a front plugboard card, a high-speed backboard, a rear plugboard card and an optical switching connector, wherein signal interconnection is realized between the front plugboard card and the high-speed backboard through the high-speed electric connector, a plurality of FPGA high-speed chips are also arranged on the front plugboard card, a plurality of high-speed optical modules are arranged on the rear plugboard card, the optical modules are connected with the optical connector arranged on the rear end surface of the rear plugboard card, and the optical connector is interconnected with the optical switching connector arranged on a chassis panel through an optical fiber cable assembly. According to the utility model, the FPGA chips and the optical modules are respectively arranged on the front plugboard card and the rear plugboard card, so that the overall heat consumption of the front plugboard card is dispersed, the number of links of photoelectric conversion is increased, and the problems of insufficient space layout of components and signal integrity of high-speed signal communication between the front plugboard card and the rear plugboard card are solved.
Description
Technical Field
The utility model relates to the technical field of photoelectric conversion, in particular to a 10Gbps photoelectric conversion interconnection system based on a VPX front-back IO architecture.
Background
With the rapid development of communication technology, high data volume interaction and long-distance transmission between devices are increasingly required, and thus, a photoelectric conversion interconnection system based on the VITA66 standard is being widely used in communication devices of vehicle-mounted or ground fixed stations. The photoelectric conversion interconnection system integrates modularization, integration and miniaturization, and can realize plug-and-play photoelectric conversion communication equipment architecture. The topology diagram of the specific system architecture is shown in fig. 1, and the model diagram is shown in fig. 2. The architecture mainly realizes photoelectric conversion and interconnection of data through the following points:
(1) The FPGA high-speed chip on the functional board card realizes the transmission and the reception of high-speed electric signals;
(2) The photoelectric conversion module on the functional board card converts the high-speed electric signals sent by the FPGA high-speed chip into optical signals to be transmitted to the external equipment, and then converts the received optical signals of the external equipment into the high-speed electric signals to be transmitted to the FPGA high-speed chip, so that data interaction is realized;
(3) The functional board card is arranged in an optical connector plug of the board card through an optical module tail optical fiber and then is interconnected with an optical cable arranged in an optical connector socket on the backboard, so that the interconnection of optical links is realized.
This architecture has mainly the following drawbacks:
(1) The space of the existing functional board card is insufficient to meet the layout requirement of the multi-path optical module
The prior standard 6U VPX board card has the external dimension of 233.35mm which is 160mm, and in addition, in order to consider the heat consumption of the chip, a radiating cold plate structure is designed, and the installation of the cold plate occupies the layout space of a part of devices, so that when multiple paths of optical signals need to be output, the board card has insufficient space to carry out the layout of high-speed chips and optical modules.
(2) High complexity of board card circuit design and poor maintainability
Because the functions of the current equipment are more and more complex, the integrated chips on the board card are more and more, and the photoelectric conversion modules are required to be laid out, the layout of devices on the board card and the wiring of the PCB are complicated, and the design of the signal integrity of the circuit and the maintenance after the chip fails are extremely difficult.
(3) The board card has large power consumption and difficult heat dissipation
The integrated chip and the optical module on the board card are all concentrated in the range of 233.35mm x 160mm, the board card has high power consumption, and the difficulty is increased for system heat dissipation.
Disclosure of Invention
In order to overcome the defects in the prior art, the utility model provides a 10Gbps photoelectric conversion interconnection system based on a VPX front-back IO architecture, which is provided with a rear plugboard card, enlarges the layout area of the whole device and is beneficial to the design of heat dissipation of a whole system; the photoelectric conversion module is separated from other integrated chips, so that the design difficulty of the front plugboard card is reduced, the maintainability of the functional board card is improved, the number of photoelectric conversion links is increased, and the signal integrity problem of 10Gbps high-speed signal communication between the front plugboard card and the rear plugboard card is solved.
The utility model is realized by the following technical scheme, the 10Gbps photoelectric conversion interconnection system based on the VPX front and rear IO architecture provided by the utility model comprises a chassis box body, a front plugboard card, a high-speed backboard, a rear plugboard card, an optical fiber cable component and an optical switching connector, wherein the optical switching connector is arranged on a chassis panel and used as an external optical interface, the front plugboard card, the high-speed backboard, the rear plugboard card and the optical fiber cable component are all arranged in the chassis, the high-speed backboard is arranged between the front plugboard card and the rear plugboard card, one side surface of the front plugboard card and one side surface of the high-speed backboard are in signal interconnection through a first electric connector, the other side surface of the rear plugboard card and the other side surface of the high-speed backboard are in signal interconnection through a second electric connector, a plurality of FPGA high-speed chips are arranged on the front plugboard card, a plurality of optical modules are arranged on the rear plugboard card, one end of each optical module is in high-speed electric signal interconnection with the second electric connector, and the other end of each optical module is connected with the optical connector arranged on the rear plugboard and the rear end surface of the chassis through the optical cable component.
According to the scheme, the external optical signal can be converted into the 10Gbps electrical signal through the optical module and then transmitted to the FPGA high-speed chip of the front plugboard card. Or, converting the multipath 10Gbps electric signals of the FPGA high-speed chip into optical signals and outputting the optical signals to the outside. According to the scheme, the plurality of high-speed electric signal FPGA chips and the plurality of 10Gbps optical modules are respectively arranged on the front plugboard card and the rear plugboard card, so that the overall heat consumption of the front plugboard card is dispersed, the number of links of photoelectric conversion is increased, the design difficulty of the front plugboard card is reduced, the maintainability of the functional board card is improved, and the problem of insufficient space of layout components caused by the front plugboard card is solved.
Preferably, the first electrical connector is a VPX20 series electrical connector for front plug (P/J), and the second electrical connector is a VPX20 series electrical connector for rear plug (RP/RJ).
As a further preference, the plug end of the first electric connector is arranged on the front plugboard card, and the socket end of the first electric connector is arranged on one side surface of the high-speed backboard, which is close to the front plugboard card; the second electric connector plug end is arranged on the rear plugboard card, and the second electric connector socket end is arranged on one side surface of the high-speed backboard, which is close to the rear plugboard card; the plurality of FPGA high-speed chips are in signal interconnection with the first electrical connector plug, and the plurality of 10Gbps optical modules are in signal interconnection with the second electrical connector plug.
As a further preferable mode, the two ends of the optical fiber cable are optical connectors with built-in MT plugs, one end of the optical connector is optically coupled with the optical connector on the rear end face of the rear plugboard card, and the other end of the optical connector is optically coupled with the optical switching connector on the chassis panel.
As a further preferable aspect, the optical connector is an optical connector of the JYSK series, and the optical switching connector is an optical connector of the GYM series.
As a further preferable mode, the front plugboard card and the rear plugboard card are made of high-speed plates, high-speed differential signal wires designed in the front plugboard card and the rear plugboard card are made of strip line models, and wiring impedance is controlled according to 100+/-10 omega; when the front plugboard card and the rear plugboard card are designed in a high-speed differential signal line lamination mode, a 10Gbps high-speed differential signal line is arranged on a signal layer at a position 1.1mm away from the top layer of the printed board; the sizes of the high-speed differential signal through holes and the bonding pads of the electric connectors in the front plugboard card and the rear plugboard card are designed according to the recommended size of the VPX20 connector, the high-speed differential signal through holes are designed in a back drilling mode, anti-bonding pads are added at the positions of the high-speed differential signal through holes, the length of each anti-bonding pad is 3.5mm, and the width of each anti-bonding pad is 1.1mm.
As a further preferable mode, the plates of the front plugboard card and the rear plugboard card are R5775 series plates of M6.
As a further preferred option, the fan-out via holes of the pins of the optical module on the rear plugboard card are designed to be blind holes, and the back drilling treatment is carried out on the wiring via holes at the coupling capacitors connected in series on the circuit, so that the stub effect brought by the via holes is reduced, and the link loss is reduced.
As a further preferable mode, the high-speed backboard plates are selected from R5775 series plates of M6, and the optimal thickness of the high-speed backboard is controlled to be 3.8mm plus or minus 0.38mm. The sizes of the high-speed differential signal through holes and the bonding pads of the high-speed backboard connector are designed according to the recommended size of the VPX20 connector, anti-bonding pads are added at the positions of the through holes corresponding to the high-speed differential signals of the backboard, the length of the anti-bonding pads is 4.8mm, and the width of the anti-bonding pads is 1.3mm.
The utility model ensures the signal quality of the high-speed electric signal through the design, avoids error codes in the photoelectric conversion link, and further ensures the data interaction quality.
Compared with the prior art, the utility model has obvious advantages and beneficial effects. By means of the technical scheme, the utility model can achieve quite technical progress and practicability, has wide utilization value, and has at least the following advantages:
the utility model increases the rear plugboard card, enlarges the layout area of the whole device, and is beneficial to the design of heat dissipation of the whole system; the chip and the photoelectric conversion module are separated and respectively arranged on the front plugboard card and the rear plugboard card, so that the design difficulty of the front plugboard card is reduced, the maintainability and the heat dissipation performance of the functional board card are improved, the number of links of photoelectric conversion is greatly increased, and the problem of insufficient space of layout components caused by the front plugboard card is effectively solved.
By designing the board, the connector and the high-speed differential signal line wiring of the front plugboard card, the rear plugboard card and the high-speed backboard, the signal integrity problem of 10Gbps high-speed signal communication between the front plugboard card and the rear plugboard card is solved.
The foregoing description is only an overview of the present utility model, and is intended to be implemented in accordance with the teachings of the present utility model, as well as the preferred embodiments thereof, together with the following detailed description of the utility model, given by way of illustration only, together with the accompanying drawings.
Drawings
FIG. 1 is a topology of a prior art photovoltaic conversion system conforming to the VITA66 standard;
FIG. 2 is a diagram of a prior art photovoltaic conversion system conforming to the VITA66 standard;
FIG. 3 is a topology diagram of a 10Gbps photoelectric conversion system based on VPX front-back IO architecture of the present utility model;
FIG. 4 is a model diagram of a 10Gbps photoelectric conversion system based on a VPX front-back IO architecture of the present utility model;
FIG. 5 is a schematic diagram of the front and rear card board high speed signal trace locations and via backdrilling;
FIG. 6 is a diagram of the differential pair anti-pad dimensions of the front card and rear card high speed connector pins;
fig. 7 is a diagram of high speed connector pin differential pair anti-pad dimensions on a high speed backplane.
Element and symbol description:
1-a case body of the case;
2-function board card;
3-VPX20 electrical connectors;
4-a back plate;
5-an external optical interface of the case;
6-a fiber optic cable assembly;
7-RPB5 series optical connectors;
8-front plugboard card;
9-a high-speed back plate;
10-a rear plugboard card;
an 11-optical connector;
12-an optical switching connector;
13-a first electrical connector;
14-a second electrical connector;
15-a top pad of the printed board;
16-high speed signal lines;
17-a bottom layer of the printed board;
18-back drilling of high-speed signal holes.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the present utility model will be clearly and completely described below with reference to the specific embodiments and the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments. The embodiments generally described and illustrated in the figures herein may be implemented in a variety of different configurations. Thus, the following detailed description of the embodiments of the utility model, as presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to fall within the scope of the utility model.
The utility model provides a 10Gbps photoelectric conversion interconnection system based on a VPX front-rear IO architecture, which mainly comprises a case body 1, a front plugboard card 8, a high-speed backboard 9, a rear plugboard card 10, an optical fiber cable component 6 and an optical switching connector 12. The front plugboard card and the rear plugboard card have the size of the VPX standard 6U board card, the height of the chassis box body can meet the plugging of the VPX standard 6U board card, and the front plugboard card and the rear plugboard card have a good heat dissipation system. The optical switching connector is arranged on the chassis panel and used as an external optical interface. The front plugboard card, the high-speed backboard, the rear plugboard card and the optical fiber cable assembly are all arranged in the chassis, the high-speed backboard is arranged between the front plugboard card and the rear plugboard card, the signal interconnection is realized between the front plugboard card and one side surface of the high-speed backboard through a plurality of first electric connectors 13, and the signal interconnection is realized between the rear plugboard card and the other side surface of the high-speed backboard through a plurality of second electric connectors 14. The front card board is also provided with a plurality of chips and other components, and the chips comprise but are not limited to a power conversion chip, a control chip, a plurality of FPGA high-speed chips and the like (the power conversion chip and the control chip are in the prior art and are not shown in fig. 3 and 4). The power conversion chip is connected with the control chip and the plurality of FPGA high-speed chips, the control chip is also connected with the plurality of FPGA high-speed chips, and the plurality of FPGA high-speed chips are in signal interconnection with the plurality of first electric connectors. The rear plugboard card is provided with a plurality of 10Gbps optical modules (namely photoelectric conversion modules), one end of each optical module is connected with a second electric connector to realize high-speed electric signal interconnection, the other end of each optical module is connected with a plurality of optical connectors 11 arranged on the rear end face of the rear plugboard card, and the optical connectors are connected with a plurality of optical transfer connectors on the chassis panel through optical fiber cable assemblies.
In a specific embodiment, the number of the first electrical connectors is equal to the number of the second electrical connectors, and the number of the FPGA high-speed chips and the number of the optical modules are selected according to the number of specific photoelectric conversion links; the optical modules are in one-to-one correspondence with the optical connectors on the rear end face of the rear plugboard card, and the optical connectors on the rear end face of the rear plugboard card and the optical switching connectors on the chassis panel can be in one-to-one correspondence or in a many-to-one relationship; the specific interconnection scheme is specifically designed according to the actual application situation.
Through the scheme, the multipath optical signals outside the chassis are transmitted to the optical connectors corresponding to the end faces of the rear plugboard cards through the optical switching connectors and the optical fiber cable assemblies which are respectively connected, the optical signals are transmitted to the corresponding optical modules through the optical connectors, the optical modules convert the optical signals into 10Gbps electrical signals, and the electrical signals are transmitted to the FPGA high-speed chips of the front plugboard cards through the second electrical connectors, the high-speed backboard and the first electrical connectors. Or, the multi-path 10Gbps electric signals of the FPGA high-speed chip on the front plugboard card are transmitted to the optical module of the rear plugboard card through the first electric connector, the high-speed backboard and the second electric connector, the electric signals are converted into optical signals through the optical module, and the optical signals are transmitted to the optical switching connector through the optical connector on the rear end face of the rear plugboard card through the optical fiber cable assembly, so that the signals are output outwards, and the aim of data interaction is achieved. According to the utility model, the plurality of high-speed electric signal FPGA chips and the plurality of 10Gbps optical modules are respectively arranged on the front plugboard card and the rear plugboard card, so that the problem of insufficient space of layout components caused by the front plugboard card is solved, and wiring and maintenance of the board card are facilitated.
In one embodiment, the first electrical connector is a VPX20 series electrical connector for front plug (P/J) and the second electrical connector is a VPX20 series electrical connector for rear plug (RP/RJ).
On the basis of the embodiment, the plug end of the P/J connector is arranged on the front plugboard card, and the socket end of the P/J connector is arranged on one side surface of the high-speed backboard, which is close to the front plugboard card. The plug end of the RP/RJ connector is arranged on the rear plugboard card, and the socket end of the RP/RJ connector is arranged on one side surface of the high-speed backboard, which is close to the rear plugboard card. A plurality of FPGA high-speed chips are in signal interconnection with the plug end of the P/J connector, and a plurality of 10Gbps optical modules are in signal interconnection with the plug end of the RP/RJ connector.
In one embodiment, the optical connector on the rear end face of the rear card board adopts JYSK-series optical connectors, and the optical switching connector on the chassis panel adopts GYM-series optical connectors as external optical interfaces. The two ends of the optical fiber cable are optical connectors with built-in MT plugs, one end of the optical connector is optically coupled with the JYSK series optical connectors, and the other end of the optical connector is optically coupled with the GYM series optical connectors.
The high-speed backboard mainly comprises a printed board manufactured by a high-speed board and a high-speed VPX20 connector socket, and is mainly responsible for supplying power to each front plugboard card and each rear plugboard card and providing 10Gbps electric signal transmission channels between the front plugboard cards and between the front plugboard cards and the rear plugboard cards.
Because the signal quality requirement of the 10Gbps optical module on the high-speed electric signal is higher, if the signal integrity design is not fully considered in the process of designing the high-speed signal wiring of the front plugboard card, the high-speed backboard and the rear plugboard card, error codes can occur in the photoelectric conversion link, so that the interaction of data is affected. In order to ensure that no error code exists in the whole photoelectric conversion link, the design key points of the front plugboard card, the high-speed backboard and the rear plugboard card need to be paid attention to in the design process, and the design key points are as follows:
(1) Front plugboard card design
For 10Gbps high-speed signals, a front plugboard card is a high-speed board, and an R5775 series board of M6 is usually selected. The front plugboard is plugged by a high-speed VPX20 connector, and the transmission rate of the high-speed VPX20 connector is up to 20Gbps.
When designing the high-speed differential signal line in the front plugboard card, the high-speed differential signal line needs to be ensured to adopt a strip line model, and the two ground planes are referenced as much as possible and are complete in reference, and the wiring impedance is controlled according to 100+/-10 omega.
When the front plugboard is clamped on the high-speed differential signal wire lamination design, the high-speed differential signal wire of 10Gbps is preferentially arranged on a signal layer (the position is the position where the pin of the fish-eye structure of the connector is pressed into the inner contact hole wall of the through hole and is farthest from the top layer of the printed board) at the position 1.1mm away from the top layer of the printed board, so that the short piles brought by the pin of the VPX connector are conveniently reduced, and the purpose of reducing the insertion loss is achieved, and is particularly shown in figure 5. The high-speed differential signal line of the front plugboard card is preferably not arranged on the bottom layer of the board card, and does not appear to have short piles, but the path of the signal passing through the through hole is increased, the parasitic capacitance at the through hole is increased, the rising edge of the high-speed signal is slowed down, and the quality of the high-speed signal is influenced.
The high-speed differential signal via hole and the pad size of the VPX20 connector plug of the front plugboard card are designed according to the recommended size of the VPX20 connector, the high-speed differential signal via hole is designed by back drilling as shown in fig. 5, and an anti-pad is added at the differential signal via hole so as to facilitate the lifting of the impedance at the via hole, and the larger the anti-pad size is, the more the impedance at the via hole is improved, but in order to achieve complete wiring reference, the recommended size of the anti-pad is as shown in fig. 6, and the length of the anti-pad is 3.5mm and the width is 1.1mm.
(2) High speed backplane design
In order to meet the requirement of 10Gbps high-speed signal transmission, the high-speed backboard plates are preferably selected from high-speed plates, and in one embodiment, the high-speed backboard plates are selected from R5775 series plates of M6.
The design of the signal integrity of the vias on the high speed backplane is also critical because the high speed signals of the front card pass through the VPX20 receptacle connector and vias on the high speed backplane to the rear card without any traces. The following points are mainly noted in the design of the high-speed backboard:
a) In order to reduce the parasitic capacitance effect of the through hole, the thickness of the high-speed backboard needs to be reduced as much as possible, and the optimal thickness of the high-speed backboard is controlled to be 3.8mm plus or minus 0.38mm under the condition that the pin length of the VPX20 socket connector with the front and back sides being in compression joint with the high-speed backboard and the thickness tolerance of the high-speed backboard are fully considered.
b) The high-speed differential signal via and pad sizes of the high-speed backplane VPX20 connector receptacle are designed according to the VPX20 connector recommended dimensions. The anti-bonding pad is added at the position of the through hole corresponding to the backboard high-speed differential signal, so that the impedance at the position of the through hole is conveniently improved, the larger the anti-bonding pad size is, the more the impedance at the position of the through hole is improved, but in order to achieve the overcurrent capacity of a power supply layer, the suggested size of the anti-bonding pad is shown in fig. 7, and the length of the anti-bonding pad is 4.8mm, and the width of the anti-bonding pad is 1.3mm.
(3) Rear plugboard card design
The wiring design and anti-pad size design of the rear card board can be fully referred to the design points of the front card board. Namely, the rear plugboard is clamped by a high-speed board, and R5775 series boards of M6 are preferred. The rear plugboard card plug adopts a high-speed VPX20 connector plug with the transmission rate as high as 20Gbps.
When the high-speed signal line is designed in the rear plugboard card, the high-speed differential signal line needs to be ensured to adopt a strip line model, and the two ground planes are referenced as much as possible and are complete in reference, and the wiring impedance is controlled according to 100+/-10 omega.
When the rear plugboard is clamped on the high-speed differential signal wire lamination design, the high-speed differential signal wire of 10Gbps is preferentially arranged on a signal layer at a position 1.1mm away from the top layer of the printed board, so that short piles brought by pins of the VPX connector are reduced, and the purpose of reducing insertion loss is achieved. The high-speed differential lines of the rear card are preferably not routed to the bottom of the card so as not to affect high-speed signal quality.
The sizes of the high-speed differential signal via holes and the bonding pads of the rear plugboard card connector are designed according to the recommended size of the VPX20 connector, the high-speed signal holes are designed in a back drilling way as shown in fig. 5, anti-bonding pads are added at the positions of the differential via holes, and the recommended sizes of the anti-bonding pads are as follows: the length is 3.5mm and the width is 1.1mm.
The pin fanning-out via holes of the optical modules on the rear plugboard card are designed to be blind holes, and the back drilling treatment is carried out on the wiring via holes at the coupling capacitors connected in series on the circuit, so that the stub effect caused by the via holes is reduced, and the link loss is further reduced.
The utility model increases the rear plugboard card, which is equivalent to enlarging the layout area of the whole device, so that the whole heat consumption of the front plugboard card is dispersed, on one hand, the design of heat dissipation of the whole system is facilitated, on the other hand, the FPGA high-speed chip and the 10Gbps photoelectric conversion module can be respectively arranged on the front plugboard card and the rear plugboard card, the number of photoelectric conversion links is increased, the design difficulty of the front plugboard card is reduced, the maintainability of the functional board card is improved, and meanwhile, the signal integrity problem of 10Gbps high-speed signal communication between the front plugboard card and the rear plugboard card is solved.
The foregoing is merely an embodiment of the present utility model, and the present utility model is not limited in any way, and may have other embodiments according to the above structures and functions, which are not listed. Therefore, any simple modification, equivalent variation and modification of the above embodiments according to the technical substance of the present utility model without departing from the scope of the technical solution of the present utility model will still fall within the scope of the technical solution of the present utility model.
Claims (10)
1. The 10Gbps photoelectric conversion interconnection system based on the VPX front and back IO architecture is characterized by comprising a chassis box body (1), a front plugboard card (8), a high-speed backboard (9), a back plugboard card (10), an optical fiber cable component (6) and an optical switching connector (12), wherein the optical switching connector is arranged on a chassis panel and used as an external optical interface, the front plugboard card, the high-speed backboard, the back plugboard card and the optical fiber cable component are all arranged in the chassis, the high-speed backboard is arranged between the front plugboard card and the back plugboard card, one side surface of the front plugboard card and one side surface of the high-speed backboard are in signal interconnection through a first electrical connector, the other side surface of the back plugboard card and the other side surface of the high-speed backboard are in signal interconnection through a second electrical connector, a plurality of FPGA high-speed chips are arranged on the front plugboard card, a plurality of FPGA high-speed chips are in signal interconnection with the first electrical connector, one end of the optical module is in high-speed electrical signal interconnection with the second electrical connector, the other end of the optical module is connected with an optical connector (11) arranged on the back plugboard card rear end surface, and the optical connector is in signal interconnection with the optical connector (11) arranged on the back plugboard and the optical cable component is in the chassis through the optical fiber cable component (12).
2. The 10Gbps photoelectric conversion interconnect system based on VPX front-to-back IO architecture of claim 1, wherein the first electrical connector is a front-plug VPX20 series electrical connector and the second electrical connector is a rear-plug VPX20 series electrical connector.
3. The 10Gbps photoelectric conversion interconnect system based on VPX front-to-back IO architecture according to claim 1 or 2, wherein the first electrical connector plug end is disposed on the front card board, and the first electrical connector socket end is disposed on a side of the high-speed backplane near the front card board; the second electric connector plug end is arranged on the rear plugboard card, and the second electric connector socket end is arranged on one side surface of the high-speed backboard, which is close to the rear plugboard card; the plurality of FPGA high-speed chips are in signal interconnection with the first electrical connector plug, and the plurality of 10Gbps optical modules are in signal interconnection with the second electrical connector plug.
4. The 10Gbps photoelectric conversion interconnect system based on VPX front-back IO architecture according to claim 1, wherein the optical connectors with built-in MT plugs are at both ends of the fiber optic cable, one end of which is optically coupled to the optical connector at the back end face of the back card board, and the other end of which is optically coupled to the optical transit connector on the chassis panel.
5. The 10Gbps photoelectric conversion interconnect system based on VPX front-back IO architecture according to claim 1 or 4, wherein the optical connector is an optical connector of the jsk series, and the optical transit connector is an optical connector of the GYM series.
6. The 10Gbps photoelectric conversion interconnection system based on the VPX front and rear IO architecture as claimed in claim 1, wherein the front plugboard card and the rear plugboard card are high-speed boards, high-speed differential signal lines designed in the front plugboard card and the rear plugboard card adopt a strip line model, and wiring impedance is controlled according to 100+/-10 omega; when the front plugboard card and the rear plugboard card are designed in a high-speed differential signal line lamination mode, the high-speed differential signal line of 10Gbps is preferentially arranged on a signal layer at a position 1.1mm away from the top layer of the printed board; the sizes of the high-speed differential signal through holes and the bonding pads of the electric connectors in the front plugboard card and the rear plugboard card are designed according to the recommended size of the VPX20 connector, the high-speed differential signal through holes are designed in a back drilling mode, anti-bonding pads are added at the positions of the high-speed differential signal through holes, the length of each anti-bonding pad is 3.5mm, and the width of each anti-bonding pad is 1.1mm.
7. The 10Gbps photoelectric conversion interconnection system based on VPX front-back IO architecture according to claim 1 or 6, wherein the front card board and the back card board are made of R5775 series of M6 boards.
8. The 10Gbps photoelectric conversion interconnect system based on VPX front-back IO architecture according to claim 1 or 6, wherein the optical module pin fanout vias on the back card board are blind hole design, and the routing vias at the coupling capacitors connected in series on the circuit are back drilled, so as to reduce stub effect caused by the vias and reduce link loss.
9. The 10Gbps photoelectric conversion interconnection system based on the VPX front-rear IO architecture as claimed in claim 1, wherein the high-speed backboard is an R5775 series board of M6, and the optimal thickness of the high-speed backboard is controlled to be 3.8mm plus or minus 0.38mm.
10. The 10Gbps photoelectric conversion interconnect system based on VPX front-to-back IO architecture according to claim 1 or 9, wherein the high-speed backplane connector high-speed differential signal via and pad size is designed according to the recommended size of VPX20 connector, anti-pads are added at the corresponding via of the backplane high-speed differential signal, the anti-pads have a length of 4.8mm and a width of 1.3mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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