CN219611601U - Field effect tube with built-in absorption loop - Google Patents

Abstract

The utility model discloses a field effect tube with an absorption loop built in, which consists of a grid G, a source S and a drain D, wherein the drain D of the field effect tube is connected with the positive electrode of a fast recovery diode D2, the negative electrode of the fast recovery diode D2 is connected with the negative electrode of a transient voltage suppression diode D1, the positive electrode of the transient voltage suppression diode D1 is connected with a lead-out pin VDC, and the grid G and the source S are kept unchanged. The utility model has the advantages that: the components are smaller, the occupied PCB area is small, the EMI effect after encapsulation is good, and the heat dissipation effect is good.

Description

Field effect tube with built-in absorption loop

Technical Field

The utility model relates to the field of integrated circuits, in particular to a field effect transistor with an absorption loop.

Background

The main components of the switching power supply mostly have parasitic inductances and capacitances, the parasitic capacitances Cp are typically connected in parallel with the switching elements or diodes, and the parasitic inductances are typically connected in series therewith. Due to the parasitic capacitance and inductance, the switching element often generates larger surge voltage and surge current when being switched on and off.

The on-off of the switch and the reverse recovery of the diode generate larger surge current and surge voltage. While the most effective way to suppress the inrush current when the switch is on is to use a zero voltage switching circuit. On the other hand, the surge voltage of the switch opening and the surge voltage of the diode reverse recovery may damage the semiconductor element and also cause noise. For this reason, an snubber circuit is required when the switch is turned off. The surge voltage generation mechanism is the same as that when the switch is turned off at the time of the reverse recovery of the diode, and therefore, this absorption circuit is also applicable to a diode circuit.

In applications where the switching power supply is less than 120W, flyback topologies are basically employed. The field effect transistor is 600V or 650V mainly, and also has high voltage MOSFET for ammeter power supply, up to 1200V. The current is mainly from 1A to 12A. In practical use, the D pole of the mosfet is connected with one end of the primary winding of the high-frequency transformer, the G pole is connected with a driving signal, and the S pole is connected with a sampling power resistor. Meanwhile, the D pole of the MOSFET is connected with an absorption loop to the high voltage after mains rectification, as shown in fig. 2, D1 and D2 form an absorption loop which generates reflection voltage at two ends of a primary winding of a transformer when a MOSFET is cut off, and D2 generally takes fast recovery diodes of FR series, such as FR107, FR157 and FR207; d1 is a TVS tube, and P6KE 180-240 (600W 180V-240V) or 1.5KE180-240 (1 KW 180V-240V) is generally taken.

In practical application, the absorption loop circuit needs to be selected according to different powers, and the selected diodes are selected to be fixed two diodes according to the power of the switching power supply, wherein the two diodes are distributed on the D pole of the field effect transistor and occupy a larger area of the PCB; in the occasion that the volume needs less can't satisfy the application needs, external absorption circuit can lead to the EMI to reach standard.

Disclosure of Invention

The utility model mainly aims to provide a field effect transistor with an internal absorption loop, which solves the technical problems in the background technology.

In order to achieve the above objective, the present utility model provides a field effect transistor with an absorption loop built in, the field effect transistor is composed of a gate electrode G, a source electrode S and a drain electrode D, the drain electrode D of the field effect transistor is connected to the positive electrode of a fast recovery diode D2, the negative electrode of the fast recovery diode D2 is connected to the negative electrode of a transient voltage suppression diode D1, the positive electrode of the transient voltage suppression diode D1 is connected to a lead-out pin VDC, and the gate electrode G and the source electrode S remain unchanged.

Preferably, the drain electrode D of the field effect tube is connected with the positive electrode of the fast recovery diode D2 and one end of the primary winding of the voltage device, the negative electrode of the fast recovery diode D2 is connected with the negative electrode of the transient voltage suppression diode D1, and the positive electrode of the transient voltage suppression diode D1 is connected with the lead-out pin VDC and the other end of the primary winding of the voltage device.

The transient voltage suppression diode D1 and the fast recovery diode D2 are built into the existing field effect transistor structure to be packaged together to form the field effect transistor with the built-in absorption loop.

Preferably, the transient voltage suppression diode D1 adopts FR series, and the fast recovery diode D2 adopts TVS tube to form high voltage field effect tube.

More preferably, the transient voltage suppressing diode D1 is FR107, FR157 or FR207, and the fast recovery diode D2 is P6KE 180-240 (600W 180V-240V) or 1.5KE180-240 (1 KW 180V-240V).

The utility model provides an integrated circuit element for the design of a switching power supply, simply replaces the original discrete device, reduces the space, has compact design and can obviously improve the EMI of a field effect transistor after encapsulation.

The utility model has the advantages that: the components are smaller, the occupied PCB area is small, the EMI effect after encapsulation is good, and the heat dissipation effect is good.

Drawings

The accompanying drawings, which are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate embodiments of the utility model and together with the description serve to explain the utility model and do not constitute a limitation on the utility model. In the drawings:

FIG. 1 is a schematic diagram of the present utility model;

FIG. 2 is a prior art diagram of the present utility model;

fig. 3 is a diagram showing the effect of the encapsulation of the present utility model.

Detailed Description

The following description of the utility model and the differences between the utility model and the prior art will be understood with reference to fig. 1 and the text. The following describes the utility model in further detail, including preferred embodiments, by way of the accompanying drawings and by way of examples of some alternative embodiments of the utility model. It should be noted that: any technical feature and any technical solution in this embodiment are one or several of various optional technical features or optional technical solutions, and in order to describe brevity, all of the optional technical features and the optional technical solutions of the present utility model cannot be exhausted in this document, and it is inconvenient for an implementation of each technical feature to emphasize that it is one of various optional implementations, so those skilled in the art should know: any technical means provided by the utility model can be replaced or any two or more technical means or technical features provided by the utility model can be mutually combined to obtain a new technical scheme. Any technical features and any technical solutions in the present embodiment do not limit the protection scope of the present utility model, and the protection scope of the present utility model should include any alternative technical solution that can be conceived by a person skilled in the art without performing creative efforts, and a new technical solution obtained by combining any two or more technical means or technical features provided by the present utility model with each other by a person skilled in the art.

The embodiment of the utility model provides a field effect transistor with an internal absorption loop.

The technical scheme provided by the utility model is described in more detail below with reference to fig. 1.

Example 1

The field effect tube with the built-in absorption loop comprises a grid G, a source S and a drain D, wherein the drain D of the field effect tube is connected with the positive electrode of a fast recovery diode D2, the negative electrode of the fast recovery diode D2 is connected with the negative electrode of a transient voltage suppression diode D1, the positive electrode of the transient voltage suppression diode D1 is connected with a lead-out pin VDC, and the grid G and the source S are kept unchanged.

Example 2

The field effect tube with built-in absorption loop in embodiment 1, wherein the drain electrode D of the field effect tube is connected with the positive electrode of the fast recovery diode D2 and one end of the primary winding of the voltage device, the negative electrode of the fast recovery diode D2 is connected with the negative electrode of the transient voltage suppression diode D1, and the positive electrode of the transient voltage suppression diode D1 is connected with the lead-out pin VDC and the other end of the primary winding of the voltage device; the transient voltage suppression diode D1 and the fast recovery diode D2 are built in the existing field effect transistor structure to be packaged together to form a field effect transistor with a built-in absorption loop; the transient voltage suppression diode D1 adopts FR series, and the fast recovery diode D2 adopts a TVS tube to form a high-voltage field effect tube; the transient voltage suppression diode D1 adopts FR107, FR157 or FR207, and the fast recovery diode D2 adopts P6KE 180-240 (600W 180V-240V) or 1.5KE180-240 (1.5 KW 180V-240V).

Example 3

In the field effect transistor with built-in absorption loop as described in embodiment 1 or 3, in fig. 1, the G pole and S pole of the original MOSFET tube remain unchanged, the D pole is also connected to one end of the primary winding of the transformer, and the built-in pin names VDC of D1 and D2 are directly connected to one end of the rectified and filtered mains supply and the VDC end of the primary winding of the transformer;

wherein the corresponding MOSFETs will have different D1, D2 configurations, the following table is the main configuration:

table one:

D1	D2	MOSFET(Q1)
			P6K220	FR107	600-650V,1A-7A
P6K220	FR157	600-650V,7A-12A
			P6K330	FR107	800V-1200V1-3A

d1 will have different values applied to different occasions, resulting in different models of the series of integrated MOSFETs;

q1 is mainly a planar MOSFET, is not limited to the utilization of a super junction MOSFET, and can be realized in other specific forms;

the field effect transistor integrated with the built-in absorption circuit is characterized in that two diodes of different types are added inside, D1 is a TVS (transient voltage suppression diode) and D2 is a fast recovery diode, and the pins of the package are changed from 3 pins to 4 pins;

the utility model is expanded into a high-voltage field effect tube with a built-in absorption circuit of 4 pins based on the TO220 iron package or the TO220F plastic package, which is not limited TO the package described in the specification, and other types of packages can realize the technical scheme of the utility model in other specific forms.

Example 4

The utility model adds a VDC pin on the basis of the prior field effect transistor to realize a high-voltage field effect transistor with a built-in absorption circuit, and the figure 3 is a designed packaging effect diagram; the width of the package is increased by about 2.5mm on the original basis; the other plastic package and the iron package are similar to the original plastic package and the iron package;

PIN 1 is the added VDC PIN, and is used for connecting a flyback switching power supply to the direct-current voltage after rectification and filtration of the mains supply;

pin 2 is still the gate of the MOSFET, i.e., the G-pole;

pin 3 is still the drain, i.e., D-pole, of the MOSFET;

pin 4 is still the source, i.e., S-pole, of the MOSFET;

the utility model integrates a high-voltage field effect transistor with a built-in absorption circuit formed by D1, D2 and Q1, and the package is provided with a pin as a VDC pin as shown in figure 3, and is used for connecting a flyback switching power supply to a direct-current voltage after rectification and filtration of a commercial power;

after D1 and D2 are built in a conventional high-voltage planar MOSFET, different series of high-voltage field effect transistors with built-in absorption circuits are formed;

q1 is not limited to a planar high-voltage MOSFET, and a high-voltage super-junction MOSFET can be used as the requirement of the technical scheme of the utility model;

the utility model relates to a field effect transistor with an internal absorption circuit, which provides a simplified field effect transistor (MOSFET) for the design of a switching power supply, and the internal absorption circuit omits the external absorption circuit of the original design, reduces the design space of a PCB and further reduces the size of the power supply. Meanwhile, in the design of a switch power supply with larger power, a radiator is arranged on Q1 to radiate heat, but D1 and D2 are difficult to install the radiator due to installation, and self-heating can only be cooled by air; after the technical scheme of the utility model is improved, D1, D2 and Q1 are packaged into a whole, and a radiator is arranged together, so that the radiator can radiate heat at the same time.

Any of the above-described embodiments of the present disclosure, unless otherwise indicated, if they disclose a numerical range, then the disclosed numerical range is the preferred numerical range, as will be appreciated by one of skill in the art: the preferred numerical ranges are merely those of the many possible numerical values where technical effects are more pronounced or representative. Since the numerical values are more and cannot be exhausted, only a part of the numerical values are disclosed to illustrate the technical scheme of the utility model, and the numerical values listed above should not limit the protection scope of the utility model.

If the terms "first," "second," etc. are used herein to define a part, those skilled in the art will recognize that: the use of "first" and "second" is used merely to facilitate distinguishing between components and not otherwise stated, and does not have a special meaning.

In addition, terms used in any of the above-described aspects of the present disclosure to express positional relationship or shape are meant to include a state or shape that is similar, analogous or approaching thereto unless otherwise stated. Any part provided by the utility model can be assembled by a plurality of independent components, and can also be manufactured by an integral forming process.

Finally, it should be noted that the above-mentioned embodiments are only for illustrating the technical scheme of the present utility model and are not limiting; while the utility model has been described in detail with reference to the preferred embodiments, those skilled in the art will appreciate that: modifications may be made to the specific embodiments of the present utility model or equivalents may be substituted for part of the technical features thereof; without departing from the spirit of the utility model, it is intended to cover the scope of the utility model as claimed.

Claims (4)

1. The field effect tube with the built-in absorption loop comprises a grid G, a source S and a drain D, and is characterized in that the drain D of the field effect tube is connected with the positive electrode of a fast recovery diode D2, the negative electrode of the fast recovery diode D2 is connected with the negative electrode of a transient voltage suppression diode D1, the positive electrode of the transient voltage suppression diode D1 is connected with a lead-out pin VDC, and the grid G and the source S are kept unchanged.

2. The field effect tube with built-in absorption loop according to claim 1, wherein the drain electrode D of the field effect tube is connected to the positive electrode of the fast recovery diode D2 and one end of the primary winding of the voltage device, the negative electrode of the fast recovery diode D2 is connected to the negative electrode of the transient voltage suppression diode D1, and the positive electrode of the transient voltage suppression diode D1 is connected to the lead-out pin VDC and the other end of the primary winding of the voltage device.

3. The field effect transistor with built-in absorption loop according to claim 1 or 2, wherein the transient voltage suppression diode D1 is an FR series, and the fast recovery diode D2 is a TVS transistor to form a high voltage field effect transistor.

4. A field effect transistor with built-in absorption loop according to claim 3, wherein said transient voltage suppressing diode D1 is FR107, FR157 or FR207, and said fast recovery diode D2 is P6KE 180-240600W 180V-240V or 1.5KE180-2401 KW 180V-240V.