CN219592390U - Signal measurement circuit, battery management circuit, chip and electronic equipment - Google Patents
Signal measurement circuit, battery management circuit, chip and electronic equipment Download PDFInfo
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- CN219592390U CN219592390U CN202222874405.0U CN202222874405U CN219592390U CN 219592390 U CN219592390 U CN 219592390U CN 202222874405 U CN202222874405 U CN 202222874405U CN 219592390 U CN219592390 U CN 219592390U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The application provides a signal measuring circuit, a battery management circuit, a chip and an electronic device, wherein the signal measuring circuit comprises: the sampling circuit is used for sampling the voltage signal to obtain an input voltage signal; the integrating circuit is used for receiving an input voltage signal and a scaling control signal following the input voltage signal and scaling the input voltage signal according to the scaling control signal; and the analog-to-digital conversion circuit is used for converting the scaled input voltage signal into a digital signal. The application can reduce the requirements of analog-digital conversion on signals with larger range in terms of voltage resistance, response speed, linearity and the like.
Description
Technical Field
The present application relates to the field of electronic circuits, and more particularly, to a signal measurement circuit, a battery management circuit, a chip, and an electronic device.
Background
In the related art, when the dynamic range of an input signal is large, there are high requirements on withstand voltage, dynamic range, and the like of a subsequent analog-to-digital converter (ADC). For example, when the dynamic range of the input signal is 0 to 100V, it is difficult for a common analog-to-digital converter to withstand a voltage of up to 100V, and such a wide range of voltage cannot be measured.
Disclosure of Invention
In view of the above problems, embodiments of the present utility model provide a signal measurement circuit, a battery management circuit, a chip, and an electronic device, so as to at least partially solve the technical problems of high requirements on withstand voltage, response speed, linearity, and the like of analog-to-digital conversion when the dynamic range of an input signal is large.
In a first aspect, an embodiment of the present utility model provides a signal measurement circuit, including: the sampling circuit is used for sampling the voltage signal to obtain an input voltage signal; the integrating circuit is connected with the sampling circuit and is used for receiving an input voltage signal and a scaling control signal and scaling the input voltage signal according to the scaling control signal, wherein the scaling control signal follows the input voltage signal; and the analog-to-digital conversion circuit is connected with the integration circuit and is used for converting the scaled input voltage signal into a digital signal.
Optionally, the integrating circuit includes: an operational amplifier; the integrating capacitor array is connected between the input end and the output end of the operational amplifier and comprises a plurality of integrating capacitors; and the switch network is connected with the integrating capacitor array and is used for selecting one or more integrating capacitors in the integrating capacitor array to participate in integration so that the scaling ratio of the integrating circuit follows the input voltage signal.
Optionally, the signal measurement circuit further comprises: the multiplexer is connected with the sampling circuit and the integrating circuit and is used for receiving the selection signal, selecting one voltage signal from the multiple voltage signals according to the selection signal and inputting the one voltage signal to the sampling circuit; and the first switch control circuit is connected with the integration circuit and is used for receiving the selection signal and controlling the switch network to select one or more integration capacitors according to the selection signal so that the scaling ratio of the integration circuit follows the input voltage signal.
Optionally, the signal measurement circuit further comprises: and the second switch control circuit is connected with the sampling circuit and the switch network and is used for receiving the input voltage signal and controlling the switch network to select one or more integrating capacitors according to the input voltage signal so as to enable the scaling ratio of the integrating circuit to be matched with the voltage range of the input voltage signal.
Optionally, the analog-to-digital conversion circuit includes: a digital-to-analog converter, a successive approximation logic circuit and the operational amplifier; the signal measurement circuit further comprises a switch circuit; the switch circuit is connected with the digital-to-analog converter, the operational amplifier and the integrating capacitor array and is used for enabling the operational amplifier and the integrating capacitor array to form the integrating circuit; or the operational amplifier is connected with the digital-to-analog converter so that the operational amplifier, the digital-to-analog converter and the successive approximation logic circuit form the analog-to-digital conversion circuit.
Optionally, at least part of the capacitances in the array of integrating capacitances are also used as at least part of the weighting capacitances in the digital-to-analog converter.
Optionally, the switching circuit includes: the first switch is connected between the input end and the output end of the operational amplifier; the second switch is connected between the integrating capacitor array and the output end of the operational amplifier; the third switch is connected between the input end of the operational amplifier and the sampling circuit; and the fourth switch is connected between the output end of the digital-to-analog converter and the input end of the operational amplifier.
Optionally, the first switch is used for being closed in a sampling stage, and shorting the output end and the input end of the operational amplifier to form a buffer; the third switch is used for being closed in a scaling stage, and the output end of the sampling circuit is connected with the input end of the operational amplifier; the second switch is used for being closed in a scaling stage, and the integrating capacitor array is connected between the input end and the output end of the operational amplifier to form the integrating circuit; and switching off in a conversion stage, and disconnecting the connection between the integrating capacitor array and the output end of the operational amplifier; the fourth switch is used for closing in the conversion stage and connecting the output end of the digital-to-analog converter and the integrating capacitor array to the input end of the operational amplifier.
Optionally, the switching circuit further comprises: the fifth switch is connected between the integrating capacitor array and the reference voltage end; the sixth switch is connected between the output end of the sampling circuit and the common-mode voltage end; the third switch, the fifth switch and the sixth switch are used for being closed in the sampling stage, and the integrating capacitor array is connected between a common-mode voltage end and a reference voltage end.
Optionally, the sampling circuit includes: the first end of the first sampling capacitor is connected with the first input end of the integrating circuit; the first end of the second sampling capacitor is connected with the second input end of the integrating circuit; in the sampling stage, the second end of the first sampling capacitor is connected with the first voltage end, and the second end of the second sampling capacitor is connected with the second voltage end; the voltage signal sampled by the sampling circuit is the voltage difference between the first voltage end and the second voltage end.
Optionally, the signal measurement circuit further comprises: a crossbar circuit for: in the scaling stage, connecting the second end of the first sampling capacitor to the second voltage end, and connecting the second end of the second sampling capacitor to the first voltage end; or the second ends of the first sampling capacitor and the second sampling capacitor are connected to a preset voltage end so as to adjust the voltages of the second ends of the first sampling capacitor and the second sampling capacitor.
In a second aspect, an embodiment of the present application provides a battery management circuit, including a signal measurement circuit of an embodiment of the present application.
Optionally, the voltage signal sampled by the sampling circuit is a voltage difference between two ends of any one or more batteries in the plurality of batteries.
In a third aspect, an embodiment of the present application provides a chip including the signal measurement circuit or the battery management circuit of the embodiment of the present application.
In a fourth aspect, an embodiment of the present application provides an electronic device, including: the signal measuring circuit, the battery management circuit or the chip of the embodiment of the application.
According to one or more technical schemes provided by the embodiment of the application, the voltage signal is sampled by the sampling circuit to obtain the input voltage signal, the integrating circuit scales the input voltage signal according to the scaling signal following the input voltage signal, and the analog-to-digital conversion circuit performs analog-to-digital conversion on the scaled input voltage signal, so that the requirements on the voltage resistance, response speed, linearity and the like of analog-to-digital conversion on the voltage signal with a large range are reduced.
Drawings
Further details, features and advantages of the application are disclosed in the following description of exemplary embodiments with reference to the following drawings, in which:
FIG. 1 shows a schematic block diagram of a signal measurement circuit according to an exemplary embodiment of the application;
FIG. 2 shows a schematic block diagram of a signal measurement circuit according to an exemplary embodiment of the application;
FIG. 3 shows a schematic block diagram of a signal measurement circuit according to an exemplary embodiment of the application;
FIG. 4 shows a schematic block diagram of a scaling control according to an exemplary embodiment of the present application;
FIG. 5 shows a schematic block diagram of an integrated circuit according to an exemplary embodiment of the application;
fig. 6 shows a schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the application;
FIG. 7 shows a schematic block diagram of an analog-to-digital conversion circuit and an integrating circuit multiplexing operational amplifier according to an exemplary embodiment of the application;
FIG. 8 shows a schematic block diagram of an analog-to-digital conversion circuit and an integrating circuit multiplexing operational amplifier according to an exemplary embodiment of the application;
FIG. 9 shows a schematic block diagram of a signal measurement circuit of a differential signal according to an exemplary embodiment of the application;
fig. 10 shows a schematic block diagram of a battery management circuit according to an exemplary embodiment of the present application;
FIG. 11 shows a schematic block diagram of a battery management circuit according to an exemplary embodiment of the present application;
Fig. 12 shows a flowchart of a signal measurement method according to an exemplary embodiment of the present application.
Detailed Description
Embodiments of the present application will be described in more detail below with reference to the accompanying drawings. While the application is susceptible of embodiment in the drawings, it is to be understood that the application may be embodied in various forms and should not be construed as limited to the embodiments set forth herein, but rather are provided to provide a more thorough and complete understanding of the application. It should be understood that the drawings and embodiments of the application are for illustration purposes only and are not intended to limit the scope of the present application.
It should be understood that the various steps recited in the method embodiments of the present application may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the application is not limited in this respect.
The term "including" and variations thereof as used herein are intended to be open-ended, i.e., including, but not limited to. The term "according to" is based, at least in part, on. The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments. Related definitions of other terms will be given in the description below. It should be noted that the terms "first," "second," and the like herein are merely used for distinguishing between different devices, modules, or units and not for limiting the order or interdependence of the functions performed by such devices, modules, or units.
It should be noted that references to "one", "a plurality" and "a plurality" in this disclosure are intended to be illustrative rather than limiting, and those skilled in the art will appreciate that "one or more" is intended to be construed as "one or more" unless the context clearly indicates otherwise.
The embodiment of the application provides a signal measuring circuit.
Fig. 1 shows a schematic block diagram of a signal measurement circuit according to an exemplary embodiment of the present application, as shown in fig. 1, the signal measurement circuit includes: the sampling circuit is used for sampling the voltage signal to obtain an input voltage signal; the integrating circuit is connected with the sampling circuit and is used for receiving an input voltage signal and a scaling control signal following the input voltage signal and scaling the input voltage signal according to the scaling control signal; and the analog-to-digital conversion circuit is connected with the integration circuit and is used for converting the scaled input voltage signal into a digital signal. By adopting the embodiment, the voltage signal is sampled by the sampling circuit to obtain the input voltage signal, the integrating circuit scales the input voltage signal according to the scaling signal following the input voltage signal, and the analog-to-digital conversion circuit performs analog-to-digital conversion on the scaled input voltage signal, so that the requirements on the voltage resistance, response speed, linearity and the like of analog-to-digital conversion on the voltage signal with a larger range are reduced.
In this embodiment, the input voltage signal may be a single-ended input signal or a differential input signal, which is not limited in this embodiment. The analog-to-digital conversion circuit may be a Flash type, a successive approximation type, a sigma-delta type or a hybrid type analog-to-digital conversion circuit, and the present embodiment is not limited thereto. In practical applications, the analog-to-digital conversion circuit may be selected according to the analog-to-digital conversion performance requirements.
In this embodiment, the scaling control signal follows the input voltage signal, which means that the scaling varies with the amplitude of the input voltage signal, e.g. the larger the amplitude of the input voltage signal, the larger the scaling factor. Since the scaling ratio follows the input voltage signal variation rather than being fixed, the input voltage signal can be scaled to within the preset voltage range even if the input voltage is dynamically varied over a large range.
In this embodiment, the scaling control signal follows an input voltage signal, which is a signal obtained by sampling the voltage signal. For example, when the signal measurement circuit is applied to a battery management system, the voltage signal may be a voltage difference between two ends of any one or more batteries in the battery pack, and the input voltage signal is a signal obtained by sampling the voltage difference.
Two possible implementations of the scaling control signal are described below.
Fig. 2 shows a schematic block diagram of a signal measurement circuit according to an exemplary embodiment of the present application, as shown in fig. 2, the signal measurement circuit includes: the circuit comprises a sampling circuit, an integrating circuit, an analog-to-digital conversion circuit, a multiplexer and a first switch control circuit. Wherein, the sampling circuit, the integrating circuit and the analog-to-digital conversion circuit refer to the previous description of the specification. The multiplexer may employ a Multiplexer (MUX), a switching network, etc., but is not limited thereto.
As shown in fig. 2, the multiplexer is connected to the sampling circuit, and is configured to receive a selection signal, and select one voltage signal from the multiple voltage signals (shown as the 1 st, 2 nd and n th paths in fig. 2) according to the selection signal, and input the selected voltage signal to the sampling circuit. The first switch control circuit is connected with the integration circuit and is used for receiving the selection signal and generating a scaling control signal corresponding to the selection signal. The voltage of each voltage signal corresponds to a preset voltage range, and the voltage of the multiple voltage signals corresponds to multiple preset voltage ranges. The scaling control signal is determined based on the selection signal. As an example, the multiple voltage signals may be voltage differences between two ends of any one or more batteries of the battery string, the battery string may include multiple voltage ends, and the voltage difference between any two voltage ends may be used as the one-way voltage signal.
Taking voltage signals as examples, for example, the dynamic range of an analog-to-digital conversion circuit is 0-2V, the amplitude range of a first path of voltage signals is 0-5V, the amplitude range of a second path of voltage signals is 0-10V, the amplitude range of a third path of voltage signals is 0-15V, the amplitude range of a fourth path of voltage signals is 0-20V, when a multiplexer selects the first path of voltage signals based on a selection signal, a first switch control circuit generates a control signal with scaling ratio of 1/2.5, and the first path of voltage signals are scaled to 0-2V; when the multiplexer selects the second path of voltage signals based on the selection signals, the first switch control circuit generates control signals with scaling ratio of 1/5, and the second path of voltage signals are scaled to 0-2V; when the multiplexer selects a third voltage signal based on the selection signal, the first switch control circuit generates scaling ratio of 1/7.5, and the third voltage signal is 0-2V after scaling; when the multiplexer selects the fourth path of voltage signal based on the selection signal, the first switch control circuit generates scaling ratio of 1/10 and the fourth path of voltage signal is scaled to 0-2V. The scaling ratio refers to a ratio of the voltage amplitude after scaling to the voltage amplitude before scaling, for example, a scaling ratio of 1/2.5 refers to a scaling ratio of 2.5V voltage to 1V after scaling, which is equivalent to a scaling multiple of 2.5 times.
Fig. 3 shows a schematic block diagram of a signal measurement circuit according to an exemplary embodiment of the present application, as shown in fig. 3, the signal measurement circuit includes: the analog-to-digital conversion circuit comprises a sampling circuit, an integrating circuit, an analog-to-digital conversion circuit and a second switch control circuit. Wherein, the sampling circuit, the integrating circuit and the analog-to-digital conversion circuit refer to the previous description of the specification.
As shown in fig. 3, the second switch control circuit is connected to the sampling circuit and is configured to receive an input voltage signal and output a scaling control signal according to the input voltage signal. The second switch control circuit may determine the range of the input voltage signal by using a comparison circuit, a low-precision analog-to-digital conversion, or the like, so as to output the scaling control signal according to the input voltage signal, which is not limited in this embodiment.
Taking a voltage signal as an example, for example, the dynamic range of the analog-to-digital conversion circuit is 0-2V, the dynamic range of the voltage signal is 0-20V, and the sampling circuit samples the voltage signal to obtain an input voltage signal. When the input voltage signal obtained by sampling is detected to be smaller than 5V, the scaling ratio is 1/2.5, and the input voltage signal is 0-2V after scaling; when the input voltage signal obtained by detection sampling is between 5 and 10V, the scaling ratio is 1/5, and the input voltage signal is 1 to 2V after scaling.
The integrating circuit comprises an integrating capacitor, the scaling ratio of the integrating circuit is related to the size of the integrating capacitor, and the greater the integrating capacitor is, the higher the scaling degree is, namely the greater the scaling multiple is. As an embodiment, as shown in fig. 4, the integrating circuit includes an integrating capacitor array and a switch network, the scaling control signal is a switch control signal of the switch network, and the switch network is configured to receive the scaling control signal, and select an integrating capacitor of the integrating capacitor array according to the scaling control signal to obtain a corresponding scaling ratio. As an example, the integrating capacitor array comprises a plurality of integrating capacitors having the same capacitance value, and the switching network gates a corresponding number of integrating capacitors according to the scaling control signal, thereby obtaining a corresponding scaling. As another example, the integrating capacitor array includes a plurality of integrating capacitors having different capacitance values, and the switching network gates the integrating capacitors of the corresponding capacitance values according to the scaling control signal, thereby obtaining the corresponding scaling. As an embodiment, the switching network may use a low voltage switch since the integrating circuit is in the low voltage domain.
The signal measurement process of the signal measurement circuit of the present embodiment includes a sampling stage, a scaling stage, and a conversion stage in chronological order. In some embodiments, the sampling circuit is configured to sample the voltage signal in a sampling phase to obtain an input voltage signal; the integrating circuit is used for scaling the input voltage signal according to the scaling control signal in the scaling stage; the analog-to-digital conversion circuit is used for converting the scaled input voltage signal into a digital signal in a conversion stage.
Exemplary embodiments of the integrating circuit, the analog-to-digital conversion circuit, and the sampling circuit are described below, respectively.
Fig. 5 shows a schematic block diagram of an integration circuit according to an exemplary embodiment of the application, as shown in fig. 5, the integration circuit comprising an operational amplifier, an integration capacitance array and a switching network, wherein the switching network is arranged to receive a scaling control signal and to select the integration capacitance of the integration capacitance array in dependence of the scaling control signal. Therefore, the capacitance of the integrating capacitor array can be adaptively adjusted according to the change of the scaling control signal, and the scaling of the integrating circuit is adjusted so as to enable the integrating circuit to follow the amplitude of the input voltage signal.
In the example of fig. 5 and 2 in combination, a first switch control circuit is coupled to the switching network for receiving the selection signal and controlling the switching network to select one or more integrating capacitances based on the selection signal such that the scaling of the integrating circuit follows the input voltage signal.
In the example of fig. 5 and 3, the second switch control circuit is connected to the sampling circuit and the switch network, and is configured to receive the input voltage signal, and control the switch network to select one or more integration capacitors according to the input voltage signal, so as to match the scaling ratio of the integration circuit to the voltage range of the input voltage signal.
Fig. 6 shows a schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of the application, as shown in fig. 6, comprising a digital-to-analog converter (DAC), a successive approximation logic circuit and a comparator. Wherein the digital-to-analog converter may be a capacitive DAC, a resistive DAC, or a hybrid capacitive-resistive DAC.
Because the operational amplifier of the integrating circuit and the comparator of the analog-to-digital conversion circuit are offset, the offset has larger limitation in a high-precision signal acquisition scene. For this reason, in some embodiments, the operational amplifier of the integrating circuit is multiplexed as the comparator of the analog-to-digital conversion circuit, so that the offset of the operational amplifier in the scaling stage and the offset of the comparator in the conversion stage can cancel each other, thereby improving the analog-to-digital conversion accuracy.
Exemplary embodiments of multiplexing operational amplifiers for analog-to-digital conversion circuits and integrating circuits are described below.
In some embodiments, the operational amplifier is used to: in the scaling stage, an integrating circuit is formed with the integrating capacitor array to scale the input voltage signal; in the conversion stage, the analog-to-digital conversion circuit is formed by the analog-to-digital conversion circuit, the digital-to-analog conversion circuit and the successive approximation logic circuit, and the scaled input voltage signal is converted into a digital signal.
As an embodiment, the multiplexing of the analog-to-digital conversion circuit and the integrating circuit to the operational amplifier is realized by a switching circuit. The switch circuit is connected with the digital-to-analog converter, the operational amplifier and the integrating capacitor array and is used for forming an integrating circuit by the operational amplifier and the integrating capacitor array; or the operational amplifier is connected with the digital-to-analog converter so that the operational amplifier, the digital-to-analog converter and the successive approximation logic circuit form an analog-to-digital conversion circuit. The switching circuit is used for shorting the output end and the input end of the operational amplifier to form a buffer in the sampling stage; in the scaling stage, connecting the output end of the sampling circuit with the input end of the operational amplifier, and connecting the integrating capacitor array between the input end and the output end of the operational amplifier to form an integrating circuit; in the conversion phase, the connection between the integrating capacitor array and the output of the operational amplifier is disconnected, and the output of the digital-to-analog converter and the integrating capacitor array are connected to the input of the operational amplifier. Optionally, the switching circuit is further configured to: in the sampling phase, an array of integrating capacitors is connected between the common mode voltage terminal and the reference voltage terminal.
Fig. 7 is a schematic block diagram of an analog-to-digital conversion circuit and an integrating circuit multiplexing operational amplifier according to an exemplary embodiment of the present application, taking an input voltage signal as a single-ended signal as an example, and as shown in fig. 7, a switching circuit includes: a first switch (S1 in the figure) connected between a first input terminal (a-terminal in the figure) and an output terminal of the operational amplifier; a second switch (S2 in the figure) connected between the integrating capacitor array and the output terminal of the operational amplifier; a third switch (S3 in the figure) connected between the first input terminal of the operational amplifier and the sampling circuit; a fourth switch (S4 in the figure) is connected between the output of the digital-to-analog converter and the second input of the operational amplifier (+ in the figure).
As one implementation mode, the first switch is used for being closed in the sampling stage, and the output end and the input end of the operational amplifier are short-circuited to form a buffer; the third switch is used for being closed in the scaling stage, and the output end of the sampling circuit is connected with the input end of the operational amplifier; the second switch is used for being closed in the scaling stage, and the integrating capacitor array is connected between the input end and the output end of the operational amplifier to form an integrating circuit; and switching off in the conversion stage, and disconnecting the connection between the integrating capacitor array and the output end of the operational amplifier; the fourth switch is used for closing in the conversion stage and connecting the output end of the digital-to-analog converter and the integrating capacitor array to the input end of the operational amplifier.
A switching circuit, further comprising: a fifth switch (S5 in the figure) connected between the integrating capacitor array and the reference voltage terminal; a sixth switch (S61 and S62 in the figure) connected between the output terminal of the sampling circuit and the common mode voltage terminal; the third switch, the fifth switch and the sixth switch are used for closing in the sampling stage, and the integrating capacitor array is connected between the common-mode voltage end and the reference voltage end.
As shown in reference 7, before the voltage signal is sampled in the sampling stage, the switches S3, S5, S61 and S62 are all closed, and the integrating capacitor array is connected between the common-mode voltage terminal and the reference voltage terminal, and the voltages at the two ends of the integrating capacitor array are the common-mode voltage VCM and the reference voltage Vref, respectively. During sampling, S3 may be turned off, and the sampling circuit samples the voltage signal. In the sampling stage, S1 is closed, S2 is opened, S4 is opened, the output end and the input end of the operational amplifier are short-circuited to form a buffer, and the voltage of the output end of the operational amplifier follows the voltage of the first input end.
Referring to fig. 7, during the scaling phase, S4 remains open, S61 and S62 open, and S3 closed connects the output of the sampling circuit with the input of the operational amplifier; s1 is opened, S2 is closed, S5 is opened, an integrating circuit is formed by the integrating capacitor array and the operational amplifier, and the sampled voltage Vin is scaled. Taking Cs as an example of the capacitance of the sampling capacitor, after scaling, the voltage at the first input end of the operational amplifier may be expressed as Vref-vin×cs/Cint, where Cint represents the capacitance of the integrating capacitor.
Referring to fig. 7, in the conversion phase, S2 is opened and S4 is closed, the output terminal of the digital-to-analog converter is connected to the second input terminal (shown as a +terminal in the figure) of the operational amplifier, the integrating capacitor array is connected to the first input terminal (shown as a-terminal in the figure) of the operational amplifier, the operational amplifier serves as a comparator of the analog-to-digital conversion circuit, and the output terminal of the operational amplifier is connected to the successive approximation logic circuit. The successive approximation logic performs successive approximation logic such that the output voltage of the digital-to-analog converter (denoted as Vdac) successively approximates Vref-Vin Cs/Cint (i.e., the voltage at the first input of the operational amplifier), and thus the magnitude of the input voltage signal Vin can be determined based on Vdac and known Vref, cs, cint. The magnitude of the measured voltage signal can be further determined according to the scaling of Vin and the integrating circuit, so that the voltage signal is measured.
Fig. 8 is a schematic block diagram of a multiplexing operational amplifier of an analog-to-digital conversion circuit and an integrating circuit according to an exemplary embodiment of the present application, and the signal measurement circuit shown in fig. 8 is different from fig. 7 in that, in the conversion stage, both the output terminal of the analog-to-digital conversion circuit and the integrating capacitor array are connected to a first input terminal (shown as a-terminal in the figure) of the operational amplifier, and a second input terminal (shown as a +terminal in the figure) of the operational amplifier is connected to a reference voltage terminal to access the reference voltage Vref. The successive approximation logic circuit performs successive approximation logic such that the output voltage Vdac of the digital-to-analog converter successively approximates Vin Cs/Cint such that the voltage at the first input of the operational amplifier used as the comparator approximates the voltage Vref at the other end. Also, the magnitude of the input voltage signal Vin may be determined from Vdac and known Vref, cs, cint. The magnitude of the measured voltage signal can be further determined according to the scaling of Vin and the integrating circuit, so that the voltage signal is measured.
In some embodiments, an integrating capacitor array (shown with reference to fig. 5, 7, 8) is used to: an integrating circuit is formed by the scaling stage and the operational amplifier to scale the input voltage signal; at least part of the capacitance in the array of integrating capacitances is used as at least part of the weight capacitance in the digital-to-analog converter during the conversion phase. The digital to analog converter may comprise a capacitor array, a resistor array or a capacitor-resistor hybrid array that forms a capacitor array DAC or a capacitor-resistor hybrid DAC with the at least some of the capacitors in the integrating capacitor array. Therefore, the components of the signal measuring circuit can be reduced and the circuit area can be reduced by multiplexing the integrating capacitor array.
The signal measurement circuit will be described below taking a voltage signal as an example of a differential signal.
Fig. 9 shows a schematic block diagram of a signal measurement circuit of a differential signal according to an exemplary embodiment of the present application, as shown in fig. 9, the signal measurement circuit including a sampling circuit, an integrating circuit, and an analog-to-digital conversion circuit. The sampling circuit is used for sampling the voltage difference between the two input ends in a sampling stage to obtain an input voltage signal; the integrating circuit is used for scaling the input voltage signal in a scaling stage; and the analog-to-digital conversion circuit is used for converting the scaled input voltage signal into a digital signal in a conversion stage.
As shown in fig. 9, the sampling circuit includes a first sampling unit Cs1 and a second sampling unit Cs2. The voltage signal sampled by the sampling circuit is the voltage difference between the first voltage terminal and the second voltage terminal. The integrating circuit comprises an operational amplifier, a first integrating capacitor array and a second integrating capacitor array. The analog-to-digital conversion circuit comprises a successive approximation logic circuit, a first digital-to-analog converter and a second digital-to-analog converter.
As shown in fig. 9, the signal measurement circuit further includes: switches S11 and S12 (corresponding to the first switch), switches S21 and S22 (corresponding to the second switch), switches S31 and S32 (corresponding to the third switch), switches S41 and S42 (corresponding to the fourth switch), switch S11 being connected between the positive phase input terminal and the negative phase output terminal of the operational amplifier, and switch S12 being connected between the negative phase input terminal and the positive phase output terminal of the operational amplifier; the switch S21 is connected between the first integrating capacitor array and the negative phase output end of the operational amplifier, and the switch S22 is connected between the second integrating capacitor array and the positive phase output end of the operational amplifier; the switch S31 is connected to the non-inverting input terminal of the operational amplifier and C S 1, a switch S32 connected between the negative input terminal of the operational amplifier and C S 2 between the first ends of 2; the switch S41 is connected between the output terminal of the first digital-to-analog converter and the positive phase input terminal of the operational amplifier, and the switch S42 is connected between the output terminal of the second digital-to-analog converter and the negative phase input terminal of the operational amplifier. Optionally, the method further comprises: switches S51 and S52, switches S61 and S62. The switch S51 is connected between the first integrating capacitor array and the first reference voltage terminal Vref1, and the switch S52 is connected between the second integrating capacitor array and the second reference voltage terminal Vref 2; the switch S61 is connected between the VCM and the non-inverting input terminal of the operational amplifier, and the switch S62 is connected between the VCM and the operational amplifierBetween the negative phase inputs of the amplifier.
As an embodiment, the first sampling unit Cs1 and the second sampling unit Cs2 may be implemented by capacitors, which are referred to as a first sampling capacitor and a second sampling capacitor, respectively. In the sampling stage, the second end of the first sampling capacitor is connected to the first voltage end, and the second end of the second sampling capacitor is connected to the second voltage end. The signal measurement circuit further comprises a cross-switch circuit for: in the scaling stage, connecting the second end of the first sampling capacitor to the second voltage end, and connecting the second end of the second sampling capacitor to the first voltage end; or, the second ends of the first sampling capacitor and the second sampling capacitor are connected to a preset voltage end so as to adjust the voltages of the second ends of the first sampling capacitor and the second sampling capacitor.
The analog-to-digital conversion process of the signal measurement circuit shown in fig. 9 is exemplarily described below.
The analog-to-digital conversion process includes: a sampling stage, a scaling stage (also referred to as a gain stage) and a conversion stage.
Sampling: before the voltage signal is sampled, the switches S31, S32, S51, S52, S61 and S62 are all closed, the first integrating capacitor array and the second integrating capacitor array are connected between the common-mode voltage end and the reference voltage end, the voltages at the two ends of the first integrating capacitor array and the second integrating capacitor array are the common-mode voltage VCM and the reference voltage Vref respectively, and the crossbar circuit can disconnect the first sampling unit Cs1 and the second sampling unit Cs2 from the first voltage end and the second voltage end. At the time of sampling, the switches S21, S22, S41, and S42 are opened, and the switches S11, S12, S51, S52, S61, S62, S31, and S32 are closed. In the sampling stage, the operational amplifier is short-circuited to form a buffer, and the voltage of the output end of the operational amplifier follows the voltage of the input end. The first ends of the first sampling unit Cs1 and the second sampling unit Cs2 are connected with a common-mode voltage end, and the second ends of the first sampling unit Cs1 and the second sampling unit Cs2 are respectively connected with a first voltage end and a second voltage end by a cross switch circuit.
After the sampling is completed, the voltage difference between the first sampling unit Cs1 and the second sampling unit Cs2 is vin. The voltage at one end of the first integrating capacitor array is VCM, and the voltage at the other end of the first integrating capacitor array is Vref1; the voltage at one end of the second integrating capacitor array is VCM, and the voltage at the other end of the second integrating capacitor array is Vref2.
In the scaling stage, the crossbar circuit switches the voltage signals of the first sampling unit and the second sampling unit, connects the second end of the first sampling capacitor to the second voltage end, and connects the second end of the second sampling capacitor to the first voltage end, so that the voltage difference between the first sampling unit Cs1 and the second sampling unit Cs2 becomes 2×vin. In the scaling stage, the switches S11, S12, S61, S62, S41, S42, S51, S52 are opened, and the switches S21, S22, S31, S32 are closed. At this time, the operational amplifier, the first integrating capacitor array and the second integrating capacitor array form an integrating circuit, and the voltage difference between the first sampling unit and the second sampling unit is scaled. Assuming that the capacitance values of the first sampling unit and the second sampling unit are the same, and Cs is the same; the capacitance values of the first integrating capacitor array and the second integrating capacitor array are the same and are Cint; when the scaling is completed, the voltage at the negative output end of the operational amplifier is voutp=vref 1-Vin (Cs/Cint), the voltage at the positive output end is voutn=vref 2+vin (Cs/Cint), the output voltage is Voutp-voutn=2×vin (Cs/Cint), and Cs/Cint is the scaling ratio.
In the changeover phase, the switches S11, S12, S21, S22, S51, S52, S61 and S62 are open, and the switches S31, S32, S41 and S42 are closed. At this time, the analog-to-digital conversion circuit performs analog-to-digital conversion. The successive approximation logic circuit receives the comparison result output by the operational amplifier as the comparator, adjusts the output voltages of the first digital-to-analog converter and the second digital-to-analog converter according to the comparison result, and gradually approximates the voltage at the non-inverting input end and the voltage at the inverting input end of the comparator after multiple comparison and DAC adjustment. After the comparison of the preset times, the analog-to-digital conversion is completed, and a digital signal corresponding to the input voltage signal is obtained.
As an embodiment, during the conversion stage, the first digital-to-analog converter may multiplex at least part of the capacitances in the first integrating capacitor array, that is, at least part of the capacitances in the first integrating capacitor array may be used as the weight capacitances in the first digital-to-analog converter, so as to reduce the number of capacitances in the circuit and reduce the circuit area. In this case, all or part of the weight capacitances in the first digital-to-analog converter may come from the first integrating capacitance array. Of course, the first digital-analog converter and the first integrating capacitor array may be independent of each other, i.e., the first integrating capacitor array may not be multiplexed as the weight capacitor.
Similarly, during the conversion phase, the second digital-to-analog converter may multiplex at least part of the capacitances in the second integrating capacitor array, i.e., at least part of the capacitances in the second integrating capacitor array may be used as the weight capacitances in the second digital-to-analog converter, so as to reduce the number of capacitances in the circuit and reduce the circuit area. In this case, all or part of the weight capacitances in the second digital-to-analog converter may come from the second integrating capacitance array. Of course, the second digital-to-analog converter and the second integrating capacitor array may be independent of each other, i.e., the first integrating capacitor array may not be multiplexed as the weight capacitor.
As an embodiment, the signal measurement circuit as shown in fig. 9 may further include a first switching network and a second switching network (not shown in the figure). The first switch network is connected with the first integrating capacitor array, and the second switch network is connected with the second integrating capacitor array. The first switch network and the second switch network are used for receiving a scaling control signal, adjusting the capacitance values of the first integrating capacitor array and the second integrating capacitor array according to the scaling control signal, and adjusting the scaling by changing the Cint. As one embodiment, the first switch network and the second switch network select the integrating capacitances of the first integrating capacitor array and the second integrating capacitor array according to the scaling control signal, so as to adjust the Cint and further adjust the scaling. For example, the first and second arrays of integrating capacitances respectively comprise a plurality of integrating capacitances, the first and second switching networks respectively may comprise a plurality of switches, each of which may be respectively connected in series with one or a group of integrating capacitances, the integrating capacitance or capacitances in series with the switch being gated when the switch is closed. The more switches are closed, the more capacitors are gated, and accordingly, the larger the capacitance Cint of the integrating capacitor array is, so that the capacitance Cint of the integrating capacitor array can be adjusted by controlling the state of the switches, and the scaling ratio can be adjusted. Since the first capacitor array and the second capacitor array are in the low voltage domain, the first switch network and the second switch network may employ low voltage switches.
An embodiment of the scaling control signal is shown in fig. 2 or fig. 3, and will not be described herein.
The following description will take an application in battery management as an example.
The lithium ion battery has the advantages of high energy density, environment protection, convenient use and the like, and becomes an ideal power supply of new energy electronic products. The lithium batteries are widely applied to new energy automobiles, can be applied to the fields of battery energy storage, electric tools, electric vehicles, unmanned aerial vehicles, industrial robots and the like, and can be applied to consumer electronics industries such as mobile phones, notebooks, wearable equipment and the like, and the function of accurately monitoring the electric quantity of the batteries is required in the application scenes. The battery electric quantity monitoring is realized through an electric quantity meter, the electric quantity meter obtains charge (current time) information by sampling the current of the battery in a specified time window with high precision, and obtains corresponding electric quantity information through measuring the open-circuit voltage and then carrying out analog-digital conversion.
The battery sampling circuit in the related art can only sample fixed battery voltage, does not have a gain control function, and has higher requirements on voltage resistance, response speed, linearity and the like of the later-stage ADC when the battery voltage is large or large current flows. In addition, because of the offset of the comparator and the amplifier in the traditional sampling system, the system has a larger limitation in a high-precision signal acquisition scene. Therefore, under the application of a plurality of lithium batteries, the sampling circuit in the related art cannot meet the requirements of the ADC (analog to digital converter) for the fields of high-precision instruments and meters and sensing measurement.
The embodiment of the application provides a battery management circuit which realizes signal acquisition, level conversion and signal measurement through time division multiplexing. The voltage signals at two ends of a single battery or a plurality of batteries are sampled at high voltage through a cross switch, and a plurality of strings of batteries are selected in a time-sharing mode through switch array and integration capacitance self-adaptive adjustment. The charge movement, the high voltage-low voltage conversion and the signal acquisition and the gain scaling are realized through the sampling capacitor, the integrating capacitor and the operational amplifier. In the signal measurement phase: the differential operational amplifier is multiplexed into a comparator, and forms a successive approximation analog-to-digital converter (SAR-ADC) with an integrating capacitor and a digital-to-analog converter (DAC), and the successive approximation measurement is carried out on the battery voltage signals collected at two ends of the integrating capacitor, so that offset cancellation can be realized due to the multiplexing of the operational amplifier and the comparator architecture, and high-precision signal processing is realized.
Fig. 10 and 11 show schematic block diagrams of a battery management circuit according to an exemplary embodiment of the present application, as shown in fig. 10 and 11, the battery management circuit includes: a multiplexer (also called a multiplexer, because it is in the high voltage domain, labeled HV MUX in the figure), an array of integrating capacitors (labeled Cint in the figure) of sampling capacitors (labeled Cs in the figure), an operational amplifier (labeled OPA-COMP in the figure), a digital-to-analog converter (labeled DAC in the figure). Each integrating capacitor is connected with a switch. As shown in fig. 10 and 11, the multiplexer is in the high voltage domain (HVdomain), and the integrating capacitor array, the operational amplifier, and the digital-to-analog converter are in the low voltage domain (LVdomain). The high voltage domain is isolated from the low voltage domain by a sampling capacitor Cs. For ease of illustration, the switches in fig. 10 and 11 are labeled with their control signals, e.g., the switch labeled S0 indicates that the switches are controlled by the same control signal S0, are all closed when S0 is a close signal, and are all open when S0 is an open signal. In fig. 10 and 11, "s0+s1" indicates the logical relationship of or, that is, the switch is closed when either one of S0 and S1 is a close signal, and is opened when both S0 and S1 are open signals.
The difference between fig. 10 and fig. 11 is that in fig. 10, a separate integrating capacitor array and digital-to-analog converter DAC is used, the output of the digital-to-analog converter is connected to the input of the operational amplifier; in fig. 11, the digital-to-analog converter multiplexes at least part of the integrating capacitor array, the output end of the digital-to-analog converter is connected to the integrating capacitor array through the switch Sconv, and the output of the digital-to-analog converter is transferred to the input end of the operational amplifier through the integrating capacitor array.
The battery voltage acquisition measurement comprises a signal sampling stage, a signal gain stage and a signal conversion stage.
In the signal sampling stage, the multiplexer HV MUX selects two voltage terminals from the plurality of voltage terminals B1-Bn according to the clock signal Sn <1:n > to be connected to the sampling capacitor Cs, and the voltage difference between the two selected voltage terminals is a sampled voltage signal. By selecting the voltage terminals B1-Bn, the voltage at the two ends of any one or more batteries in the battery pack can be detected. By simultaneously controlling the capacitance of the integrating capacitor array Cint through Sn <1:n >, multiple scaling following the input voltage signal can be achieved, thereby enabling a wide range of battery voltage measurements.
Taking the example of selecting the voltage terminal Bx and the voltage terminal Bx-1 from the plurality of voltage terminals B1 to Bn, the voltage difference between the voltage terminal Bx and the voltage terminal Bx-1 is the sampled voltage signal Vin, the sampling stage Sconv is the closed signal, one end of the sampling capacitor Cs receives the voltage of the voltage terminal Bx or the voltage terminal Bx-1, the other end receives the common-mode voltage Vcm, and the voltage difference of the sampling capacitor Cs is Vin. S0 is a closing signal, S1 is an opening signal, and Sref is a closing signal. The op-amp input and output are now shorted to a buffer whose output always follows the input, the primary function being impedance transformation.
In the signal scaling stage, S0 and Sconv are open signals, S1 is a closed signal, sref is an open signal, the sampling voltage on the sampling capacitor Cs is 2×vin, the operational amplifier and the integrating capacitor Cint form an integrating scaling circuit, the sampling voltage is scaled, the scaling ratio depends on the ratio of the integrating capacitor Cint to the sampling capacitor Cs, and the capacitance of the integrating capacitor Cint is controlled by the clock signal Sn <1:n >, so that the scaling ratio can be dynamically adjusted to convert the sampling voltage in the high-voltage domain into the low-voltage domain for processing.
After the signal scaling is completed, the voltage of the positive phase output end of the operational amplifier isThe voltage at the negative phase output terminal is +.>The output voltage is: />
In the signal conversion stage, S0 is the off signal, S1 is the off signal, sref is the off signal, the DAC starts to work, the DAC, the integrating capacitor array and the operational amplifier (used as a comparator) form a successive approximation analog-to-digital converter (SAR-ADC), and Vadcn and Vadcp with different gears and the collected signal V are sequentially output through clock control ref_ -V inVadcn 、By comparison, the gear of Vadcn, vadcp is adjusted according to the output of the comparator, taking FIG. 11 as an example, the final V adcn The output voltage approaches +.>Error + -V LSB 2; final V adcp The output voltage approaches +.>Error + -V LSB /2. The digital control of the DAC is the digital output of the voltages at the two ends of the battery. At this stage, the operational amplifiers of the original scaling stage are multiplexed into comparators, and offset of the operational amplifiers/comparators of the scaling stage and the conversion stage can cancel each other out, thereby providing SAR-ADC accuracy.
In the embodiment, the voltage acquisition and detection of the high-voltage battery string is realized through the control of the cross switch, the conversion of different power domains of voltage signals is performed based on the charge integration of the active operational amplifier, and the analog-to-digital conversion of high-precision successive approximation is performed through multiplexing the integrating capacitor, the DAC and the operational amplifier into the comparator.
The embodiment of the application also provides a signal measurement method, as shown in fig. 12, comprising the following steps:
step S1201, sampling the voltage signal to obtain an input voltage signal;
step S1202, receiving an input voltage signal and a scaling control signal, and scaling the input voltage signal according to the scaling control signal, wherein the scaling control signal follows the input voltage signal;
in step S1203, the scaled input voltage signal is converted into a digital signal.
By adopting the embodiment, the input voltage signal is obtained by sampling the voltage signal, the input voltage signal is scaled according to the scaling signal following the input voltage signal, and the scaled input voltage signal is subjected to analog-to-digital conversion, so that the requirements on the voltage signal with a large range in terms of voltage resistance, response speed, linearity and the like are reduced.
The embodiment of the application also provides a chip, which comprises the circuit. The Chip may be, but is not limited to, a SOC (System on Chip) Chip, a SIP (System in package ) Chip. The chip performs analog-to-digital conversion on the scaled input voltage signal by scaling the input voltage signal, so that the requirements on voltage resistance, response speed, linearity and the like of analog-to-digital conversion on signals with a large range are reduced.
The embodiment of the application also provides electronic equipment, which comprises an equipment main body and the chip arranged in the equipment theme. The electronic device may be, but is not limited to, a weight scale, a body fat scale, a nutritional scale, an infrared electronic thermometer, a pulse oximeter, a body composition analyzer, a mobile power supply, a wireless charger, a quick charger, an on-board charger, an adapter, a display, a USB (Universal Serial Bus ) docking station, a stylus, a real wireless headset, a car center screen, a car, a smart wearable device, a mobile terminal, a smart home device. The intelligent wearing equipment comprises, but is not limited to, an intelligent watch, an intelligent bracelet and a cervical vertebra massage instrument. Mobile terminals include, but are not limited to, smartphones, notebook computers, tablet computers, POS (point of sales terminal, point of sale terminal) machines. The intelligent household equipment comprises, but is not limited to, an intelligent socket, an intelligent electric cooker, an intelligent sweeper and an intelligent lamp. By scaling the input voltage signal and performing analog-to-digital conversion on the scaled input voltage signal, the electronic equipment reduces the requirements on voltage resistance, response speed, linearity and the like of analog-to-digital conversion on signals with a large range.
The foregoing has outlined a detailed description of the signal measurement circuit, battery management circuit, chip, electronic device and method of the present application, and the detailed description of the principles and embodiments of the present application has been provided herein by way of example only to assist in the understanding of the method of the present application and its core ideas; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (15)
1. A signal measurement circuit, comprising:
the sampling circuit is used for sampling the voltage signal to obtain an input voltage signal;
the integrating circuit is connected with the sampling circuit and is used for receiving the input voltage signal and a scaling control signal following the input voltage signal and scaling the input voltage signal according to the scaling control signal;
and the analog-to-digital conversion circuit is connected with the integration circuit and is used for converting the scaled input voltage signal into a digital signal.
2. The signal measurement circuit of claim 1, wherein the integrating circuit comprises:
An operational amplifier;
the integrating capacitor array is connected between the input end and the output end of the operational amplifier and comprises a plurality of integrating capacitors;
and the switch network is connected with the integration capacitor array and is used for selecting one or more integration capacitors in the integration capacitor array to participate in integration so that the scaling ratio of the integration circuit follows the input voltage signal.
3. The signal measurement circuit of claim 2, further comprising:
the multiplexer is connected with the sampling circuit and is used for receiving a selection signal, selecting one voltage signal from multiple voltage signals according to the selection signal and inputting the voltage signal to the sampling circuit;
and the first switch control circuit is connected with the switch network and is used for receiving the selection signal and controlling the switch network to select one or more integration capacitors according to the selection signal so that the scaling ratio of the integration circuit follows the input voltage signal.
4. The signal measurement circuit of claim 2, further comprising:
and the second switch control circuit is connected with the sampling circuit and the switch network and is used for receiving the input voltage signal and controlling the switch network to select one or more integrating capacitors according to the input voltage signal so as to enable the scaling ratio of the integrating circuit to be matched with the voltage range of the input voltage signal.
5. The signal measurement circuit of claim 2, wherein the analog-to-digital conversion circuit comprises: a digital-to-analog converter, a successive approximation logic circuit and the operational amplifier; the signal measurement circuit further comprises a switch circuit;
the switch circuit is connected with the digital-to-analog converter, the operational amplifier and the integrating capacitor array and is used for enabling the operational amplifier and the integrating capacitor array to form the integrating circuit; or the operational amplifier is connected with the digital-to-analog converter so that the operational amplifier, the digital-to-analog converter and the successive approximation logic circuit form the analog-to-digital conversion circuit.
6. The signal measurement circuit of claim 5, wherein at least a portion of the capacitances in the array of integrating capacitances are further used as at least a portion of the weighting capacitances in the digital-to-analog converter.
7. The signal measurement circuit of claim 5, wherein the switching circuit comprises:
the first switch is connected between the input end and the output end of the operational amplifier;
the second switch is connected between the integrating capacitor array and the output end of the operational amplifier;
The third switch is connected between the input end of the operational amplifier and the sampling circuit;
and the fourth switch is connected between the output end of the digital-to-analog converter and the input end of the operational amplifier.
8. The signal measurement circuit of claim 7, wherein,
the first switch is used for being closed in a sampling stage, and the output end and the input end of the operational amplifier are short-circuited to form a buffer;
the third switch is used for being closed in a scaling stage, and the output end of the sampling circuit is connected with the input end of the operational amplifier;
the second switch is used for being closed in a scaling stage, and the integrating capacitor array is connected between the input end and the output end of the operational amplifier to form the integrating circuit; and switching off in a conversion stage, and disconnecting the connection between the integrating capacitor array and the output end of the operational amplifier;
the fourth switch is used for closing in the conversion stage and connecting the output end of the digital-to-analog converter and the integrating capacitor array to the input end of the operational amplifier.
9. The signal measurement circuit of claim 7, wherein the switching circuit further comprises:
The fifth switch is connected between the integrating capacitor array and the reference voltage end;
the sixth switch is connected between the output end of the sampling circuit and the common-mode voltage end;
the third switch, the fifth switch and the sixth switch are used for being closed in a sampling stage, and the integrating capacitor array is connected between a common-mode voltage end and a reference voltage end.
10. The signal measurement circuit of any one of claims 1-9, wherein the sampling circuit comprises:
the first end of the first sampling capacitor is connected with the first input end of the integrating circuit;
the first end of the second sampling capacitor is connected with the second input end of the integrating circuit;
in the sampling stage, the second end of the first sampling capacitor is connected to a first voltage end, and the second end of the second sampling capacitor is connected to a second voltage end;
the voltage signal sampled by the sampling circuit is a voltage difference between the first voltage end and the second voltage end.
11. The signal measurement circuit of claim 10, wherein the signal measurement circuit further comprises: a crossbar circuit for: in the stage of the scaling-up and scaling-down,
Connecting a second end of the first sampling capacitor to the second voltage end, and connecting a second end of the second sampling capacitor to the first voltage end; or alternatively
And connecting the second ends of the first sampling capacitor and the second sampling capacitor to a preset voltage end so as to adjust the voltages of the second ends of the first sampling capacitor and the second sampling capacitor.
12. A battery management circuit comprising a signal measurement circuit according to any one of claims 1 to 11.
13. The battery management circuit of claim 12 wherein the voltage signal sampled by the sampling circuit is a voltage difference between two terminals of any one or more of the plurality of batteries.
14. A chip comprising a circuit according to any one of claims 1 to 13.
15. An electronic device, comprising: a circuit according to any one of claims 1 to 13 or a chip according to claim 14.
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