CN219591384U

CN219591384U - Semiconductor device with a semiconductor device having a plurality of semiconductor chips

Info

Publication number: CN219591384U
Application number: CN202320282790.1U
Authority: CN
Inventors: 和田秀雄; 滨中启伸
Original assignee: Kioxia Corp
Current assignee: Kioxia Corp
Priority date: 2022-04-28
Filing date: 2023-02-22
Publication date: 2023-08-25
Anticipated expiration: 2033-02-22
Also published as: CN116981249A

Abstract

The semiconductor device of the present utility model includes a transistor. The memory cell array is disposed above the transistor. The 1 st semiconductor layer is provided above the memory cell array, and has a 1 st surface on the memory cell array side and a 2 nd surface on the opposite side to the 1 st surface. The 1 st metal wiring is disposed above the 2 nd surface and electrically connected to the 1 st semiconductor layer. The 2 nd metal wiring is provided in the same layer as the 1 st metal wiring above the 2 nd surface, and is not in contact with the 1 st metal wiring and the 1 st semiconductor layer. The 1 st contact is provided below the 1 st metal wiring, extends in the 1 st direction from the 1 st surface toward the 2 nd surface, and electrically connects one of the plurality of transistors to the 1 st metal wiring. The 2 nd contact is provided below the 2 nd metal wiring, extends in the 1 st direction, and electrically connects another one of the plurality of transistors to the 2 nd metal wiring.

Description

Semiconductor device with a semiconductor device having a plurality of semiconductor chips

[ citation of related utility model ]

The present utility model claims priority benefits based on the priority of the prior Japanese patent application No. 2022-74771 filed on 28 of 04 of 2022, and the prior Japanese patent application No. 2022-204771 filed on 21 of 12 of 2022, the entire contents of which are incorporated herein by reference.

Technical Field

The present embodiment relates to a semiconductor device.

Background

A semiconductor device is known in which a memory cell array is provided over a CMOS (Complementary Metal Oxide Semiconductor ) circuit. With such a semiconductor device, a structure is proposed in which a semiconductor source layer is provided over a memory cell array, and a metal source line is provided over the semiconductor source layer. By connecting the metal source line to the semiconductor source layer, the resistance of the entire source layer is reduced. However, the metal layer constituting the metal source line is used only as the source line, and cannot be used for other purposes.

Disclosure of Invention

An embodiment provides a semiconductor device in which a metal layer provided over a source layer of a semiconductor is used not only as a source line but also for other purposes.

The semiconductor device of the present embodiment includes a plurality of transistors. The memory cell array is disposed above the plurality of transistors. The 1 st semiconductor layer is provided above the memory cell array, and has a 1 st surface on the memory cell array side and a 2 nd surface on the opposite side to the 1 st surface. The 1 st metal wiring is disposed above the 2 nd surface and electrically connected to the 1 st semiconductor layer. The 2 nd metal wiring is provided in the same layer as the 1 st metal wiring above the 2 nd surface, and is not in contact with the 1 st metal wiring and the 1 st semiconductor layer. The 1 st contact is provided below the 1 st metal wiring, extends in the 1 st direction from the 1 st surface toward the 2 nd surface, and electrically connects one of the plurality of transistors to the 1 st metal wiring. The 2 nd contact is provided below the 2 nd metal wiring, extends in the 1 st direction, and electrically connects another one of the plurality of transistors to the 2 nd metal wiring.

According to the above configuration, a semiconductor device in which a metal layer provided over a source layer of a semiconductor is used not only as a source line but also for other purposes can be provided.

Drawings

Fig. 1 is a cross-sectional view showing a configuration example of a semiconductor device according to embodiment 1.

Fig. 2 is a plan view showing a laminate of embodiment 1.

Fig. 3 is a schematic cross-sectional view illustrating a three-dimensional structure of a memory cell of embodiment 1.

Fig. 4 is a schematic cross-sectional view illustrating a three-dimensional structured memory cell of embodiment 1.

Fig. 5 is a schematic plan view showing a metal wiring layer according to embodiment 1.

Fig. 6A is a schematic cross-sectional view of AA line in fig. 5.

Fig. 6B is a schematic cross-sectional view showing the comparative example of fig. 6A.

Fig. 6C is a schematic cross-sectional view of line BB in fig. 5.

Fig. 6D is a schematic cross-sectional view of the CC line in fig. 5.

Fig. 7 is a schematic plan view block diagram showing a metal wiring layer according to embodiment 1.

Fig. 8 is a graph showing a change in resistance value of the source layer according to embodiment 1.

Fig. 9 is a schematic plan view showing a metal wiring layer according to embodiment 2.

Fig. 10 is a graph showing a change in resistance value of the source layer according to embodiment 2.

Fig. 11 is a schematic plan view showing a metal wiring layer according to embodiment 3.

Fig. 12 is a graph showing a change in resistance value of the source layer according to embodiment 3.

Fig. 13 is a block diagram showing a configuration example of a semiconductor memory device to which any of the above embodiments is applied.

Fig. 14 is a circuit diagram showing an example of a circuit configuration of the memory cell array.

Fig. 15 is a cross-sectional view showing another configuration example of the semiconductor memory device.

Fig. 16 is a plan view showing a configuration example of the semiconductor device of embodiment 4.

Fig. 17 is a cross-sectional view showing a configuration example of the semiconductor device of embodiment 4.

Fig. 18 is a cross-sectional view showing a configuration example of the semiconductor device of embodiment 4.

Fig. 19 is a perspective view showing a configuration example of the semiconductor device of embodiment 4.

Detailed Description

Hereinafter, embodiments of the present utility model will be described with reference to the drawings. The present embodiment is not limited to the present utility model. The drawings are schematic diagrams or conceptual diagrams, and ratios of the respective parts and the like are not necessarily the same as those of the actual objects. In the description and drawings, the same elements as those described above with respect to the drawings that have already been shown are denoted by the same reference numerals, and detailed description thereof is omitted as appropriate.

(embodiment 1) fig. 1 is a cross-sectional view showing an example of the structure of a semiconductor device 1 according to embodiment 1. Hereinafter, the lamination direction of the laminate 20 is referred to as the Z direction. The Y direction is defined as 1 direction intersecting, for example, orthogonal to, the Z direction. For example, 1 direction intersecting with each of the Z direction and the Y direction, i.e., orthogonal to each other, is defined as the X direction. In the present specification, the X direction is an example of the 3 rd direction, the Y direction is an example of the 2 nd direction, and the Z direction is an example of the 1 st direction.

The semiconductor device 1 includes an array chip 2 having a memory cell array, and a CMOS chip 3 having a CMOS circuit. The array chip 2 and the CMOS chip 3 are bonded to each other on the bonding surface B1, and are electrically connected to each other via a wiring bonded to the bonding surface. Fig. 1 shows a state in which an array chip 2 is mounted on a CMOS chip 3.

The CMOS chip 3 includes a substrate 30, a transistor 31, a via hole 32, wirings 33 and 34, and an interlayer insulating film 35.

The substrate 30 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 31 is an NMOS (N-metal-Oxide-Semiconductor) or PMOS (P-metal-Oxide-Semiconductor) transistor provided over the substrate 30. The transistor 31 constitutes, for example, a CMOS circuit that controls the memory cell array of the array chip 2. The transistor 31 is an example of a plurality of logic circuits. Semiconductor elements such as a resistor element and a capacitor element other than the transistor 31 may be formed over the substrate 30.

The via 32 electrically connects the transistor 31 and the wiring 33, or the wiring 33 and the wiring 34. The wirings 33 and 34 constitute a multilayer wiring structure in the interlayer insulating film 35. The wiring 34 is embedded in the interlayer insulating film 35 and exposed substantially on the same plane as the surface of the interlayer insulating film 35. The wirings 33 and 34 are electrically connected to the transistor 31 and the like. The via hole 32 and the wirings 33 and 34 are made of low-resistance metal such as copper or tungsten. The interlayer insulating film 35 covers and protects the transistor 31, the via 32, and the wirings 33 and 34. As the interlayer insulating film 35, for example, an insulating film such as a silicon oxide film is used.

The array chip 2 includes a laminate 20, a pillar CL, a slit ST (LI), a semiconductor source layer BSL, a metal layer 40, a contact 29, and a bonding pad 50.

The laminated body 20 is disposed above the transistor 31 and is located in the Z direction with respect to the substrate 30. The laminate 20 is formed by alternately laminating a plurality of electrode films 21 and a plurality of insulating films 22 along the Z direction. The laminate 20 constitutes a memory cell array. For example, a conductive metal such as tungsten is used for the electrode film 21. As the insulating film 22, for example, an insulating film such as a silicon oxide film is used. The insulating film 22 insulates the electrode films 21 from each other. That is, the plurality of electrode films 21 are laminated in an insulated state from each other. The number of stacked electrode films 21 and insulating films 22 is arbitrary. The insulating film 22 may be a porous insulating film or an air gap, for example.

The 1 or more electrode films 21 at the upper and lower ends in the Z direction of the laminate 20 function as a source side select gate SGS and a drain side select gate SGD, respectively. The electrode film 21 between the source side select gate SGS and the drain side select gate SGD functions as a word line WL. The word line WL is a gate electrode of the memory cell MC. The drain-side select gate SGD is the gate electrode of the drain-side select transistor. The source side select gate SGS is disposed in an upper region of the stacked body 20. The drain-side select gate SGD is disposed in a lower region of the laminate 20. The upper region refers to a region of the laminate 20 on the side closer to the CMOS chip 3, and the lower region refers to a region of the laminate 20 on the side away from the CMOS chip 3 (on the side closer to the metal layer 40).

The semiconductor device 1 has a plurality of memory cells MC connected in series between a source side selection transistor and a drain side selection transistor. The structure in which the source side selection transistor, the memory cell MC, and the drain side selection transistor are connected in series is called a "memory string" or a "NAND (Not And) string. The memory string is connected to the bit line BL, for example, via a via 28. The bit line BL is a wiring 23 provided below the laminate 20 and extending in the X direction (the paper surface direction of fig. 1).

A plurality of columnar bodies CL are provided in the laminate 20. The column CL extends inside the laminate 20 so as to penetrate the laminate 20 in the laminate stacking direction (Z direction), and is provided from the via hole 28 connected to the bit line BL to the semiconductor source layer BSL. The internal structure of the columnar body CL will be described below. In addition, in the present embodiment, the columnar body CL has a high aspect ratio, and is thus formed in 2 segments in the Z direction. However, the columnar body CL may be formed in 1 stage.

In addition, a plurality of slits ST (LI) are provided in the laminate 20. The slit ST (LI) extends in the X direction and penetrates the laminate 20 in the lamination direction (Z direction) of the laminate 20. The slit ST (LI) is filled with an insulating film such as a silicon oxide film, and the insulating film is formed in a plate shape. The slit ST (LI) electrically separates the electrode film 21 of the laminate 20. Alternatively, an insulating film such as a silicon oxide film may be coated on the inner wall of the slit ST (LI), and a conductive material may be buried inside the insulating film. In this case, the conductive material also functions as the source wiring LI reaching the semiconductor source layer BSL. That is, the slit ST may be a source line LI electrically connected to the semiconductor source layer BSL and electrically separated from the electrode film 21 of the stacked body 20 constituting the memory cell array. The slit is also called ST (LI).

A semiconductor source layer BSL is provided on the laminate 20. The semiconductor source layer BSL is an example of the 1 st semiconductor layer. The semiconductor source layer BSL is provided corresponding to the laminate 20. The semiconductor source layer BSL has a 1 st surface F1 and a 2 nd surface F2 opposite to the 1 st surface F1. A stacked body 20 (memory cell array) is provided on the 1 st surface F1 side of the semiconductor source layer BSL, and a metal layer 40 is provided on the 2 nd surface F2 side. The metal layer 40 includes a source line 41 and a power line 42. The source line 41 and the power line 42 will be described below. The semiconductor source layer BSL is commonly connected to one end of the plurality of columns CL, and applies a common source potential to the plurality of columns CL in the same memory cell array 2 m. That is, the semiconductor source layer BSL functions as a common source electrode of the memory cell array 2 m. The semiconductor source layer BSL is made of a conductive material such as doped polysilicon. The metal layer 40 is made of a metal material having a lower resistance than the semiconductor source layer BSL, such as copper, aluminum, or tungsten. Further, 2s is a step portion of the electrode film 21 provided for the purpose of connecting the contact to each electrode film 21. Regarding the stepped portion 2s, description is made below with reference to fig. 2.

On the other hand, a bonding pad 50 is provided on the laminate 20 in a region where the semiconductor source layer BSL is not provided. The bonding pad 50 is an example of the 1 st electrode. The bonding pad 50 is connected to a metal wire or the like (not shown), and receives power supply from outside the semiconductor device 1. The bonding pad 50 is connected to the transistor 31 of the CMOS chip 3 via the contact 29, the wiring 24 and the wiring 34. Accordingly, an external power supply supplied from the bonding pad 50 is supplied to the transistor 31. The contact 29 is made of a low-resistance metal such as copper or tungsten.

In the present embodiment, the array chip 2 and the CMOS chip 3 are formed separately and bonded to the bonding surface B1. Therefore, the transistor 31 is not provided in the array chip 2. In addition, the stacked body 20 (memory cell array) is not provided in the CMOS chip 3. The transistor 31 and the laminate 20 are both located on the 1 st plane F1 side of the semiconductor source layer BSL. The transistor 31 is located on the opposite side of the 2 nd plane F2 where the metal layer 40 is located.

A through hole 28, a wiring 23, and a wiring 24 are provided below the laminate 20. The wirings 23 and 24 are buried in the interlayer insulating film 25 and exposed substantially on the same plane as the surface of the interlayer insulating film 25. The wirings 23 and 24 are electrically connected to the semiconductor body 210 of the pillar CL and the like. The through hole 28, the wiring 23, and the wiring 24 are made of low-resistance metal such as copper or tungsten. The interlayer insulating film 25 covers and protects the laminate 20, the via hole 28, the wiring 23, and the wiring 24. As the interlayer insulating film 25, for example, an insulating film such as a silicon oxide film is used.

The interlayer insulating film 25 and the interlayer insulating film 35 are bonded to each other on the bonding surface B1, and the wiring 24 and the wiring 34 are bonded to each other on the bonding surface B1 substantially on the same plane. Thus, the array chip 2 and the CMOS chip 3 are electrically connected via the wiring 24 and the wiring 34.

Fig. 2 is a schematic plan view showing the laminate 20. The laminate 20 includes a step portion 2s and a memory cell array 2m. The stepped portion 2s is provided at the edge of the laminated body 20. The memory cell array 2m is sandwiched or surrounded by the step portions 2s. The slit ST (LI) is provided from the step portion 2s at one end of the laminate 20 to the step portion 2s at the other edge of the laminate 20 through the memory cell array 2m. The slit SHE is provided at least in the memory cell array 2m. The slit SHE is shallower than the slit ST (LI) and extends substantially parallel to the slit ST (LI). The slit SHE is provided for electrically separating the electrode film 21 for each drain-side select gate SGD.

The portion of the laminate 20 sandwiched by 2 slits ST (LI) shown in fig. 2 is called a BLOCK (BLOCK). The blocks constitute, for example, the minimum unit of data erasure. The slit SHE is disposed within the block. The laminate 20 between the slit ST (LI) and the slit SHE is called finger (finger). The drain side select gates SGD are separated by fingers. Therefore, 1 finger structure in the block can be set to the selected state by the drain side select gate SGD at the time of data writing and reading.

Fig. 3 and 4 are schematic cross-sectional views illustrating a memory cell of a three-dimensional structure, respectively. The plurality of pillars CL are respectively disposed in memory cells MH provided in the laminate 20. Each of the pillars CL penetrates the laminate 20 from the upper end of the laminate 20 along the Z direction and reaches the inside of the laminate 20 and the inside of the semiconductor source layer BSL. The plurality of pillars CL each include a semiconductor body 210, a memory film 220, and a core layer 230. The column CL includes a core layer 230 provided at a central portion thereof, a semiconductor body (semiconductor member) 210 provided around the core layer 230, and a memory film (charge storage member) 220 provided around the semiconductor body 210. The semiconductor body 210 extends in the lamination direction (Z direction) within the laminate 20. The semiconductor body 210 is electrically connected to the semiconductor source layer BSL. The memory film 220 is provided between the semiconductor body 210 and the electrode film 21, and has a charge trapping portion. The plurality of pillars CL selected one by one from each finger are commonly connected to 1 bit line BL via the via hole 28 of fig. 1. Each column CL is provided in a region of the memory cell array 2m, for example.

As shown in fig. 4, the shape of the memory hole MH in the X-Y plane is, for example, a circle or an ellipse. Between the electrode film 21 and the insulating film 22, a barrier insulating film 21a constituting a part of the memory film 220 may be provided. The barrier insulating film 21a is, for example, a silicon oxide film or a metal oxide film. An example of the metal oxide is aluminum oxide. The barrier film 21b may be provided between the electrode film 21 and the insulating film 22, and between the electrode film 21 and the memory film 220. For example, in the case where the electrode film 21 is tungsten, the barrier film 21b is a laminated structure film of titanium nitride and titanium, for example. The blocking insulating film 21a suppresses reverse tunneling of charges from the electrode film 21 to the memory film 220 side. The barrier film 21b improves the adhesion between the electrode film 21 and the barrier insulating film 21a.

The semiconductor body 210 as a semiconductor component has a shape of, for example, a bottomed tubular shape. The semiconductor body 210 is, for example, polysilicon. The semiconductor body 210 is, for example, undoped silicon. In addition, the semiconductor body 210 may also be p-type silicon. The semiconductor body 210 serves as a channel for each of the drain side select transistor STD, the memory cell MC, and the source side select transistor STS. One end of the plurality of semiconductor bodies 210 in the same memory cell array 2m is commonly electrically connected to the semiconductor source layer BSL.

The portion of the memory film 220 other than the blocking insulating film 21a is disposed between the inner wall of the memory hole MH and the semiconductor body 210. The memory film 220 is, for example, cylindrical in shape. The plurality of memory cells MC have a memory region between the semiconductor body 210 and the electrode film 21 to be the word line WL, and are stacked in the Z direction. The memory film 220 includes, for example, a cover insulating film 221, a charge trapping film 222, and a tunnel insulating film 223. The semiconductor body 210, the charge trapping film 222, and the tunnel insulating film 223 extend in the Z direction, respectively.

The cover insulating film 221 is provided between the insulating film 22 and the charge trapping film 222. The cover insulating film 221 includes, for example, silicon oxide. When the sacrificial film (not shown) is replaced with the electrode film 21 (replacement step), the insulating film 221 is covered to protect the charge trapping film 222 from etching. The cover insulating film 221 may be removed from between the electrode film 21 and the memory film 220 in the replacement step. In this case, as shown in fig. 3 and 4, for example, the blocking insulating film 21a is not provided between the electrode film 21 and the charge trapping film 222. In addition, in the case where the electrode film 21 is formed without using a replacement step, the insulating film 221 does not need to be covered.

The charge trapping film 222 is provided between the blocking insulating film 21a and the cover insulating film 221 and the tunnel insulating film 223. The charge trapping film 222 includes, for example, silicon nitride, and has a trapping site therein for trapping charges. The portion of the charge trapping film 222 sandwiched between the electrode film 21 to be the word line WL and the semiconductor body 210 serves as a charge trapping portion to constitute a memory region of the memory cell MC. The threshold voltage of the memory cell MC varies depending on whether or not there is charge in the charge trapping part, or the amount of charge trapped in the charge trapping part. Thereby, the memory cell MC holds information.

A tunnel insulating film 223 is disposed between the semiconductor body 210 and the charge trapping film 222. The tunnel insulating film 223 contains, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 223 is a potential barrier between the semiconductor body 210 and the charge trapping film 222. For example, when electrons are injected from the semiconductor body 210 to the charge trapping region (writing operation) and when holes are injected from the semiconductor body 210 to the charge trapping region (erasing operation), the electrons and the holes pass through the potential barrier of the tunnel insulating film 223, respectively.

The core layer 230 fills the inner space of the cylindrical semiconductor body 210. The core layer 230 is, for example, columnar in shape. The core layer 230 is made of silicon oxide, for example, and has insulation properties.

Next, with reference to fig. 5 to 6B, the semiconductor source layer BSL, the insulating layer 60, and the metal layer 40 (source line 41, power lines 42, 43) will be described.

Fig. 5 shows a structure of the metal layer 40 when the semiconductor device 1 is viewed from the Z direction. Fig. 6A and 6B show schematic cross-sectional views on the line A-A of fig. 5. Hereinafter, the source line 41a and the source line 41b are collectively referred to as a source line 41, and the power line 42a and the power line 42b are collectively referred to as a power line 42. The source line 41, the power line 42, and the power line 43 are collectively referred to as a metal layer 40.

As shown in fig. 1, the semiconductor source layer BSL is disposed above the memory cell MC. As shown in fig. 6A and 6B, the semiconductor source layer BSL has a 1 st surface F1 on the memory cell MC side and a 2 nd surface F2 on the opposite side to the 1 st surface F1. The semiconductor source layer BSL is an example of the 1 st semiconductor layer, and includes doped polysilicon. The semiconductor source layer BSL is electrically connected to the memory cell MC, and supplies a cell source voltage for operating the memory cell MC.

The insulating layer 60 is disposed on the 2 nd surface F2 of the semiconductor source layer BSL. The insulating layer 60 is an example of the 1 st insulating layer, and silicon oxide is used, for example. As described below, the insulating layer 60 electrically separates the power supply line 42 from the semiconductor source layer BSL, but electrically connects the source line 41 and the semiconductor source layer BSL through a contact hole provided in the insulating layer 60.

The metal layer 40 is disposed on the 2 nd surface F2 of the semiconductor source layer BSL. In the present embodiment, the insulating layer 60 is provided between the metal layer 40 and the semiconductor source layer BSL. As shown in fig. 5, the metal layer 40 includes a source line 41, and power lines 42 and 43. The source line 41 and the power lines 42 and 43 are made of a metal having a lower resistance than the semiconductor source layer BSL, for example, aluminum. In fig. 5, 5 source lines 41 and 5 power lines 42 are shown, but the number of these lines is arbitrary.

Here, the source line 41 and the power supply lines 42 and 43 will be described in detail.

The source line 41 is disposed on the 2 nd surface F2 side of the semiconductor source layer BSL, and is electrically connected to the semiconductor source layer BSL. The source line 41 is an example of the 1 st metal wiring layer. As shown in fig. 6A, the source line 41 may be connected to the semiconductor source layer BSL via a contact CC3. As shown in fig. 6B, the source line 41 may be connected to the semiconductor source layer BSL through the entire bottom surface of the source line 41.

Fig. 6A and 6B are schematic cross-sectional views showing examples of connection structures between the source line 41 and the semiconductor source layer BSL. In fig. 6A, a contact CC3 is formed by filling a contact hole selectively formed in the insulating layer 60 with a low-resistance metal (aluminum or the like). On the other hand, in fig. 6B, the entire insulating layer 60 under the source line 41 is removed, and the entire bottom surface of the source line 41 is in contact with the semiconductor source layer BSL. Thus, the source line 41 in fig. 6B has a wider contact area with the semiconductor source layer BSL than the source line 41 in fig. 6A. Therefore, the contact resistance between the source line 41 and the semiconductor source layer BSL in fig. 6B is lower than the contact resistance between the source line 41 and the semiconductor source layer BSL in fig. 6A. The configuration of fig. 6B is preferable in consideration of the resistance of the source layers 41 and BSL as a whole. However, the configuration of fig. 6A may be adopted as long as the resistance of the entire source layers 41 and BSL can be sufficiently reduced even though the connection is made via the contact CC3.

Thus, the source line 41 and the semiconductor source layer BSL are electrically connected to each other, thereby integrally forming a source layer. Thus, the source line 41 and the semiconductor source layer BSL are collectively referred to as source layers 41 and BSL. As described above, since the source line 41 includes a metal having a lower resistance than the semiconductor source layer BSL, the resistance of the source layer 41 and BSL as a whole is lower than the semiconductor source layer BSL. That is, the source line 41 has an effect of reducing the resistances of the source layers 41 and BSL. By reducing the resistances of the source layers 41 and BSL, voltage drop of the cell source voltages in the source layers 41 and BSL can be suppressed. This situation results in a reduction in power consumption. The source line 41 is connected to the contact CC1, and is electrically connected to any one of the transistors 31 of the CMOS chip 3 via the contact CC 1. Thereby, the source line 41 applies a cell source voltage to the memory cell MC via the semiconductor source layer BSL. The cell source voltage is a voltage applied to the source layers 41 and BSL through the contact CC1, and becomes the source voltage of the memory cell MC.

The power line 42 is provided on the 2 nd surface F2 side of the semiconductor source layer BSL and electrically separated from the source layers 41 and BSL. The power supply line 42 is an example of the 2 nd metal wiring layer. As shown in fig. 5, 5 power lines 42 are commonly connected to the power line 43, and the power line 43 is further connected to the bonding pad 50. The bonding pad 50 is an example of the 1 st electrode. The power line 42 is provided with a contact CC2, and the bonding pad 50 is provided with a contact CC4. The contact CC2 and the contact CC4 are connected to any one of the transistors 31 of the CMOS chip 3.

In the present embodiment, the power supply line 42 is provided between the plurality of source lines 41 and is simultaneously present in the same layer on the semiconductor source layer BSL (insulating layer 60). More specifically, the source lines 41 and the power lines 42 extend in the Y direction, are electrically separated from each other, and are alternately (stripe-like) arranged in the X direction when viewed from the Z direction. The source line 41 and the power supply line 42 have rectangular shapes having a longitudinal direction in the Y direction. By simultaneously providing the source line 41 and the power line 42 in the same layer as in the present embodiment, the source line 41 and the power line 42 can be formed in a single layer without being multilayered.

The source lines 41 and the power lines 42 are preferably alternately and substantially equally arranged. For example, the source lines 41a, the power lines 42a, the source lines 41b, and the power lines 42b may be arranged at substantially equal intervals in the X direction in this order. In this case, the distance between the source line 41a and the source line 41b and the distance between the power line 42a and the power line 42b are arranged to be substantially the same in the X direction. By disposing the source lines 41 and the power lines 42 at substantially equal intervals alternately in this manner, for example, the source lines 41 and the power lines 42 can be prevented from being unevenly distributed in a partial region on the 2 nd surface F2 of the semiconductor source layer BSL. This allows the source line 41 and the power line 42 to be present in the same layer at the same time, and reduces the resistance of the source layer 41 and the BSL as a whole. The source line 41 and the power line 42 may have the same width in the X direction or may be different from each other.

Fig. 6C is a schematic cross-sectional view showing a cross section on line B-B of fig. 5 (a cross section of the source line 41 portion). The structure related to the source line 41 will be described with reference to fig. 6C.

The source line 41 is provided with a contact CC1 and a contact CC3. Contact CC1 is an example of the 1 st contact, and contact CC3 is an example of the 3 rd contact. The contact CC1 extends in the Z direction in the interlayer insulating film 25, and is electrically connected to the transistor 31a through the via hole 28, the wiring 24, and the wiring 34. The transistor 31a is an example of the 1 st logic circuit. The transistor 31a may be a circuit functioning as a cell source driver circuit. That is, the transistor 31a applies a source voltage to the source layers 41 and BSL via the via hole 28, the wirings 24 and 34, and the contact CC1, and further applies a source voltage to the memory cell MC from the source layers 41 and BSL.

The transistor 31b is electrically connected to a column CL (see fig. 1) in the memory cell MC, and applies a drain voltage to the column CL. In this way, the source voltage and the drain voltage are applied to the memory cell MC by the transistor 31a and the transistor 31b, and the cell current flows through the memory cell MC. This enables data to be read from or written to the memory cell MC.

Fig. 6D schematically shows a section on the C-C line of fig. 5 (a section of the power supply line 42 portion). The configuration of the power supply line 42 will be described with reference to fig. 6D.

The power line 42 is provided with a contact CC2, and the bonding pad 50 is provided with a contact CC4. Contact CC2 is an example of the 2 nd contact, and contact CC4 is an example of the 4 th contact. The contact CC2 extends in the Z direction in the interlayer insulating film 25, and is connected to the transistor 31c through the via hole 28, the wiring 24, and the wiring 34. The transistor 31c is an example of the 2 nd logic circuit. Similarly, the contact CC4 is connected to the transistor 31d. The transistor 31d is an example of the 3 rd logic circuit. Bond wire 52 is connected to bond pad 50, and bond wire 52 is in turn connected to an external power source (not shown). Thus, electric power for operating the semiconductor device 1 (the array chip 2 and the CMOS chip 3) is supplied from an external power source via the bonding pad 50. That is, external power from the bonding wire 52 is supplied to the transistor 31c via the power supply line 42 and the contact CC2, and is supplied to the transistor 31d via the contact CC4.

Next, the resistances at the respective positions (points T1 to T9) of the source layers 41 and BSL will be described in detail with reference to fig. 7 to 8.

Fig. 7 is a schematic plan view showing the source line 41, the power supply line 42, and the contact CC 1. Fig. 7 corresponds to region D of fig. 5.

In fig. 7, line segments E1 to E3 extending in the X direction are shown from the side near the contact point CC 1. The line segments E1 to E3 are virtual lines. The distances from the contact CC1 to the line segments E1 to E3 are set to be distances R1 to R3, respectively.

In addition, on the line segment E1 in the power supply line 42a, the point closest to the source line 41a is set as a point T1, the point closest to the source line 41b is set as a point T3, and the intermediate point between the point T1 and the point T3 is set as a point T2. That is, the point T2 is a point distant from the source line 41a than the point T1 and distant from the source line 41b than the point T3. In this case, the point T2 is on the line segment E1 within the power supply line 42a, and is farther than the points T1, T3 in terms of the distance from the source line (41 a or 41 b). Therefore, the resistances of the source layers 41 and BSL from the contact CC1 at the point T2 are highest among the points T1 to T3. Similarly, on the line segment E2 in the power supply line 42a, the point closest to the source line 41a is set as a point T4, the point closest to the source line 41b is set as a point T6, and the intermediate point between the point T4 and the point T6 is set as a point T5. That is, the point T5 is a point distant from the source line 41a than the point T4 and distant from the source line 41b than the point T6. In this case, the point T5 is on the line segment E2 within the power supply line 42a, and is farther than the points T4, T6 in terms of the distance from the source line (41 a or 41 b). Therefore, the resistances of the source layers 41 and BSL from the contact CC1 at the point T5 are highest among the points T4 to T6. Further, on the line segment E3 in the power supply line 42a, the point closest to the source line 41a is set as a point T7, the point closest to the source line 41b is set as a point T9, and the intermediate point between the point T7 and the point T9 is set as a point T8. That is, the point T8 is a point distant from the source line 41a than the point T7 and distant from the source line 41b than the point T9. In this case, the point T8 is on the line segment E3 within the power supply line 42a, and is farther than the points T7, T9 in terms of the distance from the source line (41 a or 41 b). Therefore, the resistances of the source layers 41 and BSL from the contact CC1 at the point T8 are highest among the points T7 to T9.

Fig. 8 is a graph showing the relationship between the resistances of the source layers 41 and BSL and the positions of the points T1 to T9. The horizontal axis of the graphs GE1 to GE3 indicates the positions of the points T1 to T9 on the line segments E1 to E3, and the vertical axis indicates the resistance values of the source layers 41 and BSL from the contact CC1 to the points T1 to T9.

Graph GE1 shows resistances of source layers 41 and BSL at points CC1 to T3 in fig. 7 (hereinafter, resistances of source layers 41 and BSL at points T1 to T3). The resistance component RR1 is a resistance component of the source layers 41 and BSL in the Y direction up to the position of the line segment E1 from the contact CC1 in fig. 7. The resistance component RL1 is a resistance component of the source layers 41 and BSL in the X direction from the position of the line segment E1 toward the points T1 to T3.

The distance in the Y direction from the contact CC1 to the position of the line segment E1 is the same for the points T1 to T3. Therefore, the resistance component RR1 is equal for the points T1 to T3.

In the X direction from the position of the line segment E1 toward the points T1 to T3, the source line 41 including the metal material does not exist between the end of the source line 41 and the points T1 to T3. The resistance of the semiconductor source layer BSL is higher than the resistance of the source line 41 including a metal material. Thus, in the segment E1, the resistance component RL1 is determined by the resistance of the semiconductor source layer BSL at the portion from the end of the source line 41a, 41b to the points T1 to T3. That is, the resistance component RL1 varies depending on the distances from the ends of the source lines 41a, 41b to the points T1 to T3 in the line segment E1. As a result, the resistances (rr1+rl1) of the points T1 to T3 change according to the resistance component RL 1. That is, the resistances of the source layers 41 and BSL at the points T1 to T3 vary according to the distance from the source lines 41a and 41b to the points T1 to T3 in the line segment E1.

Therefore, in the graph GE1, the resistance component RL1 at the point T1 near the source line 41a and the point T3 near the source line 41b is relatively small. Thus, the resistances (rr1+rl1) of the source layers 41, BSL at the points T1, T3 are close to the resistance component RR1, showing relatively low resistance values. On the other hand, the resistance component RL1 at the point T2 which is farther from the source line 41a than the point T1 and farther from the source line 41b than the point T3 is larger than the resistance components at the points T1, T3. Thus, the resistances (rr1+rl1) of the source layers 41 and BSL at the point T2 are higher than the resistances at the points T1 and T3. That is, the resistance at the point T2 is higher than the resistances at the points T1 and T3 by an amount corresponding to the substantial resistance component RL1 of the semiconductor source layer BSL of the distance L1 of fig. 7. In the Y direction, the distance R1 from the contact CC1 to the line segment E1 is equal to any one of the points T1 to T3. Therefore, the equal resistance component RR1 is commonly added to the points T1 to T3. Thus, the resistances (rr1+rl1) of the source layers 41 and BSL at the points T1 to T3 are curves that are close to the resistance component RR1 at the points T1 and T3 and have the maximum value (rr1+rl1) at the point T2.

The voltage drop in the cell source voltage occurs due to the resistance at points T1-T3. The greater the resistance, the greater the degree of voltage drop in the cell source voltage, and therefore the greater the voltage drop at point T2 than at points T1, T3. Therefore, the voltage drop of the cell source voltage at each of the points T1 to T3 shows the same tendency as the change in resistance shown in the graph GE 1.

Graph GE2 of fig. 8 shows resistances of source layers 41 and BSL from contact CC1 to points T4 to T6 of fig. 7 (hereinafter, resistances of source layers 41 and BSL at points T4 to T6). The resistance component RR2 is a resistance component of the source layers 41 and BSL in the Y direction from the contact CC1 to the position of the line segment E2 in fig. 7. The resistance component RL1 is a resistance component of the source layers 41 and BSL in the X direction from the position of the line segment E2 toward the points T4 to T6, and is equal to the resistance component RL1 of the line segment E1.

Like graph GE1, the resistance component RL1 at the point T4 near the source line 41a and the point T6 near the source line 41b is relatively small in the graph GE 2. Thus, the resistances (rr2+rl1) of the source layers 41, BSL at the points T4, T6 are close to the resistance component RR2, showing relatively low resistance values. On the other hand, the resistance component RL1 at the point T5 which is farther from the source line 41a than the point T4 and farther from the source line 41b than the point T6 is larger than the resistance components at the points T4, T6. Thus, the resistances (rr2+rl1) of the source layers 41 and BSL at the points T5 are higher than the resistances of the source layers 41 and BSL at the points T4 and T6. That is, the resistance at the point T5 is higher than the resistances at the points T4 and T6 by an amount corresponding to the resistance component RL1 of the semiconductor source layer BSL of the distance L1 of fig. 7. In the Y direction, the distance R2 from the contact CC1 to the line E2 is equal to any one of the points T4 to T6. Therefore, the equal resistance component RR2 is commonly added to the points T4 to T6. Thus, the resistances (rr2+rl1) of the source layers 41 and BSL are curves that approach RR2 at points T4 and T6 and have a maximum value at point T5.

Line segment E2 is farther from contact CC1 than line segment E1. Thus, the resistance component RR2 is higher than the resistance component RR1 by an amount corresponding to the resistance dRR2 of the source line 41 corresponding to the distance difference from the contact CC1 to the line segments E1 and E2. That is, the resistance component RR2 becomes the resistance component rr1+ dRR2.

The voltage drop of the cell source voltage at each of the points T4 to T6 shows the same tendency as the change in resistance shown in the graph GE 2.

Next, graph GE3 of fig. 8 shows resistances of source layers 41 and BSL from contact CC1 to points T7 to T9 of fig. 7 (hereinafter, resistances of source layers 41 and BSL at points T7 to T9). The resistance component RR3 is a resistance component of the source layers 41 and BSL from the contact CC1 to the line segment E3 in fig. 7. The resistance component RL1 is a resistance component of the source layers 41 and BSL in the X direction from the position of the line segment E3 toward the points T7 to T9, and is equal to the resistance component RL1 of the relevant line segment E1 and E2.

Like graphs GE1 and GE2, the graph GE3 of fig. 8 has a relatively small resistance component RL1 at a point T7 near the source line 41a and a point T9 near the source line 41 b. Thus, the resistances (rr3+rl1) of the source layers 41, BSL at the points T7, T9 are close to the resistance component RR3, showing relatively low resistance values. On the other hand, the resistance component RL1 at the point T8 which is farther from the source line 41a than the point T7 and farther from the source line 41b than the point T9 is larger than the resistance components at the points T7, T9. Thus, the resistances (rr3+rl1) of the source layers 41 and BSL at the point T8 are higher than the resistances at the points T7 and T9. That is, the resistance at the point T8 is higher than the resistances at the points T7 and T9 by an amount corresponding to the resistance component RL1 of the semiconductor source layer BSL of the distance L1 of fig. 7. In the Y direction, the distances R3 from the contact point CC1 to the line segment E3 are equal at any of the points T7 to T9. Therefore, the resistance component RR3 is equal and commonly added to the points T7 to T9. Thus, the resistances (rr3+rl1) of the source layers 41 and BSL are curves, for example, close to RR3 at points T7 and T9 and have a maximum value at point T8.

Line segment E3 is farther from contact CC1 than line segment E1. Thus, the resistance component RR3 is higher than the resistance component RR1 by an amount corresponding to the resistance dRR3 of the source line 41 corresponding to the distance difference from the contact CC1 to the line segments E1 and E3. That is, the resistance component RR3 becomes the resistance component rr1+ dRR3.

The voltage drop of the cell source voltage at each of the points T7 to T9 shows the same tendency as the change in resistance shown in the graph GE 3.

In the present embodiment, the source line 41 and the power supply line 42 are formed by processing the same metal layer. Thus, not only the metal layer provided on the semiconductor source layer BSL can be used for the source line 41, but also the power line 42.

However, the source line 41 is not provided entirely above the semiconductor source layer BSL, but is provided locally. In this case, the resistances of the source layers 41 and BSL are higher than those of the case where the source line 41 is provided over the entire semiconductor source layer BSL. This results in a voltage drop in the cell source voltage.

In contrast, in the present embodiment, the source lines 41 and the power lines 42 are alternately provided on the semiconductor source layer BSL. Thus, the source lines 41 can be arranged substantially uniformly and connected to the semiconductor source layer BSL. Therefore, the resistances of the source layers 41 and BSL in the present embodiment do not rise as much as in the case where the source line 41 is provided over the entire semiconductor source layer BSL.

In addition, the source line 41 and the power line 42 are formed of the same metal layer, and it is not necessary to laminate the metal layer of the source line 41 and the metal layer of the power line 42 by other steps. Therefore, the manufacturing steps of the semiconductor device can be shortened. In addition, since the source layer 41 and the power supply line 42 do not need to be stacked, the number of stacked wirings can be reduced.

In addition, the source layer 41 is not provided at the portion where the power supply line 42 is provided. Therefore, the resistances of the source layers 41 and BSL from the contact CC1 to the points T2, T5, and T8 in the middle of the power supply line 42 become high.

In contrast, in the present embodiment, the source lines 41 and the power lines 42 are alternately arranged on the semiconductor source layer BSL, whereby the width of each power line 42 (the interval between adjacent source lines 41) is narrowed. This can suppress an increase in resistance of the source layers 41 and BSL from the contact CC1 to the points T2, T5, and T8. If the width of the power supply lines 42 is narrowed and the number of the power supply lines 42 is increased, the increase in the resistance of the source layers 41 and BSL from the contact CC1 to the points T2, T5, and T8 can be further suppressed.

(embodiment 2) fig. 9 is a schematic plan view showing a source line 41, a power supply line 42, and a contact CC1 of the semiconductor device 1 of embodiment 2. Embodiment 2 is different from embodiment 1 in the planar shape of the metal layer 40 (source line 41 and power line 42), and the other structures are the same.

In embodiment 2, regarding the planar shape of the source line 41a, the sides S1 and S2 of the source line 41a are inclined with respect to the Y direction so that the width of the source line 41a in the X direction becomes wider as it goes away from the contact CC 1. On the other hand, regarding the planar shape of the power supply line 42b, the sides S3 and S4 of the power supply line 42b are inclined with respect to the Y direction so that the width of the power supply line 42b in the X direction becomes narrower as it goes away from the contact CC 1. Thus, the width of the power supply line 42b in the X direction becomes narrower in the order of the width H1, the width H2, and the width H3 as it is farther from the contact CC 2. Further, the other source line 41b and the like have the same planar shape as the source line 41 a. The other power supply lines 42a, 42c, and the like have the same planar shape as the power supply line 42 b.

Thus, the source lines 41 and the power supply lines 42 have complementary planar shapes, and are arranged so as to be staggered in the X direction without contact.

As the contact CC1 is separated in the Y direction, the resistance from the contact CC1 increases, and the voltage drop increases. Therefore, the resistance component RR2 from the contact CC1 to the line segment E2 is higher than the resistance component RR1 from the contact CC1 to the line segment E1. The resistance component RR3 from the contact CC1 to the line segment E3 is higher than the resistance component RR2 from the contact CC1 to the line segment E2. On the other hand, the width of the source line 41 in the X direction increases as it moves away from the contact CC 1. Thus, the resistance component RH1 of the source layers 41 and BSL from the source lines 41a and 41b to the point T2 in the line segment E1 is higher than the resistance component RH2 of the source layers 41 and BSL from the source lines 41a and 41b to the point T5 in the line segment E2. The resistance component RH2 of the semiconductor source layer BSL from the source lines 41a and 41b to the point T5 in the line segment E2 is higher than the resistance component RH3 of the semiconductor source layer BSL from the source lines 41a and 41b to the point T8 in the line segment E3. Thus, the variation in the resistances (rr1+rh1, rr2+rh2, rr3+rh3) of the source layers 41 and BSL from the contact CC1 to the points T1 to T9 is suppressed.

Fig. 10 is a graph showing the relationship between the resistances of the source layers 41 and BSL and the positions of the points T1 to T9. The horizontal axis of the graphs GE1 to GE3 indicates the positions of the points T1 to T9 on the line segments E1 to E3, and the vertical axis indicates the resistance values of the source layers 41 and BSL.

The graph GE1 of fig. 10 shows the change in resistance of the source layers 41 and BSL on the line segment E1 (points T1 to T3).

As in embodiment 1, the resistance component RH1 at the point T1 near the source line 41a and the point T3 near the source line 41b is relatively small. Thus, the resistances (rr1+rh1) of the source layers 41 and BSL at the points T1 and T3 approach the resistance component RR1, and exhibit relatively low resistance values. On the other hand, the resistance component RH1 at the point T2 which is farther from the source line 41a than the point T1 and farther from the source line 41b than the point T3 is larger than the resistance components at the points T1, T3. Thus, the resistances (rr1+rh1) of the source layers 41 and BSL at the point T2 are higher than the resistances at the points T1 and T3. Thus, the graph GE1 has the same tendency as GE1 of fig. 8, and the resistances (rr1+rh1) of the source layers 41 and BSL are curves such that the resistances approach the resistance component RR1 at the points T1 and T3 and have the maximum value (rr1+rh1) at the point T2. The resistance component RR1 is the same as the resistance component RR1 of embodiment 1.

Graph GE2 shows resistances of source layers 41 and BSL from contact CC1 to points T4 to T6 in fig. 9.

Here, as shown in fig. 9, the width H2 from the end of the source line 41a or 41b to the point T5 in the line segment E2 is narrower than the width H1 from the end of the source line 41a or 41b to the point T2 in the line segment E1. Therefore, the resistance component RH2 of the source layers 41 and BSL from the end of the source line 41a or 41b to the point T5 in the line segment E2 is smaller than the resistance component RH1 of the source layers 41 and BSL from the end of the source line 41a or 41b to the point T2 in the line segment E1. That is, the maximum value of the resistance component RH2 of the source layer 41, BSL at the point T5 is smaller than the maximum value of the resistance component RH1 at the point T2 by an amount corresponding to the difference between the width H2 and the width H1 of the resistance component dRH. Thus, the resistances (rr2+rh2) of the source layers 41 and BSL at the point T5 are higher than the resistances at the points T4 and T6, but are not much changed from the resistances (rr1+rh1) at the point T2. Note that, the resistance component RR2 is the same as the resistance component RR2 of embodiment 1, and is the resistance component rr1+ dRR2.

Graph GE3 shows resistances of source layers 41 and BSL from contact CC1 to points T7 to T9 in fig. 9.

Here, as shown in fig. 9, the width H3 from the end of the source line 41a or 41b to the point T8 in the line segment E3 is narrower than the widths H1, H2. Therefore, the resistance components RH3 of the source layers 41 and BSL from the end of the source line 41a or 41b to the point T8 in the line segment E3 are smaller than the resistance components RH1 and RH2. For example, the maximum value of the resistance component RH3 of the source layer 41 and BSL at the point T8 is smaller than the maximum value of the resistance component RH1 at the point T1 by an amount corresponding to the difference between the width H3 and the width H1 of the resistance component dRH. Thus, the maximum value of the resistance (rr3+rh3) of the source layer 41 and BSL at the point T8 is higher than the resistance at the points T7 and T9, but is not much changed from the maximum value of the resistance (rr1+rh1 or rr2+rh2) at the points T1 and T2. Note that, the resistance component RR3 is the same as the resistance component RR3 of embodiment 1, and is the resistance component rr1+ dRR3.

Thus, according to embodiment 2, the width of the source line 41 is narrower near the contact CC1 (cell source driver), and becomes wider as it gets farther from the contact CC1. Thus, although the distances between the points T2, T5, and T8 and the contact CC1 in the Y direction are different from each other, the resistances of the source layers 41 and BSL from the contact CC1 to the points T2, T5, and T8 may not be changed much or may be substantially equal. This can suppress voltage unevenness at any position of the source layers 41 and BSL.

Other configurations of embodiment 2 may be the same as those of embodiment 1. Therefore, embodiment 2 can also obtain the effects of embodiment 1.

(embodiment 3) fig. 11 is a schematic plan view showing a source line 41, a power supply line 42, and a contact CC1 of the semiconductor device 1 of embodiment 3. Embodiment 3 is different from embodiment 1 in the planar shape of the metal layer 40 (source line 41 and power line 42). In addition, embodiment 3 is different from embodiment 1 in that a contact CC1 is provided at both ends of the source line 41.

In embodiment 3, the source line 41a is connected to the contact CC1 (cell source driver) at both ends in the Y direction. In addition, regarding the planar shape of the source line 41a, the width of the source line 41a in the X direction becomes wider from both end portions in the Y direction toward the central portion. Therefore, the width of the source line 41a in the X direction is widest at the central portion in the longitudinal direction (Y direction). Further, the widths of the source line 41a in the X direction in the line segment E1 and the line segment E3 may be the same. The source line 41a and the source line 41b have the same planar shape.

On the other hand, the width of the power supply line 42b in the X direction becomes narrower from both ends (the contact CC1 or the power supply line 43) of the power supply line 42b in the Y direction toward the center. Therefore, the width of the power supply line 42b in the X direction is narrowest at the central portion in the longitudinal direction (Y direction). For example, the width H2 of the central portion of the power supply line 42b is narrower than the widths H1 and H3 of the both end portions thereof. Further, the widths of the power supply lines 42b in the X direction in the line segments E1 and E3 may be the same. The power supply lines 42a to 42c have the same planar shape. The power supply lines 42a and 42c have the same planar shape as the power supply line 42 b. Thus, the source lines 41 and the power supply lines 42 have complementary planar shapes, and are arranged so as to be staggered in the X direction without contact.

Regarding the planar shape of the source line 41a, the sides S1 and S5 of the source line 41a are inclined with respect to the Y direction so that the width of the source line 41a in the X direction becomes wider as going away from the contact CC1 toward the Y direction and is widest at the central portion. Regarding the planar shape of the power supply line 42b, the sides S2 and S6 of the power supply line 42b are inclined with respect to the Y direction so that the widths H1 and H3 are the widest and the width H2 is the narrowest among the widths of the power supply line 42b in the X direction.

As the contact CC1 located at both ends of the source lines 41a and 41b in the Y direction is separated, the resistance from the contact CC1 increases, and the voltage drop increases. Therefore, the resistance component RR2 of the source lines 41a and 41b from the contact CC1 to the line segment E2 is higher than the resistance component RR1 from the contact CC1 to the line segments E1 and E3. On the other hand, the width of the source lines 41a and 41b in the X direction increases as the distance from the contact CC1 at both ends increases. Thus, the resistance components RH1 and RH3 of the semiconductor source layer BSL from the source lines 41a and 41b to the points T2 and T8 in the line segments E1 and E3 are higher than the resistance component RH2 from the source lines 41a and 41b to the point T5 in the line segment E2.

The source lines 41a and 41b have a contact CC1 at both ends in the longitudinal direction. Therefore, the intermediate portions of the source lines 41a and 41b in the longitudinal direction are farthest from the contact CC1, and the resistances of the source layers 41 and BSL are maximized at the intermediate portions. Thus, in embodiment 3, the line segment E2 at the center of the source lines 41a and 41b reduces the resistance (rr2+rh2) from the contact CC1 to the source layers 41 and BSL, thereby suppressing the uneven resistance of the source layers 41 and BSL from the contact CC1 to the points T1 to T9.

Fig. 12 is a graph showing the relationship between the resistances of the source layers 41 and BSL and the positions of the points T1 to T9. The horizontal axis of the graphs GE1 to GE3 indicates the positions of the points T1 to T9 on the line segments E1 to E3, and the vertical axis indicates the resistance values of the source layers 41 and BSL.

Graph GE1 shows a change in resistance of source layers 41 and BSL in line segment E1 (points T1 to T3). The resistances of the source layers 41 and BSL in the line segment E1 of embodiment 3 are the same as those of the source layers 41 and BSL in the line segment E1 of embodiment 2 (the graph GE1 of fig. 10), and therefore, detailed description thereof is omitted.

Graph GE2 shows the change in resistance of source layers 41 and BSL in line segment E2 (points T4 to T6). The change in the resistances of the source layers 41 and BSL in the line segment E2 of embodiment 3 is substantially the same as the change in the resistances of the source layers 41 and BSL in the line segment E2 of embodiment 2 (the graph GE2 of fig. 10). However, in embodiment 3, since the contact CC1 is provided at both end portions of the source line 41a, the resistance or voltage drop of the source layer 41 and BSL from the contact CC1 to the points T4 to T6 can be made smaller than the resistance or voltage drop of the source layer 41 and BSL at the points T4 to T6 of embodiment 2.

Graph GE3 shows the resistances of source layers 41 and BSL from contact CC1 to points T7 to T9 in fig. 11. In embodiment 3, a contact CC1 is provided at both ends of the source lines 41a and 41 b. The distance from the contact CC1 at the upper end of the source line 41a, 41b to the line segment E1 is equal to the distance from the contact CC1 at the lower end of the source line 41a, 41b to the line segment E3, and is the distance R1. In addition, the width H1 is substantially the same as the width H3. Therefore, the distances from the source lines 41a and 41b to the points T1 to T3 are substantially equal to the distances from the source lines 41a and 41b to the points T7 to T9, respectively. Thus, the resistances (rr1+rl3) of the source layers 41 and BSL from the contact CC1 to the points T7 to T9 are substantially equal to the resistances (rr1+rl1) of the source layers 41 and BSL from the contact CC1 to the points T1 to T3. Thus, graphs GE1 and GE3 of FIG. 12 show the same trend.

As described above, according to embodiment 3, the contact CC1 is provided at both ends of the source line 41. Thus, the source line 41 is connected to the cell source driver at both ends thereof, and the voltage drop of the cell source voltage in the source layer 41 and the BSL can be reduced. The widths H1 and H3 of the two ends of the source line 41 are substantially the same as each other. Thus, the resistances (rr1+rh1) of the source layers 41 and BSL from the contact CC1 to the points T1 to T3 at one end of the power line 42 are substantially equal to the resistances (rr1+rh3) of the source layers 41 and BSL from the contact CC1 to the points T7 to T9 at the other end of the power line 42.

The width of the source line 41 is narrower near the contact CC1 located at both ends in the longitudinal direction thereof, and gradually becomes wider as it gets farther from the contact CC1 and gets closer to the center portion. Thus, the resistance component RH2 of the center portion of the source line 41 is lower than the resistance components RH1 and RH3 of the both end portions of the source line 41. Thus, although the distance between the point T5 and the contact CC1 in the Y direction is different from the points T2 and T8, the resistances of the source layers 41 and BSL from the contact CC1 to the point T5 may not be substantially changed or may be substantially equal to the resistances of the source layers 41 and BSL from the contact CC1 to the points T2 and T8. This can suppress voltage unevenness at any position of the source layers 41 and BSL.

Other configurations of embodiment 3 may be the same as those of embodiment 1. Therefore, embodiment 3 can also obtain the effects of embodiment 1.

Fig. 13 is a block diagram showing a configuration example of a semiconductor device to which any of the above-described embodiments is applied. The semiconductor device 1 is, for example, a semiconductor memory device 100a such as a NAND flash memory capable of nonvolatile storage of data, and is controlled by an external memory controller 1002. The communication between the semiconductor memory apparatus 100a and the memory controller 1002 supports, for example, a NAND interface standard.

As shown in fig. 13, the semiconductor memory device 100a includes, for example, a memory cell array MCA, an instruction register 1011, an address register 1012, a sequencer 1013, a driver module 1014, a row decoder module 1015, and a sense amplifier module 1016.

The memory cell array MCA includes a plurality of blocks BLK (0) to BLK (n) (n is an integer of 1 or more). The block BLK is a set of a plurality of memory cells capable of nonvolatile storage of data, and is used as an erase unit of data, for example. In addition, a plurality of bit lines and a plurality of word lines are provided in the memory cell array MCA. Each memory cell is associated with, for example, 1 bit line and 1 word line. The detailed configuration of the memory cell array MCA will be described below.

The command register 1011 holds a command CMD received by the semiconductor memory apparatus 100a from the memory controller 1002. The command CMD includes, for example, a command for causing the sequencer 1013 to execute a read operation, a write operation, an erase operation, or the like.

The address register 1012 holds address information ADD received from the memory controller 1002 by the semiconductor memory device 100 a. The address information ADD includes, for example, a block address BA, a page address PA, and a column address CA. For example, a block address BA, a page address PA, and a column address CA are used for selection of the block BLK, the word line, and the bit line, respectively.

The sequencer 1013 controls operations of the entire semiconductor memory apparatus 100 a. For example, the sequencer 1013 controls the driver module 1014, the row decoder module 1015, the sense amplifier module 1016, and the like based on the command CMD stored in the command register 1011, so that they perform a read operation, a write operation, an erase operation, and the like.

The driver module 1014 generates voltages to be used in read operations, write operations, erase operations, and the like. The driver module 1014 applies the generated voltage to the signal line corresponding to the selected word line, for example, based on the page address PA stored in the address register 1012.

The row decoder module 1015 is provided with a plurality of row decoders. The row decoder selects 1 block BLK in the corresponding memory cell array MCA based on the block address BA stored in the address register 1012. The row decoder transfers, for example, a voltage applied to a signal line corresponding to the selected word line in the selection block BLK.

The sense amplifier module 1016 applies a desired voltage to each bit line in accordance with write data DAT received from the memory controller 1002 during a write operation. In addition, the sense amplifier module 1016 determines data stored in the memory cell based on the voltage of the bit line in the read operation, and transmits the determination result to the memory controller 1002 as read data DAT.

The semiconductor memory device 100a and the memory controller 1002 described above may be combined to form 1 semiconductor device. Examples of such a semiconductor device include a memory card such as an sd card, an SSD (solid state drive ), and the like.

Fig. 14 is a circuit diagram showing an example of the circuit configuration of the memory cell array MCA. 1 block BLK among a plurality of blocks BLK included in the memory cell array MCA is extracted. As shown in fig. 14, the block BLK includes a plurality of string components SU (0) to SU (k) (k is an integer of 1 or more).

Each string component SU includes a plurality of NAND strings NS respectively associated with bit lines BL (0) to BL (m) (m is an integer of 1 or more). Each NAND string NS includes, for example, memory cell transistors MT (0) to MT (15), and select transistors ST (1) and ST (2). The memory cell transistor MT includes a control gate and a charge storage layer, and holds data nonvolatile. The selection transistors ST (1) and ST (2) are used for selecting the string component SU at various operations.

In each NAND string NS, memory cell transistors MT (0) to MT (15) are connected in series. The drain of the selection transistor ST (1) is connected to the bit line BL with which the association is established, and the source of the selection transistor ST (1) is connected to one end of the memory cell transistors MT (0) to MT (15) connected in series. The drain of the selection transistor ST (2) is connected to the other ends of the memory cell transistors MT (0) to MT (15) connected in series. The source of the selection transistor ST (2) is connected to the source line SL.

In the same block BLK, control gates of the memory cell transistors MT (0) to MT (15) are commonly connected to word lines WL (0) to WL (7), respectively. The gates of the select transistors ST (1) in the string components SU (0) to SU (k) are commonly connected to select gate lines SGD (0) to SGD (k), respectively. The gate of the selection transistor ST (2) is commonly connected to the selection gate line SGS.

In the circuit configuration of the memory cell array MCA described above, the bit line BL is common to the NAND strings NS assigned the same column address among the string components SU. The source line SL is shared among a plurality of blocks BLK, for example.

A set of a plurality of memory cell transistors MT connected to a common word line WL within 1 string component SU is referred to as a cell component CU, for example. For example, the storage capacity of the cell unit CU including the storage cell transistors MT each storing 1 bit of data is defined as "1 page of data". The cell unit CU may have a storage capacity of 2 pages or more of data according to the number of bits of data stored by the memory cell transistor MT.

The memory cell array MCA included in the semiconductor memory device 100a according to the present embodiment is not limited to the circuit configuration described above. For example, the number of memory cell transistors MT and selection transistors ST (1) and ST (2) included in each NAND string NS may be arbitrarily designed. The number of string elements SU included in each block BLK may be any number.

(variation) fig. 15 is a cross-sectional view showing another configuration example of the semiconductor memory device 100 a. The semiconductor memory device 100a includes a memory chip CH2 having a memory cell array, and a controller chip CH1 having a CMOS circuit. The memory chip CH2 and the controller chip CH1 are bonded to the bonding surface B1, and are electrically connected to each other via the wirings 24 and 34 bonded to the bonding surface. Fig. 15 shows a state in which the memory chip CH2 is mounted on the controller chip CH1.

The configuration of the memory cell array MCA of the memory chip CH2 and the configuration of the CMOS circuit may be the same as those in the above embodiment.

In the present embodiment, the memory chip CH2 and the controller chip CH1 are formed separately and bonded to the bonding surface B1.

In the controller chip CH1, a via hole 32 and wirings 33, 34 are provided above the transistor Tr. The wirings 33 and 34 constitute a multilayer wiring structure in the interlayer insulating film 35. The wiring 34 is embedded in the interlayer insulating film 35 and exposed substantially on the same plane as the surface of the interlayer insulating film 35. The wirings 33, 34 are electrically connected to the transistor Tr and the like. The through holes 32 and the wirings 33 and 34 are made of low-resistance metal such as copper or tungsten. The interlayer insulating film 35 covers and protects the transistor Tr, the via hole 32, and the wirings 33, 34. As the interlayer insulating film 35, for example, an insulating film such as a silicon oxide film is used.

In the memory chip CH2, a via hole 28 and wirings 23 and 24 are provided below the memory cell array MCA. The wirings 23 and 24 constitute a multilayer wiring structure in the interlayer insulating film 25. The wiring 24 is embedded in the interlayer insulating film 25 and exposed substantially on the same plane as the surface of the interlayer insulating film 25. The wirings 23 and 24 are electrically connected to the semiconductor body 210 of the columnar portion CL. The through holes 28 and the wirings 23 and 24 are made of low-resistance metal such as copper or tungsten. The interlayer insulating film 25 covers and protects the laminate 20, the via hole 28, and the wirings 23 and 24. As the interlayer insulating film 25, for example, an insulating film such as a silicon oxide film is used.

The interlayer insulating film 25 and the interlayer insulating film 35 are bonded to each other on the bonding surface B1, and the wiring 24 and the wiring 34 are also bonded to each other on the bonding surface B1 substantially on the same plane. Thus, the memory chip CH2 and the controller chip CH1 are electrically connected via the wirings 24 and 34.

As described above, the present embodiment can also be applied to a semiconductor device in which the memory chip CH2 and the controller chip CH1 are bonded.

(embodiment 4) fig. 16 is a plan view showing a configuration example of the semiconductor device 1 according to embodiment 4. Fig. 16 shows the plane of the entire memory chip CH 2. Fig. 17 and 18 are cross-sectional views showing configuration examples of the semiconductor device 1 according to embodiment 4. Fig. 17 shows a section along line 17-17 of fig. 16, and fig. 18 shows a section along line 18-18 of fig. 16. Fig. 19 is a perspective view showing an example of the structure of semiconductor device 1 according to embodiment 4.

In embodiment 4, the slit ST (LI) is constituted by the source wiring LI. As shown in fig. 16, the source line LI extends in a direction (for example, a substantially orthogonal direction, an X direction) intersecting the source line 41 and the power lines 42 and 43 when viewed from the Z direction. The source wiring LI is divided into 4 parts in the X direction, corresponding to 4 memory surfaces of the memory cell array MCA. Acc4 is a region where contact CC4 is provided. Acc12 is a region where contacts CC1 and CC2 are provided. An edge seal ES is provided on the outer edge of the memory chip CH2 to suppress cracking or peeling from the outside.

As shown in fig. 17, the source wiring LI has a structure in which an insulating film such as a silicon oxide film is coated on the inner wall of the slit, and a conductive material is buried inside the insulating film. One end of the source wiring LI is connected to the semiconductor source layer BSL, and the other end is connected to other wirings. Thus, the source line LI can supply a source voltage to the source line 41 through the semiconductor source layer BSL.

In the present embodiment, as shown in fig. 18, the source lines 41 and the power supply lines 42 are alternately arranged in the X direction on the 2 nd plane F2 side. The source line 41 and the power line 42 extend substantially parallel to each other in the Y direction as shown in fig. 16 and 17, respectively. The source line 41 is electrically connected to the semiconductor source layer BSL through a contact CC 3.

Here, the source line LI extends in a direction intersecting the source line 41 and the power line 42 (for example, a substantially orthogonal direction) in a plan view as viewed from the Z direction. That is, the source wiring LI extends in the arrangement direction (X direction) of the source lines 41 and the power supply lines 42 in a plan view as viewed from the Z direction. The source lines LI are alternately arranged in the extending direction (Y direction) of the source lines 41 and the power lines 42 in a plan view as seen from the Z direction.

As shown in fig. 17, the power supply line 42 is not provided beside the source line 41 in the extending direction (Y direction) of the source line 41, and therefore, the interval between the adjacent contacts CC3 can be narrowed. By narrowing the interval between the adjacent contacts CC3, the contact resistance between the source line 41 and the semiconductor source layer BSL can be reduced. Thus, the resistance of the semiconductor source layer BSL can be reduced by adjusting the interval between the adjacent contacts CC 3.

On the other hand, as shown in fig. 18 and 19, the power lines 42 are not provided adjacently on both sides of the source lines 41 in the arrangement direction (X direction) of the source lines 41 and the power lines 42, and thus there is a limit in narrowing the interval between the adjacent source lines 41. Thus, it is difficult to reduce the contact resistance between the source line 41 and the semiconductor source layer BSL by adjusting the interval between adjacent source lines 41 or the interval between the contacts CC3 in the X direction.

Therefore, in embodiment 4, the source line LI extends in a direction intersecting the source line 41 and the power line 42 (for example, in a substantially orthogonal direction) in a plan view as viewed from the Z direction. As a result, as shown in fig. 18, the source wiring LI is in contact with the entire bottom surface of the semiconductor source layer BSL in the X direction. The contacts CC3 adjacent to each other in the X direction are electrically connected not only through the semiconductor source layer BSL but also through the source wiring LI thereunder. Thereby, the resistance of the contact CC3 adjacent in the X direction is reduced. That is, according to embodiment 4, the resistance of the semiconductor source layer BSL is reduced by narrowing the interval between the contacts CC3 in the Y direction, and the resistance of the semiconductor source layer BSL is reduced by the source wiring LI in the X direction. This can reduce the resistance of the semiconductor source layer BSL to the same extent as in the case where the source line 41 is provided on the entire semiconductor source layer BSL. This can suppress the source voltage from changing to an unexpected potential.

Several embodiments of the present utility model have been described, but these embodiments are presented as examples and are not intended to limit the scope of the utility model. These embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the utility model. These embodiments and variations thereof are included in the scope and gist of the utility model, and are also included in the utility model described in the claims and the scope equivalent thereto.

Claims

1. A semiconductor device is characterized by comprising: a plurality of transistors; a memory cell array disposed above the plurality of transistors; a 1 st semiconductor layer provided above the memory cell array, the 1 st semiconductor layer having a 1 st surface on the memory cell array side and a 2 nd surface on the opposite side to the 1 st surface; a 1 st metal wiring provided above the 2 nd surface and electrically connected to the 1 st semiconductor layer; a 2 nd metal wiring which is provided in the same layer as the 1 st metal wiring above the 2 nd surface and is not in contact with the 1 st metal wiring and the 1 st semiconductor layer; a 1 st contact provided below the 1 st metal wiring and extending in a 1 st direction from the 1 st surface toward the 2 nd surface, the 1 st contact electrically connecting one of the plurality of transistors to the 1 st metal wiring; and a 2 nd contact provided below the 2 nd metal wiring, extending in the 1 st direction, and electrically connecting the other of the plurality of transistors to the 2 nd metal wiring.

2. The semiconductor device according to claim 1, further comprising a 1 st insulating layer provided over the 1 st semiconductor layer, wherein the plurality of 2 nd metal wirings are provided over the 1 st insulating layer and electrically separated from the 1 st semiconductor layer by the 1 st insulating layer.

3. The semiconductor device according to claim 1, further comprising a 1 st insulating layer provided over the 1 st semiconductor layer, wherein the plurality of 1 st metal wirings are provided over the 1 st insulating layer and electrically connected to the 1 st semiconductor layer via a plurality of 3 rd contacts provided over the 1 st insulating layer.

4. The semiconductor device according to any one of claims 1 to 3, wherein the plurality of 1 st metal wirings and the plurality of 2 nd metal wirings extend in a 2 nd direction parallel to the 2 nd surface.

5. The semiconductor device according to claim 4, wherein the 1 st metal wiring and the 2 nd metal wiring are alternately arranged in a 3 rd direction substantially orthogonal to the 1 st direction and the 2 nd direction in a plan view as viewed from the 1 st direction.

6. The semiconductor device according to claim 5, further comprising a 1 st electrode, wherein the 1 st electrode is provided above the 2 nd surface and is electrically separated from the 1 st semiconductor layer, and wherein the plurality of 2 nd metal wirings are electrically connected to the 1 st electrode.

7. The semiconductor device according to claim 6, further comprising a 4 th contact which is provided so as to extend in the 1 st direction and is connected between the 1 st electrode and a 3 rd transistor among the plurality of transistors.

8. The semiconductor device according to claim 7, wherein the plurality of 1 st metal wirings each have a rectangular shape having a longitudinal direction in the 2 nd direction in a plan view seen from the 1 st direction, and the 2 nd metal wirings extend between the plurality of 1 st metal wirings to electrically connect the 2 nd contact and the 4 th contact.

9. The semiconductor device according to claim 8, wherein sides of the plurality of 1 st metal wires facing the 2 nd metal wires are inclined with respect to the 2 nd direction in a plan view as seen from the 1 st direction, and sides of the 2 nd metal wires facing the 1 st metal wires are inclined with respect to the 2 nd direction.

10. The semiconductor device according to claim 1, further comprising a wiring which penetrates the memory cell array and is connected to the 1 st semiconductor layer in a state of being electrically separated from the memory cell array, wherein the wiring extends in a direction intersecting the 1 st and 2 nd metal wirings in a plan view as viewed from the 1 st direction.

11. The semiconductor device according to claim 10, wherein the wiring is substantially orthogonal to the 1 st and 2 nd metal wirings in a plan view as viewed from the 1 st direction.

12. The semiconductor device according to claim 10, wherein the wiring includes an insulating film provided on an inner wall of a slit penetrating the memory cell array to reach the 1 st semiconductor layer, and a conductive material filling an inner side of the insulating film.