CN219577050U

CN219577050U - LDPC check node calculating device based on full-correlation semi-probability calculation

Info

Publication number: CN219577050U
Application number: CN202320899685.2U
Authority: CN
Inventors: 刘齐
Original assignee: Sichuan Innogence Technology Co Ltd
Current assignee: Sichuan Innogence Technology Co Ltd
Priority date: 2023-04-20
Filing date: 2023-04-20
Publication date: 2023-08-22
Anticipated expiration: 2033-04-20

Abstract

The utility model discloses an LDPC check node computing device based on full correlation semi-probability computation, which comprises an input computing circuit and a selection output circuit, wherein the input computing circuit comprises a plurality of AND gates, OR gates and calculators, the AND gates, the OR gates and the calculators are sequentially connected and output min_bits data of a minimum value min and min2_bits data of an approximate minor value min2, the selection output circuit comprises a comparator and a selector, the comparator is connected with an input signal dc and the min_bits data and inputs a control signal to the selector, and the selector is used for selectively outputting the min_bits data or the min2_bits data. The utility model adopts an approximate mode to obtain the next-smallest value in the absolute value, the sign bit calculation mode is consistent with the conventional structure, and when the check node dc is larger, the resource is better.

Description

LDPC check node calculating device based on full-correlation semi-probability calculation

Technical Field

The utility model relates to the technical field of LDPC check node calculation, in particular to an LDPC check node calculation device based on full-correlation semi-probability calculation.

Background

The LDPC decoding algorithm flow based on the minimum sum algorithm is as follows:

step 1. L (q) is transferred from variable node to check node _nm ) Initializing, namely:

L ⁽⁰⁾ (q _nm )＝L(P _n )，(1-1)；

step 2, checking the node c _m To variable node v _n Passed logarithmic domain message L (r _nm ) Updating is performed as follows:

step 3, for variable node v _n To check node c _m The probability domain message L (q) _nm ) Updating is performed as follows:

step 4. Update all L (q) _n ) The formula is as follows:

if L (q) _n ) > 0, thenTranslation to 0, otherwise translation to 1;

and 5, judging iteration suspension conditions. Generally when the iteration reaches a maximum number of times orAnd (6) stopping iteration and executing the step (6). Otherwise, returning to the step 2 to continue execution;

step 6, according to the code rate, toAnd intercepting and outputting the original information, and finishing decoding.

The check node calculation of the utility model, namely the corresponding formula (1-2), uses the information base transmitted by the variable node to the check node to calculate the minimum value of the symbol multiplication of the data in different sets and the absolute value of the data.

Correlation technique of probability calculation: when the correlation between sequences tends to be minimum or maximum, some complex operations can be converted into simple AND gates, OR gates or exclusive OR gates to calculate, so that the calculation amount can be greatly reduced, and the specific list is as follows:

table 1 probability calculation table

Wherein SCC refers to the data correlation between x and y; 0 represents that there is no correlation between x and y; +1 represents that the correlation between x and y is the largest, i.e. x is fully correlated with y; the LDPC check node calculating unit based on probability calculation simplifies the minimum value calculation amount of the absolute value by utilizing the full correlation characteristic among data, and replaces the calculation process of the minimum value by an AND gate.

The structure of a conventional LDPC decoding device based on full correlation probability calculation is shown in FIG. 1, wherein CNU is a check node calculation unit.

The conventional structure of the LDPC decoding check node device based on full correlation is shown in fig. 2, 3 and 4, wherein in the calculation of full correlation probability, the calculation structure of the check node is described in fig. 2, and as can be seen from fig. 4, the calculation complexity is dc-1.

Disclosure of Invention

The utility model aims to provide an LDPC check node calculating device based on full-correlation half-probability calculation, which aims to solve the technical problem that the complexity of hardware implementation increases exponentially along with the increase of check node degree.

The utility model aims at adopting the following technical scheme: the LDPC check node calculating device based on full correlation semi-probability calculation comprises an input calculating circuit and a selection output circuit, wherein the input calculating circuit comprises a plurality of AND gates, OR gates and calculators, the AND gates, the OR gates and the calculators are sequentially connected and output min_bits data of a minimum value min and min2_bits data of an approximate minor value min2 as inputs of the selection output circuit, the selection output circuit comprises a comparator and a selector, the comparator is connected with input signals dc and the min_bits data and inputs control signals to the selector, and the selector selects and outputs the min_bits data or the min2_bits data.

Further, the input computing circuit comprises a first AND gate circuit and a second AND gate circuit, wherein the first AND gate circuit is connected with the first calculator through the OR gate circuit and is connected with the second calculator through the third AND gate circuit; the second AND gate circuit is connected with the first calculator through the OR gate circuit and is connected with the second calculator through the third AND gate circuit.

Further, the output end of the first calculator outputs min_bits data, wherein the min_bits data is the number of 1 in a bit stream with a minimum value of min; and the output end of the second calculator outputs the min2 bits data, wherein the min2 bits data is the number of 1 in the bit stream of the approximate minor value min 2.

Further, the number of the selection output circuits is the same as the magnitude of the input signal dc, and the structure of each selection output circuit is the same, and the input signal dc is the weight of the row in the H matrix.

Further, the selection output circuit comprises a comparator and a selector, wherein the input end of the comparator is connected with min_bits data and an input signal dc, and a calculator is arranged between the input signal dc and the comparator; the data input end of the selector is connected with the min_bits data and the min2_bits data, and the control end of the selector is connected with the output end of the comparator.

The utility model has the beneficial effects that: the utility model adopts an approximate mode to obtain the next-smallest value in the absolute value, the sign bit calculation mode is consistent with the conventional structure, and when the check node dc is larger, the resource is better.

Drawings

In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described, and the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a conventional LDPC decoding device based on full correlation probability calculation;

fig. 2, fig. 3, and fig. 4 are schematic structural diagrams of conventional LDPC decoding check node devices based on full correlation;

fig. 5 is a schematic structural view of the present utility model.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present utility model more apparent, the technical solutions of the embodiments of the present utility model will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present utility model, and it is apparent that the described embodiments are some embodiments of the present utility model, but not all embodiments of the present utility model. The components of the embodiments of the present utility model generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.

Thus, the following detailed description of the embodiments of the utility model, as presented in the figures, is not intended to limit the scope of the utility model, as claimed, but is merely representative of selected embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.

Example 1

Referring to fig. 5, an LDPC check node calculation device based on full correlation half probability calculation includes an input calculation circuit and a selection output circuit, where the input calculation circuit includes a plurality of and circuits, or circuits, and a calculator, the and circuits, or circuits, and the calculator are sequentially connected and output min_bits data of a minimum value min and min2_bits data of an approximate minor value min2 as inputs of the selection output circuit, and the selection output circuit includes a comparator and a selector, where the comparator accesses an input signal dc and the min_bits data, and inputs a control signal to the selector, and the selector selects and outputs the min_bits data or the min2_bits data.

In this embodiment, the input computing circuit includes a first and a second and, where the first and is connected to the first calculator through an or gate, and is connected to the second calculator through a third and gate; the second AND gate circuit is connected with the first calculator through the OR gate circuit and is connected with the second calculator through the third AND gate circuit. Further, the output end of the first calculator outputs min_bits data, wherein the min_bits data is the number of 1 in a bit stream with a minimum value of min; and the output end of the second calculator outputs the min2 bits data, wherein the min2 bits data is the number of 1 in the bit stream of the approximate minor value min 2.

In this embodiment, the number of the selection output circuits is the same as the magnitude of the input signal dc, and the structure of each selection output circuit is the same, and the input signal dc is the weight of the row in the H matrix.

In this embodiment, the selection output circuit includes a comparator and a selector, where an input end of the comparator is connected to the min_bits data and an input signal dc, and a calculator is further disposed between the input signal dc and the comparator; the data input end of the selector is connected with the min_bits data and the min2_bits data, and the control end of the selector is connected with the output end of the comparator.

Taking dc=31 as an example, the present apparatus will be described (provided that the input data m0-m31 are fully correlated):

step one, the minimum value in the input bit data m0 to m15 is obtained to obtain half_min0, and the calculation method is based on the full correlation characteristic of the data m0 to m15, and the minimum value is replaced by 16 input AND gates.

And step two, obtaining the minimum value of the input bit data m16 to m31 to obtain half_min1, wherein the calculation method is the same as that in the step one.

Step three, the minimum value min in the half_minum0 and the half_minum1 is obtained, and the calculation method is based on the full correlation characteristic of the half_minum0 and the half_minum1, and the minimum value in the half_minum0 and the half_minum1 is replaced by a two-input AND gate.

And fourthly, obtaining the maximum value min2 in the half_minum0 and half_minum1, wherein the calculating method is based on the full correlation characteristic of the half_minum0 and half_minum1, and replacing the calculation of the maximum value in the half_minum0 and half_minum2 through a two-input OR gate, wherein the obtained min2 in the step is the next smallest value in the approximate m0-m 31.

And fifthly, converting the single bit stream of the min into a numerical value min_bits of multi-bit width, wherein the calculating mode is that the number of 1 in the bit stream of the min is counted through a count calculator.

Step six, converting the single bit stream of the min2 into a numerical value min2_bits of multi-bit width, wherein the calculating mode is that the number of 1 in the bit stream of the min2 is counted through a count calculator.

And step seven, converting the single bit stream of m0 into a numerical value m0_bits of multi-bit width, wherein the calculation mode is that the number of 1 in the bit stream of m0 is counted by a count calculator.

Step eight, when m0_bits is equal to min_bits, selecting min2_bits for outputting to obtain output data N0=min 2_bits; when m0_bits is not equal to min_bits, selecting min_bits for outputting, and obtaining output data N0=min_bits.

And step nine, consistent with the modes of step seven and eight, obtaining outputs N1-N31.

In this device, the values of N0 to N31 are multi-bit data, and the device can be applied to an LDPC decoding device for half-probability calculation. Half probability calculation: the probability calculation mode is adopted for the check nodes, and the conventional calculation mode is adopted for the check nodes.

The utility model adopts an approximate mode to obtain the next-smallest value in the absolute value, the sign bit calculation mode is consistent with the conventional structure, and when the check node dc is larger, the resource is better.

It should be noted that the terms "coupled," "configured," and "arranged" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implying a number of technical features being indicated. Thus, features defining "connected", "arranged" may explicitly or implicitly include one or more such features. Moreover, the terms "connected," "configured," and the like are used to distinguish between similar objects and do not necessarily describe a particular order or sequence. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein.

In the above embodiments, the basic principle and main features of the present utility model and advantages of the present utility model are described. It will be appreciated by persons skilled in the art that the present utility model is not limited by the foregoing embodiments, but rather is shown and described in what is considered to be illustrative of the principles of the utility model, and that modifications and changes can be made by those skilled in the art without departing from the spirit and scope of the utility model, and therefore, is within the scope of the appended claims.

Claims

1. The LDPC check node calculating device based on full correlation semi-probability calculation is characterized by comprising an input calculating circuit and a selection output circuit, wherein the input calculating circuit comprises a plurality of AND gates, OR gates and calculators, the AND gates, the OR gates and the calculators are sequentially connected and output min_bits data of a minimum value min and min2_bits data of an approximate minor value min2 as inputs of the selection output circuit, the selection output circuit comprises a comparator and a selector, the comparator is connected with an input signal dc and the min_bits data and inputs a control signal to the selector, and the selector selects and outputs the min_bits data or the min2_bits data.

2. The LDPC check node calculation device based on full correlation half probability calculation as claimed in claim 1, wherein the input calculation circuit comprises a first and gate circuit and a second and gate circuit, the first and gate circuit is connected with the first calculator through an or gate circuit, and is connected with the second calculator through a third and gate circuit; the second AND gate circuit is connected with the first calculator through the OR gate circuit and is connected with the second calculator through the third AND gate circuit.

3. The LDPC check node computing device based on full correlation half probability computation as claimed in claim 2, wherein the output end of the first calculator outputs min_bits data, the min_bits data being the number of 1 s in the bit stream of the minimum value min; and the output end of the second calculator outputs the min2 bits data, wherein the min2 bits data is the number of 1 in the bit stream of the approximate minor value min 2.

4. A full correlation half probability calculation based LDPC check node calculation apparatus as claimed in claim 3, wherein the number of said selection output circuits is the same as the size of the input signal dc, which is the weight of the rows in the H matrix, and each selection output circuit is identical in structure.

5. The LDPC check node calculating device based on full correlation half probability calculation according to claim 4, wherein the selection output circuit comprises a comparator and a selector, wherein the input end of the comparator is connected with min_bits data and an input signal dc, and a calculator is arranged between the input signal dc and the comparator; the data input end of the selector is connected with the min_bits data and the min2_bits data, and the control end of the selector is connected with the output end of the comparator.