CN219575617U - Semiconductor package - Google Patents

Abstract

The present utility model provides a semiconductor package, comprising: a semiconductor chip including a pillar located on the active surface and protruding with respect to the active surface; the buffer layer is positioned on the active surface and coats the upright post; and a molding compound layer encapsulating the semiconductor chip and the buffer layer, an upper surface of the molding compound layer including a downwardly concave curved surface adjacent to the buffer layer. Embodiments of the present utility model provide for increased structural stability of a semiconductor package by encapsulating a semiconductor chip with a buffer layer and a molding compound layer that together resist warpage of the structure upon thermal cycling.

Description

Semiconductor package

Technical Field

The present utility model relates to a semiconductor package.

Background

Referring to fig. 1, in the advanced wafer level package (advanced Wafer Level Package, aWLP) structure, after the active surface of the chip (chip) 2 is packaged (molded) with the molding compound (molding) 6, the redistribution layer (RDL) 4 is configured (built) on the active surface, wherein the rigidity of the molding compound 6 and the chip 2 is stronger than that of the dielectric layer 402 in the redistribution layer 4, and the material of the dielectric layer 402 is Polyimide (PI), so that the dielectric layer 402 needs to bear the stress generated by the mismatch of the thermal expansion Coefficient (CTE) of the material during the thermal cycle, and the problem that the delamination (degradation) or the cracking (crack) of the interface between the dielectric layer 402 and the molding compound 6 or the chip 2 is easily caused because the dielectric layer 402 bears the larger stress and cannot be completely released is easily caused.

Fig. 2-5 illustrate another embodiment of an advanced wafer level package structure of the prior art, wherein fig. 3 is an enlarged view of region a of fig. 2, and fig. 4 and 5 are enlarged views of two defect cases of region b of fig. 3. Referring to fig. 4, heterogeneous materials (chip 2, dielectric layer 402, molding compound 6) interface at the corners of chip 2, the CTE of chip 2 (material is silicon) is 2.5, the CTE of dielectric layer 402 is 5 to 30, the CTE of molding compound 6 is 10 to 20, and in reliability test (Reliability testing), the entire structure will warp during thermal cycling due to CTE mismatch and small CTE of molding compound 6, delamination is extremely likely to occur at the heterogeneous material interface at the corners of chip 2, further extending into redistribution layer 4 to generate crack 3. Referring to fig. 5, molding compound 6 may infiltrate between the chip 2 and the dielectric layer 402 due to delamination at the heterogeneous material interface at the corners of the chip 2, resulting in the occurrence of a mold flash (mold flash) condition.

Disclosure of Invention

In view of the problems in the related art, an object of the present utility model is to provide a device.

To achieve the above object, the present utility model provides a semiconductor package comprising: a semiconductor chip including a pillar located on the active surface and protruding with respect to the active surface; the buffer layer is positioned on the active surface and coats the upright post; and a molding compound layer encapsulating the semiconductor chip and the buffer layer, an upper surface of the molding compound layer including a downwardly concave curved surface adjacent to the buffer layer.

In some embodiments, the curved surface abuts the upper surface of the buffer layer.

In some embodiments, the inner boundary of the curved surface is aligned with the upper surface of the buffer layer.

In some embodiments, the material of the buffer layer is the same as the material of the molding compound.

In some embodiments, the semiconductor package further comprises: and a redistribution layer on the buffer layer and the molding compound layer, the redistribution layer electrically connecting the pillars of the semiconductor chip.

In some embodiments, the redistribution layer includes a dielectric layer, portions of which conform to the curved surface.

In some embodiments, the thickness of the buffer layer is greater than the thickness of a single dielectric layer in a single redistribution layer.

In some embodiments, the rigidity of the molding compound layer is greater than the rigidity of the dielectric layer.

In some embodiments, the buffer layer is stiffer than the dielectric layer.

In some embodiments, the material of the dielectric layer is polyimide.

In some embodiments, the sidewalls of the buffer layer are aligned with the sidewalls of the semiconductor chip.

In some embodiments, the sidewalls of the buffer layer form corners with the sidewalls of the semiconductor chip.

In some embodiments, the buffer layer has a horizontal dimension that is smaller than a horizontal dimension of the semiconductor chip.

In some embodiments, the molding compound layer completely encapsulates the sidewalls of the buffer layer, the sidewalls and the bottom surface of the semiconductor chip.

In some embodiments, the upper surface of the cushioning layer is flush with the upper surface of the post.

In some embodiments, the roughness of the upper surface of the buffer layer is greater than the roughness of the lower surface of the buffer layer.

In some embodiments, the upper surface of the buffer layer has a plurality of first inner grooves.

In some embodiments, the roughness of the upper surface of the pillar is greater than the roughness of the lower surface of the pillar.

In some embodiments, the upper surface of the pillar has a plurality of second concave grooves.

In some embodiments, a portion of the first concave groove and a portion of the second concave groove are continuous.

In some embodiments, the roughness of the upper surface of the buffer layer is greater than the roughness of the upper surface of the molding compound layer, the upper surface of the molding compound layer not including the recessed groove.

The beneficial technical effects of the utility model are as follows:

embodiments of the present utility model provide for increased structural stability of a semiconductor package by encapsulating a semiconductor chip with a buffer layer and a molding compound layer that together resist warpage of the structure upon thermal cycling.

Drawings

Fig. 1 shows a prior art advanced wafer level package structure.

Fig. 2-5 illustrate another embodiment of an advanced wafer level package structure of the prior art, wherein fig. 3 is an enlarged view of region a of fig. 2, and fig. 4 and 5 are enlarged views of two defect cases of region b of fig. 3.

Fig. 6 shows a semiconductor chip according to an embodiment of the utility model.

Fig. 7 illustrates forming a buffer layer according to an embodiment of the present utility model.

Fig. 8 illustrates a step of planarizing the buffer layer until the pillars are exposed, in accordance with an embodiment of the present utility model.

Fig. 9 illustrates a step of inverting the singulated structure onto an adhesive tape according to an embodiment of the utility model.

Fig. 10 illustrates forming a layer of molding compound according to an embodiment of the utility model.

Fig. 11 shows the step of removing the carrier and the tape.

Fig. 12 illustrates constructing a redistribution layer according to an embodiment of the present utility model.

Fig. 13 is an enlarged view of a region d of fig. 12, and fig. 14 is an enlarged view of a region e of fig. 13.

Fig. 15 through 21 illustrate semiconductor packages and methods of forming the same according to further embodiments of the present utility model.

Fig. 15 shows a semiconductor chip according to an embodiment of the present utility model.

Fig. 16 illustrates forming a buffer layer according to an embodiment of the present utility model.

Fig. 17 illustrates a step of planarizing the buffer layer until the pillars are exposed, in accordance with an embodiment of the present utility model.

Fig. 18 illustrates a step of inverting the singulated structure onto an adhesive tape according to an embodiment of the utility model.

Fig. 19 illustrates forming a layer of molding compound according to an embodiment of the utility model.

Fig. 20 illustrates constructing a redistribution layer according to an embodiment of the present utility model.

Fig. 21 shows a semiconductor package of an embodiment different from that of fig. 20.

Detailed Description

For a better understanding of the spirit of embodiments of the present utility model, a further description of some preferred embodiments of the utility model is provided below.

Embodiments of the present utility model will be described in detail below. Throughout the present specification, the same or similar components and components having the same or similar functions are denoted by similar reference numerals. The embodiments described herein with respect to the drawings are of illustrative nature, of diagrammatic nature and are provided for the basic understanding of the present utility model. The embodiments of the present utility model should not be construed as limiting the utility model.

As used herein, the terms "substantially," "substantially," and "about" are used to describe and illustrate minor variations. When used in connection with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely and instances where it occurs to the close approximation.

In this specification, unless specified or limited otherwise, relative terms such as: the terms "central," "longitudinal," "lateral," "front," "rear," "right," "left," "interior," "exterior," "lower," "upper," "horizontal," "vertical," "above," "below," "upper," "lower," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the directions as described in the discussion or as illustrated in the drawings. These relative terms are for convenience of description only and do not require that the utility model be constructed or operated in a particular orientation.

For ease of description, "first," "second," "third," etc. may be used herein to distinguish between different components of a figure or series of figures. The terms "first," "second," "third," and the like are not intended to describe corresponding components.

The semiconductor package 100 and the method of forming the same of the present utility model will be described below with reference to the accompanying drawings.

Referring to fig. 6, a semiconductor chip 10 is provided, including pillars 12 located on and protruding with respect to an active surface.

Referring to fig. 7, the active surface of the semiconductor chip 10 and the pillars 12 thereon are covered with a buffer layer 20.

Referring to fig. 8, a planarization process (e.g., grinding) is performed to planarize the buffer layer 20 until the pillars 12 are exposed. After the polishing process is completed, the buffer layer 20 and the polished surface of the pillar 12 are each provided with a polishing trace, such as a recessed groove, and the polishing trace is continuous on the upper surface of the structure shown in fig. 8. In some embodiments, the buffer layer 20 may be formed of an encapsulation material (molding material). The encapsulation material may include phenolic-based resin (Novolac-based resin), epoxy-based resin (epoxy-based resin), silicone-based resin (silicone-based resin), or other suitable coating agents. The encapsulation material may also include a suitable filler (filler), such as powdered silicon dioxide, in which case a portion of the filler exposed at the upper surface of the buffer layer 20 is ground to thus include kerfs and another portion of the filler exposed at the upper surface of the buffer layer 20 is not ground to thus not include kerfs. The encapsulation material may be a pre-impregnated material (pre-impregnated (prepreg) material), for example a pre-impregnated dielectric material.

In some embodiments, a plurality of semiconductor chips 10 are connected and together form a continuous buffer layer 20 thereon, which is cut into singulated structures along dashed line c after the planarization process of fig. 8.

Referring to fig. 9, the singulated structure of fig. 8 is inverted over tape 92 on carrier 90.

Referring to fig. 10, a molding compound layer 30 is formed to encapsulate the semiconductor chip 10 and the buffer layer 20. In some embodiments, the material of the molding compound layer 30 is the same as that of the buffer layer 20, that is, six sides of the semiconductor chip 10 are covered with the same material, solving the problems of delamination and cracking caused by heterogeneous materials in the prior art.

In some embodiments, although not shown, in fig. 9 the semiconductor chip 10 and the buffer layer 20 may be trapped in the tape 92, i.e., the tape 92 has an invaginated portion in contact with the semiconductor chip 10 and the buffer layer 20, other portions of the tape 92 gradually transition from the original plane to the invaginated portion, and the transition portion is a curved surface protruding upward, such that the bottom surface of the molding compound layer 30 in fig. 10 (conformal to the tape 92) includes a curved surface (see, for example, curved surface 32 of fig. 21) adjacent to the buffer layer 20, the curved surface being recessed with respect to the bottom surface of the buffer layer 20.

Referring to fig. 11, carrier 90 and tape 92 are removed.

Referring to fig. 12, the resulting structure of fig. 11 is flipped over and a redistribution layer 40 and solder balls 120 are constructed thereon, the redistribution layer 40 including a dielectric layer 42.

Fig. 13 is an enlarged view of a region d of fig. 12, and fig. 14 is an enlarged view of a region e of fig. 13. An Under Bump Metal (UBM) 130 electrically connects the pillars 12 and the redistribution layer 40. The materials of the buffer layer 20 and the molding compound layer 30 are the same, and thus the interface therebetween is not shown, the semiconductor chip 10 of the embodiment of the present utility model is surrounded by the buffer layer 20 and the molding compound layer 30, and the buffer layer 30 separates the semiconductor chip 10 from the dielectric layer 42 of the redistribution layer 40, and particularly reduces heterogeneous materials at the corners of the semiconductor chip 10, thus solving the problem of easy delamination and cracking at the corners of the semiconductor chip 10.

Fig. 15-21 illustrate a semiconductor package 100 and methods of forming the same according to further embodiments of the present utility model.

Referring to fig. 15, a semiconductor chip 10 is provided, including pillars 12 on bonding pads 14 of an active face and protruding with respect to the bonding pads 14.

Referring to fig. 16, the active surface of the semiconductor chip 10 and the pillars 12 thereon are covered with a buffer layer 20.

Referring to fig. 17, a planarization process (e.g., grinding) is performed to planarize the buffer layer 20 until the pillars 12 are exposed. After the polishing process is completed, the buffer layer 20 and the polished surface of the pillar 12 have polishing traces, such as concave grooves, and the polishing traces are continuous on the upper surface of the structure shown in fig. 17. In some embodiments, the buffer layer 20 may be formed of an encapsulation material (molding material). The encapsulation material may include phenolic-based resin (Novolac-based resin), epoxy-based resin (epoxy-based resin), silicone-based resin (silicone-based resin), or other suitable coating agents. The encapsulant may also include a suitable filler (filler), such as powdered silicon dioxide, in which case a portion of the filler exposed at the upper surface of the buffer layer 20 is ground, thus including the kerf, and another portion of the filler exposed at the upper surface of the buffer layer 20 is not ground, thus not including the kerf. The encapsulation material may be a pre-impregnated material (pre-impregnated (prepreg) material), for example a pre-impregnated dielectric material.

In some embodiments, a plurality of semiconductor chips 10 are connected and together form a continuous buffer layer 20 thereon, which is cut into singulated structures along the dashed line f after the planarization process of fig. 17.

Referring to fig. 18, the singulated structure of fig. 17 is inverted on a tape 92 (not shown) on a carrier 90.

Referring to fig. 19, a molding compound layer 30 is formed to encapsulate the semiconductor chip 10 and the buffer layer 20. In some embodiments, the material of the molding compound layer 30 is the same as that of the buffer layer 20, that is, six sides of the semiconductor chip 10 are covered with the same material, solving the problems of delamination and cracking caused by heterogeneous materials in the prior art.

Referring to fig. 20, carrier 90 and tape 92 (not shown) are removed, the resulting structure is flipped over, and redistribution layer 40 is constructed thereon, with redistribution layer 40 including dielectric layer 42.

Fig. 21 shows an embodiment different from that of fig. 20 in that in fig. 18 the semiconductor chip 10 and buffer layer 20 are immersed in an adhesive tape 92 (not shown) on a carrier 90, such that the top surface of the molding compound layer 30 obtained in fig. 21 comprises a curved surface 32 adjoining the buffer layer 20, the curved surface 32 being recessed downwards. In some embodiments, the sag depth of the curved surface 32 is 1 μm to 3 μm, for example 2 μm. In some embodiments, the recess depth of the curved surface 32 is less than the thickness of the dielectric layer 42.

In some embodiments, since the buffer layer 20 is softer than the semiconductor chip 10 (the host material is silicon), the buffer layer 20 will be cut more during the dicing step shown in fig. 17, and thus the buffer layer 20 will shrink as shown in fig. 21 compared to the sidewalls of the semiconductor chip 10. The sidewalls of buffer layer 20 and the sidewalls of the semiconductor die may have dicing marks. The sidewalls of the buffer layer 20 are shrunk compared to the sidewalls of the semiconductor chip 10, and thus even though the material of the buffer layer 20 is different from that of the molding compound layer 30, the corners of the semiconductor chip 10 are completely covered with the molding compound layer 30 of the same material, thus reducing heterogeneous materials at the locations where stress is concentrated (corners of the semiconductor chip 10), thereby reducing the risk of delamination and cracking.

Embodiments of the present utility model provide a semiconductor package 100 including: a semiconductor chip 10 including a pillar 12 located on and protruding with respect to the active surface; a buffer layer 20 on the active surface and covering the pillars 12; the molding compound layer 30 encapsulates the semiconductor chip 10 and the buffer layer 20, and an upper surface of the molding compound layer 30 includes a downwardly concave curved surface 32 adjacent to the buffer layer 20.

In some embodiments, curved surface 32 abuts the upper surface of buffer layer 20.

In some embodiments, the inner boundary of the curved surface 32 is aligned with the upper surface of the buffer layer 20.

In some embodiments, the material of the buffer layer 20 is the same as the material of the molding compound.

In some embodiments, the semiconductor package 100 further includes: a redistribution layer 40 is disposed on the buffer layer 20 and the molding compound layer 30, the redistribution layer 40 electrically connecting the pillars 12 of the semiconductor chip 10.

In some embodiments, the redistribution layer 40 includes a dielectric layer 42, with portions of the dielectric layer 42 directly over the curved surfaces 32 conforming to the curved surfaces 32.

In some embodiments, the thickness of buffer layer 20 is greater than the thickness of single layer dielectric layer 42 in single layer redistribution layer 40.

In some embodiments, the rigidity of the molding compound layer 30 is greater than the rigidity of the dielectric layer 42.

In some embodiments, the rigidity of the buffer layer 20 is greater than the rigidity of the dielectric layer 42.

In some embodiments, the material of dielectric layer 42 is polyimide.

In some embodiments, the sidewalls of the buffer layer 20 are aligned with the sidewalls of the semiconductor chip 10.

In some embodiments, the sidewalls of the buffer layer 20 form corners with the sidewalls of the semiconductor chip 10.

In some embodiments, the horizontal dimension of the buffer layer 20 is smaller than the horizontal dimension of the semiconductor chip 10.

In some embodiments, the molding compound layer 30 completely encapsulates the sidewalls of the buffer layer 20, the sidewalls and the bottom surface of the semiconductor chip 10.

In some embodiments, the upper surface of the cushioning layer 20 is flush with the upper surface of the post 12.

In some embodiments, the roughness of the upper surface of the buffer layer 20 is greater than the roughness of the lower surface of the buffer layer 20.

In some embodiments, the upper surface of the buffer layer 20 has a plurality of first inner grooves.

In some embodiments, the roughness of the upper surface of the pillar 12 is greater than the roughness of the lower surface of the pillar 12.

In some embodiments, the upper surface of the pillar 12 has a plurality of second concave grooves.

In some embodiments, a portion of the first concave groove and a portion of the second concave groove are continuous.

In some embodiments, the roughness of the upper surface of the buffer layer 20 is greater than the roughness of the upper surface of the molding compound layer 30, and the molding compound layer 30 is not ground, so that the upper surface thereof does not include recessed grooves.

The embodiments of the present utility model increase the structural stability of the semiconductor package 100 by the buffer layer 20 and the molding compound layer 30 coating the semiconductor chip 10, the buffer layer 20 and the molding compound layer 30 together opposing the warpage of the structure upon thermal cycling.

And the present utility model also reduces the foreign materials in contact with the semiconductor chip 10, thus solving the problem of aggravating structural warpage caused by CTE mismatch of the foreign materials in the prior art, and also reducing the possibility of delamination and cracking between the foreign materials, and greatly improving the yield of products passing the stability test.

The above description is only of the preferred embodiments of the present utility model and is not intended to limit the present utility model, but various modifications and variations can be made to the present utility model by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model should be included in the protection scope of the present utility model.

Claims (10)

1. A semiconductor package, comprising:

a semiconductor chip including a pillar located on an active surface and protruding with respect to the active surface;

the buffer layer is positioned on the active surface and coats the upright post;

and a molding compound layer encapsulating the semiconductor chip and the buffer layer, an upper surface of the molding compound layer including a downwardly concave curved surface adjacent to the buffer layer.

2. The semiconductor package of claim 1, wherein the curved surface abuts an upper surface of the buffer layer.

3. The semiconductor package of claim 2, wherein an inner boundary of the curved surface is aligned with an upper surface of the buffer layer.

4. The semiconductor package of claim 1, further comprising:

and a redistribution layer on the buffer layer and the molding compound layer, the redistribution layer electrically connecting the pillars of the semiconductor chip.

5. The semiconductor package of claim 4, wherein the redistribution layer comprises a dielectric layer, a portion of the dielectric layer conforming to the curved surface.

6. The semiconductor package of claim 5, wherein a thickness of the buffer layer is greater than a thickness of a single one of the dielectric layers in a single one of the redistribution layers.

7. The semiconductor package of claim 6, wherein the rigidity of the molding compound layer is greater than the rigidity of the dielectric layer.

8. The semiconductor package of claim 7, wherein the buffer layer has a stiffness greater than a stiffness of the dielectric layer.

9. The semiconductor package of claim 8, wherein the material of the dielectric layer is polyimide.

10. The semiconductor package of claim 1, wherein the molding compound layer completely encapsulates sidewalls of the buffer layer, sidewalls and bottom surface of the semiconductor chip.