CN219574360U - Single photon detector device for laser radar signal real-time post-pulse correction - Google Patents
Single photon detector device for laser radar signal real-time post-pulse correction Download PDFInfo
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Abstract
The utility model discloses a single photon detector device for real-time post-pulse correction of a laser radar signal, which comprises an avalanche photodiode, a refrigeration box, a discriminator, a main control FPGA unit, a calculation MCU unit and a FLASH unit, wherein a conversion unit, a calculation unit, a correction unit and the like in the existing correction scheme are integrated in the single photon detector device in a hardware form, and the fitting of a post-pulse probability distribution function can be completed when performance indexes of the single photon detector device are calibrated in advance, and fitting coefficients are stored, so that the single photon detector device capable of real-time post-pulse correction of the laser radar signal is realized, and a high-integration solution for integrating weak light detection and data post-processing is provided for single photon laser radar application.
Description
Technical Field
The utility model relates to the field of single photon detectors, in particular to a single photon detector device for real-time post-pulse correction of laser radar signals.
Background
The single-photon laser radar utilizes the ultra-high sensitivity and high signal-to-noise ratio of the single-photon detector to carry out the efficient detection of the laser radar echo optical signal, and realizes the detection distance which is farther than that of the traditional laser radar under the same laser emission power. The superconducting single photon detector has the performance closest to that of an ideal single photon detector, the detection efficiency is higher than 90 percent, the dark count rate is lower than 10Hz, and the probability of a rear pulse can be ignored, but the superconducting single photon detector needs to be matched with a large-scale refrigerating device to be refrigerated to the working temperature of 4K, so that the implementation is limited.
The InGaAs/InP single photon detector has the advantages of small volume, low cost, easy system integration, good comprehensive performance index and the like, and is the best choice for the practical single photon laser radar at present. In order to reduce the dark count rate and improve the signal to noise ratio, the InGaAs/InP single photon detector usually works at the refrigeration temperature of 170-230K, but the high post-pulse effect is brought about, and the echo signal of the laser radar is distorted.
In the prior art, for example, chinese patent application No. CN106842168A, a method and a device for correcting laser radar signal distortion caused by the post-pulse effect of an InGaAs/InP single photon detector are proposed, for example, as shown in fig. 1, which mainly disclose the following correction process: converting laser radar echo signals to be corrected at the distance bin into discrete count rate distribution; calculating the post pulse counting rate of the laser radar signal generated at the distance bin according to the acquired first post pulse probability distribution function and counting rate distribution; subtracting the pulse count rate from the count rate distribution to obtain a corrected first laser radar echo signal; and carrying out nonlinear correction on the corrected laser radar echo signal to obtain a corrected second laser radar echo signal. The first post-pulse probability distribution function may be obtained by a technician obtaining a second post-pulse probability distribution function through experiments in advance and then fitting the second post-pulse probability distribution function.
However, most single photon detectors in the prior art output a detection pulse signal corresponding to the input optical signal and the noise signal, for example, an LVTTL level detection pulse electrical signal is output through the SMA interface. Therefore, in the implementation process of the post-pulse correction scheme disclosed in, for example, CN106842168A, chinese patent application, the first post-pulse probability distribution function is usually stored in a computer offline, and when receiving the laser radar signal, a time-to-digital converter (TDC) device (corresponding to a converting unit) is used to cumulatively extract time-count distribution information corresponding to the detection pulse of the single photon detector, and the distribution data is transmitted to a PC through a communication cable, and finally, the final data can be obtained through post-pulse correction by a computing program (corresponding to a computing unit and a correcting unit) set on the PC.
Disclosure of Invention
The utility model discloses a single photon detector device for real-time post pulse correction of laser radar signals, which integrates a conversion unit, a calculation unit, a correction unit and other modules in the single photon detector device in a hardware mode based on the existing post pulse correction scheme, and can complete fitting of a post pulse probability distribution function when performance indexes of the single photon detector device are calibrated in advance, and fitting coefficients are stored, so that the single photon detector device for real-time post pulse correction of the laser radar signals is realized, and a high-integration solution integrating weak light detection and data post processing is provided for single photon laser radar application.
The utility model discloses a single photon detector device for laser radar signal real-time post-pulse correction, which comprises an avalanche photodiode and a refrigeration box, and is characterized by further comprising a discriminator, a main control FPGA unit, a calculation MCU unit and a FLASH unit;
the refrigeration box is used for refrigerating the avalanche photodiode and extracting avalanche signals;
the discriminator is configured to discriminate the avalanche signal as a detection pulse signal;
the FLASH unit is arranged for storing a post-pulse probability distribution function;
the main control FPGA unit is used for acquiring time interval data of the detection pulse signals relative to the TRIG signals, reading a rear pulse probability distribution function in the FLASH unit, and sending the time interval data and the rear pulse probability distribution function to the calculation MCU unit;
the computation MCU unit is arranged for post-pulse correction using the accumulated time-count distribution and post-pulse probability distribution function.
Further, the single photon detector device further comprises a temperature sensing unit, and the refrigeration box comprises a TEC;
the TEC is configured to cool the avalanche photodiode;
the temperature sensing unit is arranged for acquiring temperature information of the avalanche photodiode;
the main control FPGA unit is used for controlling refrigeration working voltage for the TEC according to the temperature information.
Still further, the temperature sensing unit includes a thermistor and an ADC unit; the thermistor is arranged to monitor the temperature of the avalanche photodiode; the ADC unit is used for collecting the voltage division amplitude of the thermistor and sending the voltage division amplitude to the main control FPGA unit.
Further, the refrigeration box comprises a resistor R1, a resistor R2, a capacitor C1 and a first amplifier;
the resistor R1, the avalanche photodiode and the resistor R2 sequentially form a series circuit and are connected with a DC/DC power supply to obtain bias voltage;
the capacitor C1 is arranged to extract the avalanche signal from the series circuit in an ac-coupled manner;
the first amplifier is configured to amplify the avalanche signal output from the capacitor C1 and output the amplified avalanche signal to the discriminator.
Preferably, the first amplifier is a low noise amplifier.
Further, the single photon detector device further comprises a second amplifier;
the main control FPGA unit is further arranged for generating a dead time control signal based on the detection pulse signal;
the second amplifier is arranged to amplify the dead time control signal and to act on the avalanche photodiode.
Preferably, the master FPGA unit is configured to measure and obtain time interval data between the probing pulse signal and the TRlG signal using a carry delay chain clock interpolation technique.
Preferably, the TRIG signal is externally input; and/or, the avalanche photodiode is an NFAD device; and/or the detection pulse signal has a fixed level; and/or, the post-pulse probability distribution function is obtained by pre-fitting; and/or the main control FPGA unit and the computing MCU unit are in data communication through a high-speed data interface.
Further, the single photon detector device further comprises a data interface for data communication with the outside.
Preferably, the data interface is a USB interface.
Drawings
The following describes the embodiments of the present utility model in further detail with reference to the drawings.
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the present utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 schematically illustrates a device topology of a prior art lidar signal post-pulse correction scheme;
fig. 2 shows a structural topology of an example of a single photon detector device for real-time post-pulse modification of lidar signals of the present utility model.
Detailed Description
Hereinafter, exemplary embodiments of the present utility model will be described in detail with reference to the accompanying drawings. The following examples are provided by way of illustration to fully convey the spirit of the utility model to those skilled in the art to which the utility model pertains. Thus, the present utility model is not limited to the embodiments disclosed herein.
Fig. 2 shows an example of a single photon detector device for real-time post-pulse modification of a lidar signal according to the utility model.
As shown in the figure, the single photon detector device for laser radar signal real-time post-pulse correction can comprise hardware components such as an avalanche photodiode, a refrigeration box, a discriminator, a main control FPGA unit, a calculation MCU unit, a FLASH unit and the like.
The avalanche photodiode operates in a geiger mode with a bias voltage higher than the avalanche breakdown voltage for receiving, for example, the lidar return light signal and generating a corresponding avalanche current signal.
As a preferred example, the avalanche photodiode may be an NFAD (negative feedback avalanche photodiode) device.
The refrigeration cassette is used to provide the necessary refrigeration for the avalanche photodiode to suppress its dark count.
As shown in fig. 2, the refrigeration cassette may include a thermistor (e.g., PT 100) and a TEC (semiconductor refrigerator). The temperature of the NFAD device is monitored in real time by the thermistor, and the partial pressure amplitude on the thermistor is sampled (namely, temperature information related to the NFAD device is acquired) by the ADC unit and is sent to the main control FPGA unit. Therefore, the master control FPGA unit can obtain real-time temperature information of the NFAD device through calculation, and determine the refrigeration working voltage for the TEC according to the real-time temperature information (such as by means of a PID algorithm) so as to control the DC/DC power supply to output proper refrigeration working voltage to the TEC, and refrigeration temperature control is achieved. Here, it can be understood by those skilled in the art that the thermistor and ADC unit essentially constitute a kind of temperature sensing unit for NFAD devices.
According to the utility model, the refrigeration cassette can also be used for extracting corresponding avalanche signals from avalanche photodiodes, etc.
As shown in fig. 2, the refrigeration cassette may further include a resistor R1, a resistor R2, a capacitor C1, and a first amplifier. When an avalanche event occurs, an avalanche current signal output by the avalanche photodiode generates a voltage drop on the resistor R2, a weak avalanche signal is output through the ac coupling of the capacitor C1, and the weak avalanche signal is amplified by the gain of the first amplifier and then an avalanche signal with considerable amplitude is output, so that the effective extraction of the avalanche signal is realized.
As a preferred example, the first amplifier may be a Low Noise Amplifier (LNA).
Further, the main control FPGA unit may read initial configuration parameters from the FLASH unit, and apply a preset bias voltage Vb on the resistor R2, the NFAD device and the resistor R1 connected in series by controlling the DC/DC power output, so as to implement bias control of the NFAD device, for example.
In the utility model, the discriminator can discriminate the avalanche signal extracted by the refrigeration box into a detection pulse signal with a fixed level and send the detection pulse signal to the main control FPGA unit.
The main control FPGA unit may record the time interval of each probe pulse signal with respect to the TRIG signal by means of an integrated time-to-digital conversion function and transmit such time interval data to the computing MCU unit via, for example, a high-speed data interface. For example, the master FPGA unit may receive a TRIG signal (which is homologous to a laser pulse control signal emitted by the lidar) externally accessed by the probe, and measure and obtain time interval data between the probe pulse signal and the TRIG signal by a carry delay chain clock interpolation technique.
The FLASH unit is used for storing the post-pulse probability distribution function so as to be read by the main control FPGA unit and sent to the calculation MCU unit.
In the present utility model, the post-pulse probability distribution function may be generated by fitting in advance. For example, the light input interface of the single photon detector device may be masked in advance, and the dark count distribution for a certain time (for example, 60 seconds) is accumulated by the calculation MCU unit and stored in the FLASH unit; then, a narrow pulse light source is used for outputting pulse light with a certain frequency (such as 50 KHz) attenuated to the average single photon level per pulse, the pulse light is injected into a single photon detector device, and the light count distribution of the MCU unit accumulated for the same time (60 seconds) is calculated and stored in a FLASH unit; finally, a post-pulse probability distribution fitting function in the MCU unit is called, two counting distributions are read from the FLASH unit, dark counting distribution is subtracted from the light counting distribution, multi-exponential fitting (for example, double-exponential fitting or three-exponential fitting, which can be determined according to the calculation speed and precision requirement of post-pulse correction) is carried out by taking the counting peak position of the difference distribution as an origin, fitting coefficients are obtained and stored in the FLASH unit, and the post-pulse probability distribution function can be recovered through the fitting coefficients.
In the present utility model, the computation MCU unit may accumulate the time-count distribution of a fixed time interval (typically 1 second) after receiving the time interval data and the post-pulse probability distribution function provided by the master FPGA unit, and perform post-pulse correction on the time-count distribution by the post-pulse probability distribution function. For example, the computation MCU may subtract the contribution of the dark counts from the time-count distribution accumulated in real time (specifically, subtracting the average value of the pre-stored dark count distribution in each bin from the count of each bin), then calculate the post-pulse counts generated by the counts in each bin in other bins according to the pre-fitted post-pulse probability distribution function, accumulate them together to obtain the post-pulse count distribution, and subtract the post-pulse count distribution from the original time-count distribution to obtain post-pulse corrected data.
With continued reference to fig. 2, the master FPGA unit may also generate a dead time control signal (Hold-off) based on the probe pulse signal in accordance with the present utility model. For example, after receiving the detection pulse signal from the discriminator, the main control FPGA unit may generate and output a dead time control signal with a certain pulse width to the avalanche photodiode with the shortest delay, actively pull the bias voltage at two ends of the NFAD device, for example, to be below the avalanche breakdown voltage, release carriers, and suppress the post pulse.
As a preferred example, a second amplifier may be further provided in the single photon detector device for amplifying the dead time control signal output from the main control FPGA unit and applying it to the resistor R1, thereby acting on the avalanche photodiode to achieve the suppression of the post-pulse effect.
With continued reference to fig. 2, the single photon detector apparatus may also be provided with a data interface for enabling data communication interaction with the outside.
As a preferred example, the data interface may be a USB interface, which is used for outputting the data after pulse correction, reporting the real-time working state of the detector device, receiving an external control command, and the like.
In summary, the utility model is based on the existing laser radar signal real-time post-pulse correction scheme, and the laser radar signal subjected to post-pulse correction is output in real time through a data interface such as a USB interface by integrating time digital conversion and post-pulse correction functions through hardware such as an FPGA (field programmable gate array) and an MCU (micro control unit) in a single photon detector device, so that the laser radar application is not dependent on devices such as a TDC (digital logic controller) and a computer, and the system integration level can be greatly improved.
While the utility model has been described in connection with the specific embodiments illustrated in the drawings, it will be readily appreciated by those skilled in the art that the above embodiments are merely illustrative of the principles of the utility model, which are not intended to limit the scope of the utility model, and various combinations, modifications and equivalents of the above embodiments may be made by those skilled in the art without departing from the spirit and scope of the utility model.
Claims (10)
1. The single photon detector device for laser radar signal real-time post-pulse correction comprises an avalanche photodiode and a refrigeration box, and is characterized by further comprising a discriminator, a main control FPGA unit, a calculation MCU unit and a FLASH unit;
the refrigeration box is used for refrigerating the avalanche photodiode and extracting avalanche signals;
the discriminator is configured to discriminate the avalanche signal as a detection pulse signal;
the FLASH unit is arranged for storing a post-pulse probability distribution function;
the main control FPGA unit is used for acquiring time interval data of the detection pulse signals relative to the TRIG signals, reading a rear pulse probability distribution function in the FLASH unit, and sending the time interval data and the rear pulse probability distribution function to the calculation MCU unit;
the computation MCU unit is arranged for post-pulse correction using the accumulated time-count distribution and post-pulse probability distribution function.
2. The single photon detector apparatus as in claim 1 further comprising a temperature sensing unit and wherein said refrigeration cassette comprises a TEC;
the TEC is configured to cool the avalanche photodiode;
the temperature sensing unit is arranged for acquiring temperature information of the avalanche photodiode;
the main control FPGA unit is used for controlling refrigeration working voltage for the TEC according to the temperature information.
3. The single photon detector apparatus as in claim 2 wherein said temperature sensing unit comprises a thermistor and ADC unit;
the thermistor is arranged to monitor the temperature of the avalanche photodiode;
the ADC unit is used for collecting the voltage division amplitude of the thermistor and sending the voltage division amplitude to the main control FPGA unit.
4. The single photon detector apparatus as in claim 1 wherein said refrigeration cassette comprises a resistor R1, a resistor R2, a capacitor C1 and a first amplifier;
the resistor R1, the avalanche photodiode and the resistor R2 sequentially form a series circuit and are connected with a DC/DC power supply to obtain bias voltage;
the capacitor C1 is arranged to extract the avalanche signal from the series circuit in an ac-coupled manner;
the first amplifier is configured to amplify the avalanche signal output from the capacitor C1 and output the amplified avalanche signal to the discriminator.
5. The single photon detector apparatus as in claim 4 wherein said first amplifier is a low noise amplifier.
6. The single photon detector assembly as in claim 1 further comprising a second amplifier;
the main control FPGA unit is further arranged for generating a dead time control signal based on the detection pulse signal;
the second amplifier is arranged to amplify the dead time control signal and to act on the avalanche photodiode.
7. The single photon detector apparatus as claimed in any one of claims 1-6 wherein said master FPGA unit is configured to measure and obtain time interval data between the detection pulse signal and the TRIG signal using a carry delay chain clock interpolation technique.
8. The single photon detector apparatus as claimed in any one of claims 1 to 6 wherein:
the TRlG signal is externally input; and/or the number of the groups of groups,
the avalanche photodiode is an NFAD device; and/or the number of the groups of groups,
the detection pulse signal has a fixed level; and/or the number of the groups of groups,
the post-pulse probability distribution function is obtained by pre-fitting; and/or the number of the groups of groups,
and the main control FPGA unit and the computing MCU unit are in data communication through a high-speed data interface.
9. The single photon detector apparatus as claimed in any one of claims 1-6 further comprising a data interface for data communication with the outside.
10. The single photon detector apparatus as in claim 9 wherein said data interface is a USB interface.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202320376191.6U CN219574360U (en) | 2023-02-28 | 2023-02-28 | Single photon detector device for laser radar signal real-time post-pulse correction |
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| CN202320376191.6U CN219574360U (en) | 2023-02-28 | 2023-02-28 | Single photon detector device for laser radar signal real-time post-pulse correction |
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