CN219553624U - 功率半导体模块 - Google Patents
功率半导体模块 Download PDFInfo
- Publication number
- CN219553624U CN219553624U CN202190000663.7U CN202190000663U CN219553624U CN 219553624 U CN219553624 U CN 219553624U CN 202190000663 U CN202190000663 U CN 202190000663U CN 219553624 U CN219553624 U CN 219553624U
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- power semiconductor
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 166
- 239000000758 substrate Substances 0.000 claims abstract description 299
- 239000011368 organic material Substances 0.000 claims abstract description 7
- 239000010410 layer Substances 0.000 claims description 137
- 239000004020 conductor Substances 0.000 claims description 36
- 229910052751 metal Inorganic materials 0.000 claims description 24
- 239000002184 metal Substances 0.000 claims description 24
- 238000001465 metallisation Methods 0.000 claims description 23
- 239000000853 adhesive Substances 0.000 claims description 13
- 230000001070 adhesive effect Effects 0.000 claims description 13
- 239000000919 ceramic Substances 0.000 claims description 12
- 239000011888 foil Substances 0.000 claims description 10
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
- 238000005859 coupling reaction Methods 0.000 claims description 8
- 239000012790 adhesive layer Substances 0.000 claims description 3
- 239000002390 adhesive tape Substances 0.000 claims description 3
- 238000000034 method Methods 0.000 description 34
- 239000000463 material Substances 0.000 description 31
- 239000003292 glue Substances 0.000 description 13
- 230000008569 process Effects 0.000 description 12
- 238000004519 manufacturing process Methods 0.000 description 9
- 239000004593 Epoxy Substances 0.000 description 8
- 238000000576 coating method Methods 0.000 description 8
- 239000011248 coating agent Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 239000003365 glass fiber Substances 0.000 description 6
- 238000005245 sintering Methods 0.000 description 6
- 238000011109 contamination Methods 0.000 description 5
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 238000005476 soldering Methods 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 238000004026 adhesive bonding Methods 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000013461 design Methods 0.000 description 3
- 238000004806 packaging method and process Methods 0.000 description 3
- 238000007789 sealing Methods 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 239000002344 surface layer Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000001035 drying Methods 0.000 description 2
- 230000005672 electromagnetic field Effects 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 229920000728 polyester Polymers 0.000 description 2
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 239000011188 CEM-1 Substances 0.000 description 1
- 239000011189 CEM-2 Substances 0.000 description 1
- 239000011190 CEM-3 Substances 0.000 description 1
- 239000011191 CEM-4 Substances 0.000 description 1
- 239000011192 CEM-5 Substances 0.000 description 1
- 101100257127 Caenorhabditis elegans sma-2 gene Proteins 0.000 description 1
- 101100257133 Caenorhabditis elegans sma-3 gene Proteins 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 238000005219 brazing Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000005337 ground glass Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 230000008092 positive effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
- H01L25/072—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00 the devices being arranged next to each other
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- H—ELECTRICITY
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- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5385—Assembly of a plurality of insulating substrates
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- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5386—Geometry or layout of the interconnection structure
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- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
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- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/3201—Structure
- H01L2224/32012—Structure relative to the bonding area, e.g. bond pad
- H01L2224/32013—Structure relative to the bonding area, e.g. bond pad the layer connector being larger than the bonding area, e.g. bond pad
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- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
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Abstract
在一个实施例中,功率半导体模块(1)包括:‑主衬底(2),‑多个第一半导体芯片(3),该多个第一半导体芯片安装在主衬底(2)上,以及‑辅助衬底(4),该辅助衬底也安装在主衬底(2)上,辅助衬底(4)包括远离主衬底(2)的顶面(40),其中‑辅助衬底(4)是印刷电路板,该印刷电路板包括至少一个基于有机材料的载体层(41),以及‑辅助衬底(4)为第一半导体芯片(3)提供公共接触平台(44)。
Description
技术领域
提供了一种功率半导体模块。进一步地,还提供了用于制造这种功率半导体模块的方法。
背景技术
文献JP 2209787 A2涉及一种用于制备印刷电路板的方法,其中印刷电路板通过聚酰亚胺树脂层安装到铝块上。
文献CN 203367241 U涉及一种模制功率封装件的结构,其中印刷电路板通过线或含银的粘合膏接合至引线框架。
文献JP 6342986 A2公开了一种具有通过过孔或通孔互连的两个电路层的多层基板,电路层通过绝缘涂层和粘合剂安装到金属底板上。
文献US 2017/0263527 A1涉及一种半导体模块,该半导体模块包括半导体器件;衬底,半导体器件附接在该衬底上;模制外壳,半导体器件和衬底模制在该模制外壳中;至少一个功率端子,该至少一个功率端子部分模制到外壳中并从外壳突出,该功率端子与半导体器件电连接;以及包装电路板,该包装电路板至少部分地模制到外壳中并在衬底的延伸方向上从衬底突出,其中包装电路板包括用于引脚的至少一个插座,该插座经由包装电路板与半导体器件的控制输入电连接。
文献US 2016/0005678 A1公开了一种包括芯片和支撑芯片的支撑元件的电子器件。提供引线以电耦合到芯片的至少一个端子。耦合元件安装到支撑元件的未被芯片占据的自由区域。耦合元件包括导电部分,该导电部分电连接到至少一个引线且电连接到芯片的至少一个端子,以获得电耦合。
文献US 2018/0005926 A1描述了一种半导体器件,该半导体器件包括包含用于接地的第一端子和第二端子的引线框架、覆盖引线框架的密封树脂、作为第二端子的一部分并从密封树脂暴露出来的暴露部分、以及覆盖密封树脂的表面并在暴露部分处接触第二端子的导电材料。
文献JP S63 244747 A描述了一种树脂密封型集成电路器件,该树脂密封型集成电路器件包括构成引线框架的岛和多个混合单元,该多个混合单元与岛一起利用树脂一体密封。该器件具有设计简单和尺寸小的优点,但没有任何质量上的损失。
实用新型内容
要解决的问题是提供可以有效制造的功率半导体模块。
这个目的尤其通过独立权利要求中限定的功率半导体模块和方法来实现。示例性的进一步发展构成了从属权利要求的主题。
例如,功率半导体模块使用印刷电路板(简称为PCB)作为主衬底上的辅助衬底,以便为半导体芯片提供公共接触平台。使用PCB代替例如直接覆铜衬底(简称为DBC衬底)可以降低成本,并且可以获得附加的电路系统方面的灵活性。
在至少一个实施例中,功率半导体模块包括:
-至少一个主衬底,该至少一个主衬底例如是DBC衬底,
-多个第一半导体芯片,该多个第一半导体芯片安装在主衬底上,以及
-至少一个辅助衬底,该至少一个辅助衬底也安装在主衬底上,辅助衬底包括远离主衬底的顶面,
其中辅助衬底是印刷电路板,该印刷电路板包括至少一个基于有机材料的载体层,并且辅助衬底为第一半导体芯片提供公共接触平台,并且例如第一半导体芯片通过如接合线、带、箔和/或夹具的导电装置电连接到辅助衬底。
在至少一个实施例中,功率半导体模块包括:
-至少一个主衬底,该至少一个主衬底例如是DBC衬底,
-至少三个第一半导体芯片,该至少三个第一半导体芯片安装在主衬底上,以及
-至少一个辅助衬底,该至少一个辅助衬底也安装在主衬底上,辅助衬底包括远离主衬底的顶面,
其中辅助衬底是印刷电路板,该印刷电路板包括至少一个基于有机材料的载体层,并且辅助衬底为第一半导体芯片提供公共接触平台,
其中至少一个辅助衬底的顶面包括导体迹线,导体迹线中的每一个导体迹线被分配给第一半导体芯片中的至多两个第一半导体芯片,并且
其中导体迹线具有不同的长度使得补偿功率半导体模块中到第一半导体芯片的、在至少一个辅助衬底上行进的电连接线路的反之则会存在的长度差。
在至少一个实施例中,功率半导体模块包括:
-至少一个主衬底,该至少一个主衬底例如是DBC衬底,
-多个第一半导体芯片,该多个第一半导体芯片安装在主衬底上,以及
-至少一个辅助衬底,该至少一个辅助衬底也安装在主衬底上,辅助衬底包括远离主衬底的顶面,
其中辅助衬底是印刷电路板,该印刷电路板包括至少一个基于有机材料的载体层,并且辅助衬底为第一半导体芯片提供公共接触平台,
其中至少一个辅助衬底的导体迹线至少部分地电平行或反平行行进,并且
其中,如在顶面的俯视图中所见,第一半导体芯片沿着辅助衬底的两侧布置,或者第一半导体芯片沿着辅助衬底中的至少一个辅助衬底的两侧布置,使得各个辅助衬底位于第一半导体芯片之间。
例如,术语“功率半导体模块”意味着该模块被配置用于高电流。例如,功率半导体模块被配置为处理至少10A或至少50A或至少100A或至少500A的最大电流。相应地,第一半导体芯片可以是高功率部件。
例如,用于PCB的载体层的纤维增强有机材料例如从以下群组中进行选择:聚四氟乙烯(PTFE)、FR-2(酚醛棉纸)、FR-3(棉纸和环氧树脂)、FR-4(玻璃纤维和环氧树脂)、FR-5(玻璃纤维和环氧树脂)、FR-6(磨砂玻璃和聚酯)、G-10(玻璃纤维和环氧树脂)、CEM-1(棉纸和环氧树脂)、CEM-2(棉纸和环氧树脂)、CEM-3(玻璃纤维和环氧树脂)、CEM-4(玻璃纤维和环氧树脂)、CEM-5(玻璃纤维和聚酯)。因此,可以实现经济高效的辅助衬底。
根据至少一个实施例,辅助衬底通过一个接合层或者通过多个接合层附接到主衬底。至少一个接合层位于主衬底的面向辅助衬底的底侧处。例如,至少一个接合层是没有任何孔或凹陷部或切口的连续层。例如,接合层延伸到辅助衬底和主衬底之间的至少80%或90%或在其间完全延伸。借助于这种接合层,可以容易地将辅助衬底施加到主衬底上。作为可替代方案,接合层可以具有结构化部,以实现例如多个电接触或改善对主衬底的粘附。
根据至少一个实施例,至少一个接合层包括有机粘合剂层或由有机粘合剂层组成。例如,有机粘合剂层包括或由至少一种环氧树脂和/或至少一种聚合物组成。通过使用有机粘合剂,可以降低安装辅助衬底时对主衬底的温度负载。
根据至少一个实施例,接合层包括至少一个金属层或由至少一个金属层组成。该至少一个金属层可以通过焊料层和/或烧结层来实现。可以存在分别提高接合层和辅助衬底或主衬底之间的粘附性的、邻接接合层的附加的金属层,如扩散阻挡层或类似的接触层。也就是说,辅助衬底可以包括背侧金属化部,接合层施加在该背侧金属化部上。使用至少一个金属层可以在辅助衬底和主衬底之间提供低热阻。
根据至少一个实施例,辅助衬底的顶面包括金属层或由金属层组成。例如,所述金属层被配置用于线结合,例如利用铝或铜制成的线结合件。作为线结合部的可替代方案,也可以使用带、箔或夹具等。金属层可以是连续的平坦层。除了电连接装置之外(也就是说,除了线结合部、带、箔或夹具等之外),金属层可以是顶面上的唯一部件。
根据至少一个实施例,辅助衬底和主衬底之间的电连接也通过至少一个电连接装置(如结合线、带、箔或夹具)建立,例如通过多个电连接装置建立。至少一个电连接装置可以从主衬底行进到辅助衬底的顶面,或者行进到安装在顶面上的电子部件。
根据至少一个实施例,第一半导体芯片并联或反并联地电接触。因此,辅助衬底可以用作用于第一半导体芯片中的一些第一半导体芯片或用于的第一半导体芯片中的全部第一半导体芯片的公共接触平台。
根据至少一个实施例,功率半导体模块还包括至少一个第二半导体芯片。第二半导体芯片或多个第二半导体芯片不与辅助衬底电连接,或者至多间接地与辅助衬底电连接。
根据至少一个实施例,公共接触平台是用于第一半导体芯片的栅极接触件。因此,控制第一半导体芯片可以通过辅助衬底来实现。因此,辅助衬底例如用于各个第一半导体芯片的栅极的互连,而不是用于功率电路。此外,辅助衬底还可以用于其他辅助连接,如辅助发射极、集电极接触件或漏极/源极接触件,或者用于另外的电气部件(如传感器)的互连。
根据至少一个实施例,功率半导体模块包括辅助衬底中的至少两个辅助衬底。全部辅助衬底可以具有相同形式,或者存在不同构造的辅助衬底。
根据至少一个实施例,第一半导体芯片中的一些第一半导体芯片与辅助衬底中的第一辅助衬底电连接,并且第一半导体芯片中的一些其他第一半导体芯片与辅助衬底中的第二辅助衬底电连接。因此,第一半导体芯片被分配给不同的接触平台,例如用于不同的栅极接触件。
根据至少一个实施例,第一半导体芯片和/或至少一个第二半导体芯片从包括以下或由以下组成的群组中进行选择:金属氧化物半导体场效应晶体管(MOSFET)、金属绝缘体半导体场效应晶体管(MISFET)、绝缘栅双极晶体管(IGBT)、双极结型晶体管(BJT)、晶闸管、门极关断晶闸管(GTO)、门极换向晶闸管(GCT)和面结型栅场效应晶体管(junctiongate field-effect transistor,JFET)。所有第一和/或第二半导体芯片可以具有相同类型,或者存在不同种类的第一半导体芯片和/或第二半导体芯片。
根据至少一个实施例,主衬底是直接覆铜衬底,其包括中心陶瓷层和在陶瓷层的每个主侧上的至少一个金属化部。作为可替代方案,主衬底是活性金属钎焊衬底,简称为AMB衬底。因此,主衬底可以被有效地被配置用于高电气负载。
根据至少一个实施例,辅助衬底包括多个电阻器。例如,电阻器中的每个电阻器被分配给第一半导体芯片中的至多两个第一半导体芯片。例如,电阻器中的每个电阻器被分配给第一半导体芯片中的确切一个第一半导体芯片。例如,在用于至少一个第二半导体芯片的辅助衬底上没有电阻器。
根据至少一个实施例,电阻器是安装在辅助衬底的顶面上的电气器件。因此,电阻器可以通过例如焊接或烧结施加到顶面,或者也可以通过导电粘合剂连接。
根据至少一个实施例,电阻器是形成在辅助衬底的顶面中或内部中的结构。也就是说,电阻器和辅助衬底形成为单件。例如,电阻器被实现为薄的导体迹线或实现为导体迹线中的收缩部。这种导体迹线可以以曲折的方式成形。
根据至少一个实施例,功率半导体模块包括第一半导体芯片中的至少三个或至少四个第一半导体芯片,辅助衬底为其提供公共接触平台。可选地,存在至少八个或至少十个第一半导体芯片。可替代地或附加地,第一半导体芯片的数量最多为50或最多为30或最多为15。关于这些数字,同样可以应用于第二半导体芯片。
根据至少一个实施例,辅助衬底的顶面包括导体迹线。这些导体迹线中的每个导体迹线例如被分配给第一半导体芯片中的至多两个或至多四个第一半导体芯片。例如,在这些导体迹线和第一半导体芯片之间存在一对一的分配,使得分离的导体迹线可以被分配给各个单独的第一半导体芯片。
根据至少一个实施例,导体迹线中的至少一些或全部导体迹线具有相同的长度,无论导体迹线的开始和结束位置如何。因此,可以避免的是通过辅助衬底本身引入电气路径长度差。
根据至少一个实施例,分配给第一半导体芯片的导体迹线在辅助衬底上具有不同的长度。通过具有不同的长度,可以补偿功率半导体模块中到第一半导体芯片并且在辅助衬底上行进的电连接线路的反之则会存在的长度差。
根据至少一个实施例,辅助衬底的至少一些导体迹线至少部分地平行或反平行行进。因此,可以建立平行或反平行信号路径,从而可以减少电磁耦合。
根据至少一个实施例,如在顶面的俯视图中所见,第一半导体芯片沿着辅助衬底的两侧布置,使得辅助衬底位于第一半导体芯片之间。辅助衬底可以是关于第一半导体芯片的布置的对称线。顶面上用于第一半导体芯片的电接触件也可以以对称的方式布置。如果存在多个辅助衬底,这可以适用于辅助衬底中的一个辅助衬底或辅助衬底中的多于一个辅助衬底。
根据至少一个实施例,辅助衬底是多层衬底。也就是说,存在与金属层类似的至少两个导电层。例如,存在远离顶面的至少一个内部导电层,和/或在辅助衬底的底侧存在至少一个导电层。例如,在顶面处存在一个导电层,在底面处存在一个导电层,以及存在一个或多于一个中间的内部导电层。
根据至少一个实施例,辅助衬底的导体迹线中的至少两个或全部导体迹线被形成为部分翻转迹线。通过这种布置,可以减少电磁耦合。因此,各个导体迹线不限于顶面,而是位于主衬底上方的不同层面。
根据至少一个实施例,至少一个内部导电层被配置为电屏蔽层。因此,可以至少在某种程度上保护顶面处的电子部件免受由主衬底上的大电流产生的电磁场的影响。内部导电层或内部导电层中的至少一个内部导电层也可以被结构化以形成附加导体迹线。
例如,只有主衬底而不是辅助衬底被配置用于大电流。例如,辅助衬底被配置用于5A或更小、或2A或更小、或1A或更小的最大电流。
根据至少一个实施例,辅助衬底设置有至少两种不同种类的电气器件。这些电气器件例如是电阻器或集成电路(IC)或传感器(如负温度系数(NTC)热敏电阻器或正温度系数(PTC)热敏电阻器中的至少一种。
功率半导体模块例如是车辆中的功率模块,该功率模块用于将来自电池的直流电转换成用于(例如在混合动力车辆或插电式电动车辆中)电动机的交流电。
附加地提供了一种用于制造功率半导体模块的方法。借助于该方法,如结合上述实施例中的至少一个实施例所示,生产功率半导体模块。因此,对于该方法也公开了功率半导体模块的特征,反之亦然。
在至少一个实施例中,该方法用于制造功率半导体模块,并且包括:
A)提供主衬底,
B)将辅助衬底安装到主衬底上,
其中所述辅助衬底包括预施加的主材料层,该主材料层在方法步骤B)中形成接合层。
也就是说,在方法步骤B)中,至少一个预施加的主材料层变成至少一个接合层。如果存在多个预施加的主材料层,所有这些层可以变成一个接合层。在方法步骤B)中,主材料层可以经历化学反应或干燥步骤,或者可以可替代地在其材料组成和/或其形状方面保持不变或基本不变。
在步骤B)之前,作为可替代方案,主材料层可以是均质层或者可以具有图案,以实现例如改进的附接过程和/或对主衬底的粘附性。
根据至少一个实施例,在方法步骤B)之前,主衬底没有任何主材料层或接合层,这些主材料层或接合层被配置用于安装辅助衬底。因此,在方法步骤B)之前,在辅助衬底的随后位置,在主衬底处,例如仅存在主衬底处的金属化部的空的空白表面部分。
根据至少一个实施例,主材料层是在方法步骤B)之前涂覆到辅助衬底的底侧上的胶。当将辅助衬底安装到主衬底时,胶可以被预固化或者可以具有薄的凝固表层,以防止主衬底在不期望的位置被胶污染。
根据至少一个实施例,主材料层是施加在辅助衬底的底侧上的粘性箔。因此,主材料层可以是固体或基本上固体的部件。
根据至少一个实施例,主材料层是施加在辅助衬底的底侧上的双面粘合带。例如,在方法步骤B)之前,主材料层在远离顶面的侧部上包括剥离涂层。因此,可以实现在方法步骤B)之前的主材料层的较长的寿命。
附图说明
下面参照附图通过示例性实施例更详细地解释本文描述的功率半导体模块和方法。各个图中相同的元件以相同的附图标记表示。然而,没有按比例示出元件之间的关系,而是可能放大示出各个元件以帮助理解。
在附图中:
图1是功率半导体模块的修改的示意性截面图,
图2是本文描述的功率半导体模块的示例性实施例的示意性截面图,
图3是本文描述的功率半导体模块的示例性实施例的示意性俯视图,
图4是用于本文描述的功率半导体模块的示例性实施例的辅助衬底的示意性截面图,
图5至图7是用于本文描述的功率半导体模块的示例性实施例的辅助衬底的示意性俯视图,
图8是用于本文描述的功率半导体模块的示例性实施例的辅助衬底的示意性透视图,
图9是用于制造本文描述的功率半导体模块的方法的示例性实施例的示意性框图,
图10至图14是用于本文描述的功率半导体模块的示例性实施例的辅助衬底的示意性侧视图,以及
图15是本文描述的功率半导体模块的示例性实施例的示意性截面图。
具体实施方式
图1示出了改进的功率半导体模块10。模块10包括主衬底2和另外的衬底9。两个衬底2、9是DBC衬底。另外的衬底9通过接合层5连接到主衬底2,该接合层可以是焊料层。
主衬底2包括对应于另外的衬底9的陶瓷层91的中心陶瓷层21。在中心陶瓷层21、91的两侧上具有金属化部22。通过结合线24实现另外的衬底9的顶面40和主衬底2上的第一半导体芯片3之间的电连接。因为图1是截面图,所以只能看到多个第一半导体芯片3中的一个第一半导体芯片。
在功率半导体模块中,开关器件即第一半导体芯片3的操作由栅极信号控制。因此,全部开关器件的栅极接触件必须与功率模块的外部栅极端子互连。每个开关器件应该具有由另外的衬底9提供的其自己的栅极的互连。附加地,由于电磁耦合引起的栅极信号的延迟对于全部第一半导体芯片3应该是均匀的,以提供同步的开关。
所有第一半导体芯片3的栅极的互连,即结合线连接,消耗了主衬底2的大量空间来为栅极或控制电路提供金属化图案,例如在功率模块中,其中许多第一半导体芯片3安装在主衬底2上,如同在具有宽带隙器件的功率模块中一样。更重要的是,在功率MOSFET或IGBT的情况下,当另外的衬底9分别安装在源极或发射极/源极的电路图案的顶部上时,具有衬底2、9的两层设计允许快速和清晰的开关。
此外,这种空间需求增加了衬底的大小,导致衬底的成本增加并因此导致功率模块的成本增加。例如,功率模块可以包含多达20个SiC功率MOSFET器件作为第一半导体芯片3,其因此总共需要20个栅极互连。
这些另外的衬底9通常是包括顶侧和背侧上的电绝缘陶瓷层21和金属化部22或由顶侧和背侧上的电绝缘陶瓷层和金属化部组成的DBC衬底(DBC:direct bonded copper,直接覆铜)。通过胶合、烧结或焊接将另外的衬底9接合到主衬底2。因此,需要附加的接合工艺来将另外的衬底9附接到主衬底2。栅极电阻器也可以安装在另外的衬底9上(图1中未示出)。
然而,使用接合到主衬底2的金属化图案的基于DBC的另外的衬底9具有一些缺点:
-基于电绝缘陶瓷片材的DBC衬底导致高成本。因此,即使是基于相对便宜的氧化铝陶瓷的小型DBC衬底也具有大约1CHF的价格。而且,小型DCB的制造在供应商方面具有挑战性,并且通常与低产量相关。
-低成本区域中的DBC衬底在金属化图案中没有结构。那么只有用于控制电路的同质单层金属化部是可用的。因此,例如由于不可能在DBC衬底上制备单独的较小尺寸的导体迹线,所以不可能对用于改善电磁行为的控制电路进行特定布局。
-需要利用热冲击的粘合、焊接或烧结的单独接合工艺将另外的衬底9接合到主衬底2。
-需要投资胶合机器和工具。
-不能排除在接合工艺期间,与另外的衬底9的接合连接相邻的主衬底2的功率电路金属化部的区域的污染。这可能导致线结合连接的不良处理能力,或者导致需要用于适当处理的安全空间。
因此,使用通过胶合、焊接或烧结安装到主衬底2的基于DBC的另外的衬底9具有一些缺点。可以通过使用由印刷电路板(PCB)技术制成的辅助衬底4来克服这些缺点,这将为低压电路系统提供廉价且可靠的技术。
参见图2,在本功率半导体模块1中,由直接覆铜制成的图1的另外的衬底9被由小印刷电路板制成的辅助衬底4代替,以提供第一半导体芯片3的栅极接触件的互连。
在简单的情况下,印刷电路板仅具有在顶面40上的金属层42和在底侧49处的可选底部金属化金属层,但是为了改善控制电路系统(例如关于电磁行为),使用多层PCB也是可能的。类似于DBC衬底,通过较厚的铝或铜结合线24实现线结合连接是可能的。可选地,栅极电阻器可以安装在印刷电路板的顶面40(图2中未示出)上。
为了附接,例如由胶或粘合箔制成的接合层5可以直接施加在电源侧上的印刷电路板的底侧49上。因此,辅助衬底4可以通过简单的拾取和放置过程直接附接到主衬底2的金属化图案,而没有强烈的热冲击。因此,减少了由于接合工艺引起的污染对接合层5的周围的影响。基于印刷电路板技术的辅助衬底4可以用于所有类型的功率模块(如凝胶填充功率模块或模制功率模块)以及技术(如Si IGBT或宽带隙器件)。
实现基于印刷电路板技术而不是DBC衬底的辅助衬底4提供了一些商业益处,例如:
-印刷电路板的材料价格远低于DBC衬底。基于PCB的辅助衬底4具有约0.05CHF/片的价格,而相对应的DBC衬底的价格为1.00CHF/片左右。
-还提供了制造成本的降低。使用具有预施加的粘合剂的PCB辅助衬底4仅需要简单的拾取和放置过程。一方面,减少了用于将辅助衬底4接合到主衬底2的制造时间和过程步骤的数量。另一方面,由于不需要附加接合材料,实现了进一步的成本降低。
-由于减少的周围区域污染,改善了后续线结合工艺的工艺能力,同时降低了产量的损失。
-印刷电路板的使用带来了改善辅助衬底4上的辅助电路系统的电磁行为的机会,从而使得第一半导体芯片3的开关行为有所改善并且更加均匀,以及因此产生更好的模块性能和寿命。实际上,可以通过具有辅助衬底4改善整个电路系统的电磁行为。
然而,应该考虑到,基于PCB技术的辅助衬底4的积极效果对于其中较大数量的第一半导体芯片3安装在主衬底2上的功率半导体模块1来说更为显著,如在汽车分支中的宽带隙产品中的情况,其中例如多达20个SiC MOSFET安装到主衬底2上,该主衬底可以具有大约60×60mm2的侧向尺寸。
当使用印刷电路板作为辅助衬底4时,烧结或焊接也可以用于将辅助衬底4接合到主衬底2。在此,焊接材料或烧结材料例如被预施加到底侧49。然后,可以通过热辅助拾取和放置过程来完成接合工艺。如图2中所使用的那样,用于辅助衬底4上的互连的线结合的可能方案是例如带、箔或夹具。附加地或可替代地,辅助端子可以直接接合到辅助衬底4的顶面40。对于所有其他示例性实施例也是如此。
图3示出了功率半导体模块1,其包括16个功率MOSFFET器件(即,例如八个第一半导体芯片3和八个第二半导体芯片7)。第一和第二半导体芯片3、7可以是相同类型。第一半导体芯片3被布置成与辅助衬底4相邻的两行,其中如在顶视图中所见,辅助衬底4是关于半导体芯片3、7的对称线。只有第一半导体芯片3通过结合线24电连接到辅助衬底4。代替结合线24,也可以使用其他电连接装置,如带、箔或夹具。对于全部其他示例性实施例也是如此。
基于PCB的辅助衬底4可以安装在主衬底2的金属化22中形成的导体路径26上。第一半导体芯片3直接电连接到所述金属化部22和辅助衬底4的顶面40两者。然而,在所述金属化22和顶面40之间没有直接的电连接。也就是说,存在两个不同且分离的电路系统,一个在辅助衬底4上,另一个在主衬底2上。
此外,存在附加结合线24,该附加结合线到主衬底2到顶面40的至少一个其他导体路径26,使得顶面40可以用作所有第一半导体芯片3的公共栅极接触件。因此,第一电连接装置直接从主衬底2行进到辅助衬底4,例如,从主衬底2的辅助图案延伸到远离第一半导体芯片和第二半导体芯片3、7的辅助衬底4,而其他第二电连接装置直接从第一半导体芯片3行进到辅助衬底4。这同样适用于全部其他示例性实施例。
在顶面40上,存在电阻器6。电阻器6具有与金属层42的直接电接触,以及通过结合线24与第一半导体芯片3的直接电接触。例如,每个第一半导体芯片3与其自己的电阻器6接触。为了补偿不同的电气路径长度,电阻器6可以具有稍微不同的电阻,例如在从1Ω至10Ω的范围内。这同样适用于全部其他示例性实施例。第二半导体芯片7例如电连接到附加电气器件27,该附加电气器件也可以是电阻器;因此,与电阻器6相同的情况适用于附加电气器件27。
在图4中,更详细地示出了辅助衬底4的示例性实施例。所述辅助衬底4可以用在全部示例性实施例中。辅助衬底4为多层形式,并且除了顶面40处的金属层42之外包括内部导电层45。可能的是存在用于互连层42、45的通孔48。然而,例如,存在至少一个未连接到顶面40的内部导电层45。这种层45可以提供一些对电磁场的屏蔽,并减小辅助衬底4上的栅极信号和主衬底2上的发射极/源极电流之间的寄生电感。
进一步,作为可选项,存在底部金属化层49。这个层49可以完全或基本上完全被接合层5覆盖。
像在全部其他示例性实施例中一样,单独地或一起地,可以应用以下内容:辅助衬底4的厚度为例如至少0.2mm,至多3mm。可替代地或附加地,如在顶面40的俯视图中所见,辅助衬底4的测向尺寸可以至少为1mm×20mm和/或至多为15mm×150mm。而且,金属层42、45、49的厚度为例如至少20μm或80μm和/或最多0.3mm或0.1mm。与此相反,主衬底2的金属化部22的厚度例如为至少0.1mm和/或最多1mm。接合层5的厚度例如至少10μm或30μm和/或最多0.3mm或0.1mm。
在图5至图8中,焦点在辅助衬底4的顶面40处的电气电路系统上。这些方面可以单独或共同应用于全部其他示例性实施例。图5至图8中未提及的方面可以类似于其他示例性实施例中实现。
根据图5,顶面40处的金属层被成形为导体迹线46。导体迹线46中的至少一些导体迹线具有相同的长度以避免由于辅助衬底4导致的电气路径长度差。因此,用于结合线等的接触区域43可以位于顶面40的端部处,但是类似于电阻器6的全部电气器件以相同的电气路径长度连接。也就是说,当使用数个导电迹线46时,可以单独调节与每个第一半导体芯片3相关的信号路径的长度,以实现在全部电并联器件的开关方面的改进的均匀性。
此外,对照图5,通过提供平行或反平行信号路径的迹线布局,也可以降低栅极信号的电气路径的寄生电感。
在图5中,电阻器6由安装在顶面40上的分离的器件实现。与此相反,参见图6,可以通过导电迹线的相对应的布局来制备电阻器6。这有助于替换栅极电阻器,同时相对节省成本。附加地,通过迹线布局制备的电阻器给出了实现对于每个芯片具有最佳电阻的栅极电阻器的选择,从而有助于开关方面的更高的均匀性。
参见图6,可以存在用于电阻器6的单独的接触区域43,或者如图5所示,可以只有用于全部电阻器6的一个公共接触区域43。这两种变型原则上都可以应用于全部示例性实施例。
根据图7,除了作为第一种类的电气器件的电阻器6之外,还存在至少一个传感器芯片作为第二种类的电气器件61。作为可选项,可以存在另外类型62的电气器件,如IC。可能的是,器件6、61、62通过接触区域43直接电连接到顶面40、和/或器件6、61、62通过结合线24连接。
因此,使用带有迹线的印刷电路板有助于另外的功能(如辅助发射极/源极和辅助集电极或用于集成传感器(如热敏电阻)的互连的电气路径)的集成。附加地,在智能功率半导体模块1的情况下,迹线可以用于多个信号路径。
在全部图5至图7中,辅助衬底4和主衬底2之间的电互连可以可替代地或附加地由带、箔或夹具代替结合线来提供。
在用于辅助衬底4的多层PCB的情况下,对照图8,例如,可以通过部分翻转栅极和发射极/源极迹线实现栅极和辅助发射极/源极的改进的耦合。因此,导体迹线46a、46b可以均在辅助衬底4中/辅助衬底4处的两个不同层面处行进,并且相应的导体迹线46a、46b的不同部分可以通过过孔48连接。在图8中,仅示出了两对导体迹线46a、46b,但是当然可以存在更多的导体迹线,例如,如图5至图7所示。
图9示出了制造功率半导体模块1的方法的框图。在方法步骤S1中,提供第一衬底2。
在可选的方法步骤S2中,第一和/或第二半导体芯片3、7安装在主衬底2上。
根据方法步骤S3,辅助衬底4附接到主衬底2。辅助衬底4与主衬底2的接合例如通过拾取和放置过程来完成,该过程可选地是热和/或压力辅助的。
最后,在方法步骤S4中,完成布线。
在图10至图14中,示出了将辅助衬底4安装到主衬底2上的一些可能性。这些图示出了在方法步骤S3之前的情况,即在安装辅助衬底4之前的情况。
根据图10,当辅助衬底4设置在主衬底2上时,存在主材料层50,该主材料层随后形成接合层5。在图10的示例性实施例中,主材料层50是有机粘合剂51层。有机粘合剂51例如是固体。主材料层50可以覆盖整个或基本上整个底侧49。例如,主材料层50是平面平行形式。当将辅助衬底4施加到主衬底2上时(图10中未示出),主材料层50例如被压到主衬底2上,使得主材料层50然后构成接合层5。
在图11中,主材料层50是施加到辅助衬底4上的胶54。胶54具有恒定或近似恒定的厚度,例如0.1mm。胶54例如处于粘性状态。作为选项,为了避免胶水54污染主衬底2,可以存在已经干燥的胶水54的薄表层56。当将辅助衬底4压到主衬底2时,该表层56被破坏。而且,胶54可以仅部分覆盖底侧49,从而存在没有胶54的边缘区域。作为可选项,存在底部金属化层47。
类似于图10,主材料层50可以被热固化或者在施加到主衬底2上之后通过干燥来固化,或者根本不需要特定的固化步骤。
根据图12,主材料层50包括粘合剂51和两个剥离涂层55、57。因此,主材料层50是双面粘合带。在将粘合剂51安装到辅助衬底4上时,面向辅助衬底4的内部剥离涂层57被剥离,而外部剥离涂层57在刚在辅助衬底4安装到主衬底2上时之后被去除。当主材料层50被施加在辅助衬底4上并且仅存在远离顶面40的剥离涂层55时,辅助衬底4可以在被安装到主衬底2上之前被存储持续一些时间。
在图13中,示出了主材料层50是预施加的焊料层52。
作为可选项,在底侧49处可以存在单独的接触区域,使得底部金属化层47可以结构化方式形成。此外,可以存在朝向顶面40的过孔48。因此,可以省略线结合。如果图10至图12中的粘合剂51或胶54是导电的,例如,如果导电颗粒包含在有机基质材料中,则这种结构化底部金属化层47也可以用于这些示例性实施例中。
根据图14,主材料层50是预施加的烧结层53。也就是说,当被加热时,烧结层53与主衬底2连接并形成接合层5,例如利用压力和/或升高的温度。对于其余部分,与图13相同的情况也适用于图14。
在图15中,示出了功率半导体模块1的另一示例性实施例。在这种情况下,存在多于一个辅助衬底4,例如三个辅助衬底4。因此,与图3相比,通过添加两个最外面的附加辅助衬底4,图3的第二半导体芯片7变成了图15中的第一半导体芯片4。所有辅助衬底4可以具有相同的设计,尽管不同数量的第一半导体芯片3可以被分配给辅助衬底4。这同样适用于所有其他示例性实施例。
此外,在图15中示出了顶面40在每种情况下仅由相应的金属层42形成。金属层42可以是连续平面形式,但是作为替代方案,也可以被结构化成包括接触区域和/或导体迹线,如图5至图8所示。因此,例如,与图3中所示的情况相反,在顶面40上没有电阻器或其他电气器件。这同样适用于全部其他示例性实施例。
除此之外,与图3相同的情况也适用于图15。
在此描述的本发明不受参考示例性实施例给出的描述限制。相反,本发明涵盖任何新颖特征和特征的任何组合,特别地包括权利要求中的特征的任何组合,即使没有在权利要求或示例性实施例中明确指示这个特征或这个组合本身。
本专利申请要求欧洲专利申请20193107.8的优先权,其公开内容通过引用结合于此。
附图标记列表
1 功率半导体模块
2 主衬底
21 陶瓷层
22 金属化部
24 结合线
25 端子
26接触表面/导体路径
27 附加电气器件
3 第一半导体芯片
4 辅助衬底
40 顶面
41 基于有机材料的载体层
42 金属层
43 接触区域
44 公共接触平台
45 内部导电层
46、46A、46b导体迹线
47 底部金属化层
48 过孔
49 底侧
5 接合层
50 主材料层
51 有机粘合剂
52 焊料层
53 烧结层
54 胶
55 外部剥离涂层
56 表层
57 内部剥离涂层
6电阻器,第一种类的电气器件
61传感器芯片,第二类型的电气器件
62IC,另外类型的电气器件
7 第二半导体芯片
9 其他衬底
91 陶瓷层
10 改进的功率半导体模块
S 方法步骤
Claims (13)
1.一种功率半导体模块(1),其特征在于,包括:
-至少一个主衬底(2),
-多个第一半导体芯片(3),所述多个第一半导体芯片安装在所述主衬底(2)上,以及
-至少一个辅助衬底(4),所述至少一个辅助衬底也安装在所述主衬底(2)上,所述至少一个辅助衬底(4)包括远离所述主衬底(2)的顶面(40),其中
-所述至少一个辅助衬底(4)是印刷电路板,所述印刷电路板包括至少一个基于有机材料的载体层(41),以及
-所述至少一个辅助衬底(4)为所述第一半导体芯片(3)中的至少一些第一半导体芯片提供公共接触平台(44),
其中所述至少一个辅助衬底(4)通过接合层(5)被附接到所述主衬底(2),所述接合层(5)位于所述至少一个辅助衬底(4)的面向所述主衬底(2)的底侧(49)处,所述接合层(5)包括连续有机粘合剂层(51)或由所述连续有机粘合剂层组成,并且所述接合层(51)是粘合箔或双面粘合带。
2.根据权利要求1所述的功率半导体模块(1),其特征在于:
所述功率半导体模块(1)被配置成处理至少10A的最大电流。
3.根据权利要求1或2所述的功率半导体模块(1),其特征在于:
所述公共接触平台(44)是用于所述第一半导体芯片(3)的栅极接触件。
4.根据权利要求1或2所述的功率半导体模块(1),其特征在于:
所述至少一个辅助衬底(4)的所述顶面(40)包括金属层(42),并且建立所述金属层(42)和所述主衬底(2)之间的直接电连接,并且所述第一半导体芯片(3)中的至少一些第一半导体芯片直接电接触到所述金属层(42),其中所述第一半导体芯片(3)并联电连接。
5.根据权利要求1或2所述的功率半导体模块(1),其特征在于:
还包括也安装在所述主衬底(2)上的第二半导体芯片(7),其中
-所述第二半导体芯片(7)与所述至少一个辅助衬底(4)电分离,所述第一半导体芯片(3)和所述第二半导体芯片(7)从由MOSFET、MISFET、IGBT、BJT、晶闸管、GTO、GCT和JFET组成的群组中进行选择,和/或
-所述主衬底(2)是直接覆铜衬底,所述直接覆铜衬底包括中心陶瓷层(21)和在所述陶瓷层(21)的每个主侧上的至少一个金属化部(22)。
6.根据权利要求1或2所述的功率半导体模块(1),其特征在于:
包括至少两个辅助衬底(4),
其中所述第一半导体芯片(3)中的一些第一半导体芯片与所述辅助衬底(4)中的第一辅助衬底电接触,而所述第一半导体芯片(3)中的一些其他第一半导体芯片与所述辅助衬底(4)中的第二辅助衬底电接触。
7.根据权利要求1或2所述的功率半导体模块(1),其特征在于:
所述至少一个辅助衬底(4)包括多个电阻器(6),所述电阻器(6)中的每一个被分配给所述第一半导体芯片(3)中的至多两个第一半导体芯片。
8.根据权利要求7所述的功率半导体模块(1),其特征在于:
所述电阻器(6)是安装在所述至少一个辅助衬底(4)的所述顶面(40)上的电气器件。
9.根据权利要求7所述的功率半导体模块(1),其特征在于:
所述电阻器(6)是在所述至少一个辅助衬底(4)的所述顶面(40)中或者在内部中形成的结构。
10.根据权利要求1或2所述的功率半导体模块(1),其特征在于:
包括至少三个第一半导体芯片(3),所述至少一个辅助衬底(4)为所述至少三个第一半导体芯片提供所述公共接触平台(44),
其中所述至少一个辅助衬底(4)的所述顶面(40)包括导体迹线(46),所述导体迹线(46)中的每个导体迹线被分配给所述第一半导体芯片(3)中的至多两个第一半导体芯片,并且
其中所述导体迹线(46)具有不同的长度,从而补偿所述功率半导体模块(1)中到所述第一半导体芯片(3)的、在所述至少一个辅助衬底(4)上行进的电连接线路的反之则会存在的长度差。
11.根据权利要求10所述的功率半导体模块(1),其特征在于:
所述至少一个辅助衬底(4)的导体迹线(46,46a,46b)至少部分地平行或反平行电行进,并且
在所述顶面(40)的俯视图中,所述第一半导体芯片(3)沿着所述辅助衬底(4)的两侧布置,或者所述第一半导体芯片(3)沿着所述辅助衬底(4)中的至少一个辅助衬底的两侧布置,使得所述各个辅助衬底(4)位于所述第一半导体芯片(3)之间。
12.根据权利要求11所述的功率半导体模块(1),其特征在于:
所述至少一个辅助衬底(4)是多层衬底,
所述至少一个辅助衬底(4)包括内部导电层(45),所述内部导电层(45)被配置为电屏蔽层和/或所述至少一个辅助衬底(4)的所述导体迹线(46,46a,46b)被形成为部分翻转迹线,以减少电磁耦合。
13.根据权利要求1至2、8至9以及11至12中任一项所述的功率半导体模块(1),其特征在于:
所述至少一个辅助衬底(4)设置有至少两种不同类型的电气器件和/或半导体芯片(6,61,62)。
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