CN219533294U - Power line conduction sensitivity test circuit and device - Google Patents

Abstract

The utility model discloses a power line conduction sensitivity test circuit which comprises a pulse source signal output circuit, tested equipment EUT and an auxiliary power supply V6, wherein a first wiring terminal and a second wiring terminal are arranged on the pulse source signal output circuit, a first inductor L2 is arranged between the first wiring terminal and the second wiring terminal, the first wiring terminal is connected with a first capacitor C2, and when a series injection mode test is carried out, the tested equipment EUT, the auxiliary power supply V6 and the first inductor L2 are connected in series; when the parallel injection mode test is performed, the first inductor L2 and the first capacitor C2 are connected in series and then connected in parallel with the tested device EUT and the auxiliary power supply V6. The test circuit can also ensure the safety and the precision of a test without using a coupling transformer, can effectively reduce the cost, reduce wiring in the test process, is convenient to operate, and can greatly improve the test efficiency.

Description

Power line conduction sensitivity test circuit and device

Technical Field

The utility model relates to the technical field of electromagnetic compatibility testing, in particular to a power line conduction sensitivity testing circuit and a testing device adopting the same.

Background

The purpose of the power line conducted sensitivity test is to verify the ability of the device under test EUT to withstand signals coupled to the input power line, ensuring that the device performance is not degraded under pulsating voltage conditions that allow the power supply voltage waveform to be distorted. In the CS106 test configuration diagram specified in GJB151B-2013, as shown in fig. 1, the power supply first passes through a Linear Impedance Stabilizing Network (LISN) to isolate power supply interference and provide standardized power supply impedance for the tested Equipment (EUT), so as to ensure consistency of test results of different test mechanisms, a coupling transformer is used as a test disturbance signal coupling device and connected in series with a high potential line of the EUT, a primary end of the coupling transformer is connected with a disturbance signal generating system, a secondary end of the coupling transformer is connected to an EUT power supply loop, the generated test disturbance signal is coupled to the EUT power supply loop through an electromagnetic induction principle of the coupling transformer, and an oscilloscope is used as a monitoring device to monitor whether the intensity of the disturbance signal meets the standard requirement.

This kind of test circuit needs to set up the coupling transformer, because transformer itself is bulky, and installation, use are all inconvenient, influence test efficiency, use cost is higher moreover, consequently can not satisfy actual production demand more and more, and the purpose of this patent is just to improving current power cord conduction sensitivity test circuit, designs a simple structure, convenient to use's power cord conduction sensitivity test circuit.

Disclosure of Invention

In order to overcome the defects in the prior art, the utility model aims to develop a power line conduction sensitivity testing circuit which is simple in mechanism and convenient to use.

The power line conduction sensitivity test circuit comprises a pulse source signal output circuit, tested equipment EUT and an auxiliary power supply V6, wherein a first wiring terminal and a second wiring terminal are arranged on the pulse source signal output circuit, a first inductor L2 is arranged between the first wiring terminal and the second wiring terminal, the first wiring terminal is connected with a first capacitor C2, and when a series injection mode test is carried out, the tested equipment EUT, the auxiliary power supply V6 and the first inductor L2 are connected in series; when the parallel injection mode test is performed, the first inductor L2 and the first capacitor C2 are connected in series and then connected in parallel with the tested device EUT and the auxiliary power supply V6.

Preferably, the pulse source signal output circuit includes a dc voltage source V1, an energy storage capacitor C1, a loop inductance L1, and a tuning resistor R1, where the energy storage capacitor C1 and the tuning resistor R1 are connected in parallel with the dc voltage source V1, and the loop inductance L1 is connected in series between the energy storage capacitor C1 and the tuning resistor R1.

Preferably, the loop inductance L1 is also connected in series with a switch S1.

Preferably, the dc voltage source V1 is an isolated dc power source.

The patent also discloses a power line conduction sensitivity testing device, which comprises the power line conduction sensitivity testing circuit described in any one of the technical schemes.

The technical scheme has the following beneficial effects: the test circuit is provided with the first inductor and the first capacitor at the pulse source signal output, when the series injection mode test is carried out, the impedance of the first inductor is very low at low frequency, at the moment, large current mainly passes through an inductance loop of the pulse source, the internal resistance of the pulse source is protected, the voltage of tested equipment EUT is not reduced, the frequency of a signal output by the pulse source is very high, at the moment, the inductance reactance is very high, the pulse signal can be injected into a power line connected with the tested equipment EUT, and the test precision is ensured; when the parallel injection mode test is performed, as the impedance of the first capacitor is large at low frequency and the impedance of the first inductor is small at low frequency, the voltage drop of the first two ends is very low, so that the low-frequency voltage signals applied to the two ends of the pulse source are very low, the frequency of the signals output by the pulse source is very high, the inductance and inductance are very large at the moment, the capacitance of the capacitor becomes very small, at the moment, the high-frequency signals can be overlapped at the two ends of the EUT, the injection of interference signals is completed, and the precision of the test can be effectively ensured. The test circuit can also ensure the safety and the precision of a test without using a coupling transformer, can effectively reduce the cost, reduce wiring in the test process, is convenient to operate, and can greatly improve the test efficiency.

Drawings

FIG. 1 is a block diagram of a conventional power line conductivity sensitivity test circuit.

Fig. 2 is a circuit configuration diagram of the parallel injection mode test according to the embodiment of the present utility model.

Fig. 3 is a circuit configuration diagram of the serial injection mode test according to the embodiment of the present utility model.

Detailed Description

Further advantages and effects of the present utility model will become apparent to those skilled in the art from the disclosure of the present utility model, which is described by the following specific examples.

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the utility model. One skilled in the relevant art will recognize, however, that the utility model may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known aspects have not been shown or described in detail to avoid obscuring aspects of the utility model.

As shown in fig. 2, the present patent discloses a power line conduction sensitivity test circuit, which mainly includes a pulse source signal output circuit, a tested device EUT and an auxiliary power supply V6, wherein the pulse source signal output circuit is provided with a first terminal and a second terminal, a first inductor L2 is arranged between the first terminal and the second terminal, and the first terminal is connected with a first capacitor C2. The pulse source signal output circuit is used for outputting a pulse signal outwards, and as a specific implementation mode, the pulse source signal output circuit comprises a direct-current voltage source V1, an energy storage capacitor C1, a loop inductance L1 and a wave regulating resistor R1, wherein the energy storage capacitor C1 and the wave regulating resistor R1 are connected in parallel with the direct-current voltage source V1, and the loop inductance L1 is connected in series between the energy storage capacitor C1 and the wave regulating resistor R1. For convenience of control, the loop inductor L1 is also connected in series with a switch S1.

As shown in fig. 2, when the parallel injection test is performed, the first inductor L2 and the first capacitor C2 are connected in series and then connected in parallel with the device under test EUT and the auxiliary power supply V6. As can be seen from the principle in the figure, when the auxiliary power supply V6 supplies power to the tested device EUT, the pulse source circuit is connected in parallel to the two ends of the tested device EUT, and the voltage of the auxiliary power supply V6 is completely applied to the two ends of the pulse source. At this time, the filter network composed of the first inductor L2 and the first capacitor C2 has a large impedance at low frequency, and the inductor has a small impedance at low frequency, so that the voltage drop across the first inductor L2 is very low, and the low-frequency voltage signal applied across the pulse source is very low. The frequency of the signal output by the pulse source is very high, the inductance of the first inductor L2 is very large at the moment, the capacitance of the first capacitor C2 becomes very small, at the moment, high-frequency signals can be overlapped at two ends of tested equipment EUT, injection of interference signals is completed, and the testing precision is ensured. To prevent the voltage of the auxiliary power supply V6 from affecting the dc voltage source V1, the dc voltage source V1 may be configured to isolate the dc power supply.

As shown in fig. 3, in order to perform the series injection test, the device under test EUT, the auxiliary power supply V6, and the first inductor L2 are connected in series. The principle of the figure shows that the pulse source is connected in series to the power line of the device under test EUT in the series mode, and the current of the load completely flows through the pulse source. The resistor R1 in the conventional circuit is easy to damage due to a large current and has a voltage drop to reduce the EUT voltage. The mode of connecting the first inductor L2 in parallel at two ends of the resistor is adopted, and the impedance of the first inductor L2 is very low at low frequency, so that the high current mainly passes through an inductor loop of the pulse source, the resistor inside the pulse source is protected, and the EUT voltage is not reduced. The frequency of the signal output by the pulse source is very high, and the inductance reactance is very large at the moment, so that the pulse signal can be injected into a power line connected with the EUT.

The utility model also discloses a testing arrangement of adoption above-mentioned power cord conduction sensitivity test circuit, this testing arrangement and testing arrangement set up the filter network that constitutes through first inductance L2 and first electric capacity C2 at pulse source signal output, replace original coupling transformer, guarantee the safety and the precision of test, can effectively reduce cost, reduce the wiring in the test process, convenient operation can improve efficiency of software testing by a wide margin.

The above embodiments are merely illustrative of the principles of the present utility model and its effectiveness, and are not intended to limit the utility model. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the utility model. Accordingly, it is intended that all equivalent modifications and variations of the utility model be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims (5)

1. The power line conduction sensitivity test circuit comprises a pulse source signal output circuit, tested equipment EUT and an auxiliary power supply V6, wherein a first wiring terminal and a second wiring terminal are arranged on the pulse source signal output circuit; when the parallel injection mode test is performed, the first inductor (L2) and the first capacitor (C2) are connected in series and then connected with the tested Equipment (EUT) and the auxiliary power supply (V6) in parallel.

2. The power line conduction sensitivity test circuit according to claim 1, wherein the pulse source signal output circuit comprises a direct current voltage source (V1), an energy storage capacitor (C1), a loop inductance (L1) and a wave-regulating resistor (R1), the energy storage capacitor (C1) and the wave-regulating resistor (R1) are connected in parallel with the direct current voltage source (V1), and the loop inductance (L1) is connected in series between the energy storage capacitor (C1) and the wave-regulating resistor (R1).

3. The power line conductivity sensitivity test circuit according to claim 2, wherein said loop inductance (L1) is further connected in series with a switch (S1).

4. The power line conductivity sensitivity test circuit according to claim 2, wherein the dc voltage source (V1) is an isolated dc power source.

5. A power line conductivity sensitivity testing device, characterized in that it comprises a power line conductivity sensitivity testing circuit according to any one of claims 1 to 4.