CN2194008Y

CN2194008Y - Digital clock with calendar

Info

Publication number: CN2194008Y
Application number: CN 93246111
Authority: CN
Inventors: 齐鹏程
Original assignee: MILITARY REQUIREMENT PRODUCTION TECHNOLOGY INST OF GENERAL LOGISTICS DEPT PLA
Current assignee: MILITARY REQUIREMENT PRODUCTION TECHNOLOGY INST OF GENERAL LOGISTICS DEPT PLA
Priority date: 1993-12-06
Filing date: 1993-12-06
Publication date: 1995-04-05
Anticipated expiration: 2003-12-06

Abstract

The utility model relates to a digital clock with calendar which belongs to the instrument field. The digital clock with calendar can solve the problems that the common calendar clock is easy to break and does not have the lighting function. Even if the power is failing, the utility model can be normally operated. The digital clock with calendar is composed of a display circuit 1, a decoding drive circuit 2, a drive circuit 3, a tri-state buffer circuit 4, a clock circuit 5, a drive circuit 6, a bit decoder circuit 7 and a bit counting circuit 8. The output of the bit counting circuit 8 is divided into two paths. A path is connected with the input end of the tri-state buffer circuit 4. The other path is connected with the input end of the bit decoder circuit 7. The signal input end of the drive circuit 3 is connected with the tri-state buffer circuit 4 and the clock circuit 5. The signal output end of the decoding drive circuit 2 is connected with the display circuit 1. The input end is connected with the output end of the drive circuit 3. The signal input end of the bit decoder circuit 7 is connected with the clock circuit 5. The output end of the drive circuit 6 is connected with the display circuit 1. The input end is connected with the output end of the bit decoder circuit 7.

Description

Digital clock with calendar

The utility model belongs to the instrument field.

Existing time-of-day clock generally has three kinds of forms, and a kind of is the band calendar crystal clock that manually rotates board turning, and this product operation is cumbersome, and easily forgets and stir the calendar board; Another kind is the calendar digital clock of automatic board turning, and the weak point of this clock is, adopts mechanical drive, easy break-down, and do not have bright function at night; Also have a kind of employing LED digital clock, its drawback is: 1. use the cmos integrated circuit to be barricaded as, owing to use chip many, and adopt the special clock sheet, its working current is bigger, so be difficult for adding the protection power supply, during power failure, clock will be out of service, the accuracy of influence time; 2. use the electronic watch core repacking, production technology is poor, is difficult for a large amount of production, as the circuit special chip that uses a computer, and the one, cost is higher, and the 2nd, still need add some interference protection measures, could guarantee the clock reliability service.

The purpose of this utility model is to provide a kind of reliability height, energy-conservation, full-automatic carry, and the devices at full hardware calendar digital clock of band protection power supply.

The utility model comprises display circuit 1, decoder driver circuit 2, driving circuit 3, tri-state buffer circuit 4, clock circuit 5, driving circuit 6, position decoding scheme 7, position counting circuit 8, the output of position counting circuit 8 divides two-way, one the tunnel connects the input end of tri-state buffer circuit 4, another road connects the input end of a decoding scheme 7, the signal input part of driving circuit 3 links to each other with clock circuit 5 with tri-state buffer circuit 4, the signal output part of decoder driver circuit 2 links to each other with display circuit 1, the output terminal of its input termination driving circuit 3, the signal input part of position decoding scheme 7 links to each other with clock circuit 5, the output terminal of driving circuit 6 links to each other with display circuit 1, the output terminal of its input termination position decoding scheme 7.Position counting, the yardage of clock circuit 5 outputs are counted two-way, and its counting is input to driving circuit 6 by position decoding scheme 7, and signal is input to display circuit 1, and the yardage number is input to decoder driver circuit 2 by driving circuit 3, and signal is passed to display circuit 1.When error appears in clock, adjust position counting circuit 8, change the internal work state, the decoding scheme 7 of leading up to is adjusted the date, and another road is by the 4 adjustment times of three core buffer circuits.

Advantage of the present utility model be to have second, branch, the time, day, the moon, show whole automatic carries week; Use fully hard property circuit, cost is low, and the reliability height can move under various rugged surroundings; Adopt dynamic display types, guaranteeing on the enough bases of LED charactron brightness that dynamically demonstration shows that than static state economize on electricity is more than 50%; The utility model is done the protection power supply with the 3.6V accumulator, even have a power failure, also can not influence the normal operation of clock.

Fig. 1 is the utility model schematic block circuit diagram

Fig. 2 is the utility model circuit theory diagrams

Fig. 3 is the utility model power circuit

Embodiment:

Display circuit 1 is by 11 light-emitting diode display L1～L11; adjustable resistance R1～R11; light emitting diode D1～D2 forms; decoder driver circuit 2 is by decoder driver T3; resistance R 13～R17 forms; decoder driver T3 can select CD4513 for use, and driving circuit 3 is by driver T6; resistance R 18～R21 forms, and driver T6 can select 74LS07 for use; tri-state buffer circuit 4 is by six non-inverting buffer T10; resistance R 25 is formed; six non-inverting buffer T10 can select CD4503 for use, and clock circuit 5 is by clock chip T9; resistance R 26～R28; switch W4; diode D7; capacitor C 4～C6; protection power supply E1; oscillator XT forms, and clock chip T9 can select M5832 for use; driving circuit 6 is by driver T1; T2 forms; driver T1; T2 all can select 74LS06 for use, and position decoding scheme 7 is by decimal decoder T4; 2 input end four nor gate T5; 2 input ends four are formed with non-schmitt trigger T7, and position counting circuit 8 is by resistance R 22～R24; R29～R30; diode D3～D6; switch W1～W3; K switch; capacitor C 1; C2; doubinary system up counter T8 forms; T8 can select CD4520 for use; diode D5; one end of the positive pole of D6 and resistance R 23 all links to each other diode D5 with (15) pin of T8; the other end of the negative pole of D6 and resistance R 23 connect respectively T8's (12); (11); (14) pin, the 10. pin of capacitor C 1 and a termination T8 after switch W1 is in parallel; other end ground connection; 10. resistance R 22 is connected in T8; (16) between the pin, the 9. pin ground connection of T8, (16) pin meets Vdd; one end of resistance R 29 and diode D3; the anodal of D4 all links to each other with the 7. pin of T8; the other end of resistance R 29 and diode D3; the negative pole of D4 respectively with T8 6.; 4.; 3. pin links to each other, and T8 1.; 8. pin ground connection, 3.; 4.; 5.; 6. pin respectively with T4 10.; (13); (12); (11) pin links to each other; the 2. pin of T8 links to each other with the 4. pin of T7; the 8. pin ground connection of T4, (16) pin of T4 meets Vdd, and T4 is 5.; 9.; 4.; 7. pin respectively with T1 9.; 5.; 3.; 1. pin links to each other; T4 6.; 1.; (15); 2.; (14); 3. pin respectively with (13) of T2; (11); 9.; 5.; 3.; 1. pin links to each other; (12) of T1; (13) pin is unsettled, and (14) pin meets Vdd, and the pin that (11) pin meets T5 10.; T1 10.; 8.; 6.; 4.; 2. meet adjustable resistance R1 respectively; R2; R3; R4; the end of R5; adjustable resistance R1; R2; R3; R4; the other end of R5 meets light-emitting diode display L1 respectively; L2; L3; L4; the bit line of L5, capacitor C 2 be with after switch W2 is in parallel, an end ground connection; the other end links to each other with the 5. pin of T7; the 5. pin of resistance R 24 1 termination T7, another termination Vdd, resistance R 30 1 ends link to each other with the 4. pin of T7; 2. the pin of another termination K switch; the 6. pin of T7 and the 2. pin of K switch be all by capacitor C 3 ground connection, and switch W3 is connected between 18 pin of the 2. pin of K switch and T9, and T10 2.; 4.; 6.; 10. pin respectively with (14) of T8; (13); (12); (11) pin links to each other; T10 3.; 5.; 7.; 9. pin respectively with T6 9.; 5.; 3.; 1. pin links to each other; (13) pin of T10 links to each other with 3. pin, and (11) pin of T10 links to each other (12) with 5. pin; (14) pin ground connection; the 1. pin of T10 links to each other with the 1. pin of K switch; resistance R 25 be connected in and 1. between the pin of T10, the 8. pin ground connection of T10, oscillator XT(can select 32768Hz for use) be connected in T9 (16); (17) between the pin; capacitor C 5 is connected between T9's (16) pin and the ground; capacitor C 6 is connected between T9's (17) pin and the ground, (13) pin ground connection of T9, (15) pin of capacitor C 4 and resistance R 27 back one termination T9 in parallel; other end ground connection; 8. switch W4 is connected in T9; (15) between the pin, (14) pin ground connection of T9,2. (18) pin of T9 is all by resistance R 28 ground connection; the 3. pin of T9 links to each other with the 1. pin of T10; the 8. pin of T9 meets Vdd, and diode D7 positive pole connects the 8. pin of T9, and negative pole connects the 1. pin of T9; the 1. pin of T9 connects the positive pole of protection power supply E1 by resistance R 26; the minus earth of E1, T9 are 4.; 5.; 6.; 7. pin respectively with T4 10.; (13); (12); (11) pin links to each other, and T9 9.; 10.; (11); (12) pin respectively with T6 1.; 3.; 5.; 9. pin links to each other; the 7. pin ground connection of T6; resistance R 18; R19; R20; R21 one end all meets Vdd, and 9. the other end meets T6 respectively; 5.; 3.; 1. pin, (11) pin of T6 connects the 3. pin of T5; (14) pin of T6 meets Vdd; T6 10.; 8.; 6.; 4.; 2. 8. pin meets T3 respectively; 6.; 2.; 1.; 7. pin, resistance R 13; R14; R15; R16; R17 one end all meets Vcc, and 8. the other end meets T3 respectively; 6.; 2.; 1.; 7. pin; T3 3.; 4.; (18) pin meets Vcc; the 5. pin ground connection of T3, (16) of T3; (17); (11); (12); (13); (14); (15) pin respectively with the g of L1～L11; f; e; d; c; b; a links to each other, the 7 pin ground connection of T7; 1.; 2. pin respectively with (11) of T4; (13) pin links to each other; T7 3.; (12) pin and T5 are 8.; 9. pin links to each other, and (14) pin of T7 meets Vdd, and (13) pin of T7 connects (11) pin of T5; T7 9.; (11) pin links to each other; the 10. pin of T7 links to each other with the 3. pin of T5, and T5 4.; 5.; 6. pin is unsettled, the 7. pin ground connection of T5; (14) pin of T5 meets Vdd; (13) pin of T5 connects (13) pin of T2, and (12) pin of T5 links to each other with the 5. pin of T1, and the 10. pin of T5 links to each other with (11) pin of T1; the 7. pin ground connection of T2; the 4. pin of T2 meets Vdd, (12) of T2; 10.; 8.; 6.; 4.; 2. pass through R6 respectively; R7; R9; R10; R11; R12 and L6; L7; L8; L9; L10; L11 links to each other, diode D2 minus earth; the anodal adjustable resistance R8 that passes through links to each other with the negative pole of diode D1, and the positive pole of diode D1 meets Vcc.

Claims

1, devices at full hardware calendar digital clock, comprise display circuit 1, decoder driver circuit 2, driving circuit 3, tri-state buffer circuit 4, driving circuit 6, position decoding scheme 7, position counting circuit 8, it is characterized in that also comprising clock circuit 5, the output of position counting circuit 8 divides two-way, one the tunnel connects the input end of tri-state buffer circuit 4, another road connects the input end of a decoding scheme 7, the signal input part of driving circuit 3 links to each other with clock circuit 5 with tri-state buffer circuit 4, the signal output part of decoder driver circuit 2 links to each other with display circuit 1, the output terminal of its input termination driving circuit 3, the signal input part of position decoding scheme 7 links to each other with display circuit 1, the output terminal of its input termination position decoding scheme 7.

2; according to the described devices at full hardware calendar of claim 1 digital clock, it is characterized in that display circuit 1 is by 11 light-emitting diode display L1～L11; adjustable resistance R1～R11; light emitting diode D1～D2 forms; decoder driver circuit 2 is by decoder driver T3; resistance R 13～R17 forms; decoder driver T3 can select CD4513 for use, and driving circuit 3 is by driver T6; resistance R 18～R21 forms, and driver T6 can select 74LS07 for use; tri-state buffer circuit 4 is by six non-inverting buffer T10; resistance R 25 is formed; six non-inverting buffer T10 can select CD4503 for use, and clock circuit 5 is by clock chip T9; resistance R 26～R28; switch W4; diode D7; capacitor C 4～C6; protection power supply E1; oscillator XT forms, and clock chip T9 can select M5832 for use; driving circuit 6 is by driver T1; T2 forms; driver T1; T2 all can select 74LS06 for use, and position decoding scheme 7 is by decimal decoder T4; 2 input end four nor gate T5; 2 input ends four are formed with non-schmitt trigger T7, and position counting circuit 8 is by resistance R 22～R24; R29～R30; diode D3～D6; switch W1～W3; K switch; capacitor C 1; C2; doubinary system up counter T8 forms; T8 can select CD4520 for use; diode D5; one end of the positive pole of D6 and resistance R 23 all links to each other diode D5 with (15) pin of T8; the other end of the negative pole of D6 and resistance R 23 connect respectively T8's (12); (11); (14) pin, the 10. pin of capacitor C 1 and a termination T8 after switch W1 is in parallel; other end ground connection; 10. resistance R 22 is connected in T8; (16) between the pin, the 9. pin ground connection of T8, (16) pin meets Vdd; one end of resistance R 29 and diode D3; the anodal of D4 all links to each other with the 7. pin of T8; the other end of resistance R 29 and diode D3; the negative pole of D4 respectively with T8 6.; 4.; 3. pin links to each other, and T8 1.; 8. pin ground connection, 3.; 4.; 5.; 6. pin respectively with T4 10.; (13); (12); (11) pin links to each other; the 2. pin of T8 links to each other with the 4. pin of T7; the 8. pin ground connection of T4, (16) pin of T4 meets Vdd, and T4 is 5.; 9.; 4.; 7. pin respectively with T1 9.; 5.; 3.; 1. pin links to each other; T4 6.; 1.; (15); 2.; (14); 3. pin respectively with (13) of T2; (11); 9.; 5.; 3.; 1. pin links to each other; (12) of T1; (13) pin is unsettled, and (14) pin meets Vdd, and the pin that (11) pin meets T5 10.; T1 10.; 8.; 6.; 4.; 2. meet adjustable resistance R1 respectively; R2; R3; R4; the end of R5; adjustable resistance R1; R2; R3; R4; the other end of R5 meets light-emitting diode display L1 respectively; L2; L3; L4; the bit line of L5, capacitor C 2 be with after switch W2 is in parallel, an end ground connection; the other end links to each other with the 5. pin of T7; the 5. pin of resistance R 24 1 termination T7, another termination Vdd, resistance R 30 1 ends link to each other with the 4. pin of T7; 2. the pin of another termination K switch; the 6. pin of T7 and the 2. pin of K switch be all by capacitor C 3 ground connection, and switch W3 is connected between 18 pin of the 2. pin of K switch and T9, and T10 2.; 4.; 6.; 10. pin respectively with (14) of T8; (13); (12); (11) pin links to each other; T10 3.; 5.; 7.; 9. pin respectively with T6 9.; 5.; 3.; 1. pin links to each other; (13) pin of T10 links to each other with 3. pin, and (11) pin of T10 links to each other (12) with 5. pin; (14) pin ground connection; the 1. pin of T10 links to each other with the 1. pin of K switch; resistance R 25 be connected in and 1. between the pin of T10, the 8. pin ground connection of T10, oscillator XT(can select 32768Hz for use) be connected in T9 (16); (17) between the pin; capacitor C 5 is connected between T9's (16) pin and the ground; capacitor C 6 is connected between T9's (17) pin and the ground, (13) pin ground connection of T9, (15) pin of capacitor C 4 and resistance R 27 back one termination T9 in parallel; other end ground connection; 8. switch W4 is connected in T9; (15) between the pin, (14) pin ground connection of T9,2. (18) pin of T9 is all by resistance R 28 ground connection; the 3. pin of T9 links to each other with the 1. pin of T10; the 8. pin of T9 meets Vdd, and diode D7 positive pole connects the 8. pin of T9, and negative pole connects the 1. pin of T9; the 1. pin of T9 connects the positive pole of protection power supply E1 by resistance R 26; the minus earth of E1, T9 are 4.; 5.; 6.; 7. pin respectively with T4 10.; (13); (12); (11) pin links to each other, and T9 9.; 10.; (11); (12) pin respectively with T6 1.; 3.; 5.; 9. pin links to each other; the 7. pin ground connection of T6; resistance R 18; R19; R20; R21 one end all meets Vdd, and 9. the other end meets T6 respectively; 5.; 3.; 1. pin, (11) pin of T6 connects the 3. pin of T5; (14) pin of T6 meets Vdd; T6 10.; 8.; 6.; 4.; 2. 8. pin meets T3 respectively; 6.; 2.; 1.; 7. pin, resistance R 13; R14; R15; R16; R17 one end all meets Vcc, and 8. the other end meets T3 respectively; 6.; 2.; 1.; 7. pin; T3 3.; 4.; (18) pin meets Vcc; the 5. pin ground connection of T3, (16) of T3; (17); (11); (12); (13); (14); (15) pin respectively with the g of L1～L11; f; e; d; c; b; a links to each other, the 7 pin ground connection of T7; 1.; 2. pin respectively with (11) of T4; (13) pin links to each other; T7 3.; (12) pin and T5 are 8.; 9. pin links to each other, and (14) pin of T7 meets Vdd, and (13) pin of T7 connects (11) pin of T5; T7 9.; (11) pin links to each other; the 10. pin of T7 links to each other with the 3. pin of T5, and T5 4.; 5.; 6. pin is unsettled, the 7. pin ground connection of T5; (14) pin of T5 meets Vdd; (13) pin of T5 connects (13) pin of T2, and (12) pin of T5 links to each other with the 5. pin of T1, and the 10. pin of T5 links to each other with (11) pin of T1; the 7. pin ground connection of T2; the 4. pin of T2 meets Vdd, (12) of T2; 10.; 8.; 6.; 4.; 2. pass through R6 respectively; R7; R9; R10; R11; R12 and L6; L7; L8; L9; L10; L11 links to each other, diode D2 minus earth; the anodal adjustable resistance R8 that passes through links to each other with the negative pole of diode D1, and the positive pole of diode D1 meets Vcc.