CN219372401U - Semiconductor wafer level packaging structure - Google Patents
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- CN219372401U CN219372401U CN202223439266.5U CN202223439266U CN219372401U CN 219372401 U CN219372401 U CN 219372401U CN 202223439266 U CN202223439266 U CN 202223439266U CN 219372401 U CN219372401 U CN 219372401U
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Abstract
The utility model provides a semiconductor wafer-level packaging structure, which comprises a semiconductor chip, a cap, a connecting structure, a conductive structure and a solder ball, wherein the cap is of a multilayer film structure; the front surface of the semiconductor chip is opposite to the front surface of the cap, and connection is formed through a connection structure arranged between the front surface of the semiconductor chip and the front surface of the cap; the connecting structure comprises a first connecting part and a second connecting part, wherein the first connecting part is electrically connected with the semiconductor chip, the second connecting part, the semiconductor chip and the cap enclose a sealing cavity, and a device area of the semiconductor chip is positioned in the sealing cavity; a first through hole is formed in the position, corresponding to the first connecting part, on the cap, and the conductive structure is arranged in the first through hole and is electrically connected with the first connecting part; the solder balls are formed on the back surface of the cap and are electrically connected with the conductive structures. The semiconductor wafer level packaging structure provided by the utility model has the advantage of low manufacturing cost.
Description
Technical Field
The present disclosure relates to semiconductor packaging technology, and more particularly, to a semiconductor wafer level package structure.
Background
Wafer level packaging is an advanced chip packaging technology, in which a semiconductor wafer level packaging structure can be obtained by performing wafer level packaging on a semiconductor chip. The following description will be made with respect to a filter wafer level package structure as a typical representative of a semiconductor wafer level package structure. Referring to fig. 1, fig. 1 is a schematic cross-sectional view of a wafer level package structure of a filter in the prior art. As shown, includes: the filter chip, cap 20, connection structure, metal conductive structures 40, and solder balls 42. The filter chip includes a substrate 10 and a plurality of laminated structures 11 (only one laminated structure is schematically drawn in the figure for simplicity) formed on the substrate 10, a groove is formed in a position below each laminated structure 11 of the substrate 10, the groove and the laminated structure 11 above the groove enclose an air gap 12 for reflecting sound waves, each laminated structure 11 includes at least a lower electrode, a piezoelectric layer and an upper electrode from bottom to top, and the upper electrode, the piezoelectric layer, the lower electrode and the air gap 12 below the upper electrode have an overlapping area in a thickness direction of the device. The cap 20 is disposed in a front-facing manner with respect to the filter chip, and the connection of the two is achieved by a connection structure. The connection structure includes a first Au-Au bonding part 30a and a second Au-Au bonding part 30b, wherein the first Au-Au bonding part 30a is used for signal extraction, one end of the first Au-Au bonding part is connected with the cap 20, the other end of the first Au-Au bonding part is electrically connected with the filter chip, and the second Au-Au bonding part 30b is used as a sealing ring for protecting the device region of the filter chip. Through holes are formed in the cap 20 at positions corresponding to the first Au-Au bonding portions, and the metal conductive structures 40 are filled in the through holes and electrically connected to the first Au-Au bonding portions 30 a. Solder balls 42 are formed on the back of cap 20 and electrically connect to conductive structures 40. An Under Bump Metallization (UBM) layer 41 is typically formed between the solder balls 42 and the metal conductive structure 40.
For the above-described conventional filter package structure, since the metal conductive structure 40 is provided in the cap 20, the conventional cap 20 is generally implemented with high-resistance silicon (thickness is generally greater than 100 μm) in order to prevent unnecessary electrical connection. Accordingly, forming the Via hole on the cap 20 and filling the metal conductive structure 40 needs to be performed Through a Through-Silicon Via (TSV) process. The cost of the high-resistance silicon and the cost of the through silicon via technology are high, so that the manufacturing cost of the filter packaging structure is high.
Disclosure of Invention
In order to overcome the above-mentioned drawbacks of the prior art, the present utility model provides a semiconductor wafer level package structure, comprising:
the semiconductor chip comprises a semiconductor chip, a cap, a connecting structure, a conductive structure and a solder ball, wherein the cap is of a multilayer film structure;
the front surface of the semiconductor chip is opposite to the front surface of the cap, and connection is formed through the connection structure arranged between the front surface and the front surface of the cap;
the connecting structure comprises a first connecting part and a second connecting part, the first connecting part is electrically connected with the semiconductor chip, the second connecting part, the semiconductor chip and the cap enclose a sealing cavity, and a device area of the semiconductor chip is positioned in the sealing cavity;
a first through hole is formed in the position, corresponding to the first connecting part, of the cap, and the conductive structure is arranged in the first through hole and is electrically connected with the first connecting part;
the solder balls are formed on the back surface of the cap and are electrically connected with the conductive structures.
According to one aspect of the present utility model, in the semiconductor wafer level package structure, the thickness of the multilayer thin film structure ranges from 10 μm to 20 μm.
According to another aspect of the present utility model, in the semiconductor wafer level package structure, the multilayer thin film structure includes a first thin film layer and a second thin film layer stacked along a thickness thereof, or the multilayer thin film structure includes the first thin film layer and the second thin film layer alternately arranged along the thickness thereof; wherein the materials of the first thin film layer and the second thin film layer have opposite stresses.
According to still another aspect of the present utility model, in the semiconductor wafer level package structure, the materials of the first thin film layer and the second thin film layer are inorganic insulating materials.
According to still another aspect of the present utility model, in the semiconductor wafer level package structure, one of the first thin film layer and the second thin film layer is a silicon dioxide layer, and the other is a silicon nitride layer.
According to yet another aspect of the present utility model, in the semiconductor wafer level package structure, a ratio of a total thickness of the silicon oxide layer to a total thickness of the silicon nitride layer in the multilayer thin film structure is greater than 2.
According to still another aspect of the present utility model, in the semiconductor wafer level package structure, the multilayer thin film structure further includes an insulating layer formed on a sidewall of the first via hole, wherein one of the first thin film layer and the second thin film layer is a low-resistance semiconductor material and the other is an inorganic insulating material.
According to still another aspect of the present utility model, in the semiconductor wafer level package structure, one of the first thin film layer and the second thin film layer is a low-resistance silicon layer, and the other is a silicon dioxide layer.
According to still another aspect of the present utility model, in the semiconductor wafer level package structure, the multilayer thin film structure further includes a first photoresist layer formed on a surface of the structure formed by the first thin film layer and the second thin film layer facing away from the semiconductor chip.
According to still another aspect of the present utility model, in the semiconductor wafer level package structure, the first connection portion includes a metal layer and a second photoresist layer that form a connection by bonding, wherein the metal layer is located on the semiconductor chip side, the second photoresist layer is located on the cap side, and a second via hole corresponding to the conductive structure is formed on the second photoresist layer, and the conductive structure extends from the first via hole to the second via hole to be electrically connected with the metal layer; the second connection portion includes a third photoresist layer.
The cap in the semiconductor wafer level packaging structure provided by the utility model is realized by adopting a multilayer film structure. In other words, the utility model avoids the use of high-resistance silicon when the cap is realized, and correspondingly, the through holes are formed in the cap and the conductive structure is filled without using the through silicon hole technology, so that the manufacturing cost of the semiconductor wafer level packaging structure can be effectively reduced. Compared with the prior art, the semiconductor wafer level packaging structure provided by the utility model has the advantage of low manufacturing cost.
Drawings
Other features, objects and advantages of the present utility model will become more apparent upon reading of the detailed description of non-limiting embodiments, made with reference to the accompanying drawings in which:
FIG. 1 is a schematic cross-sectional view of a prior art wafer level package structure for a filter;
FIG. 2 is a schematic cross-sectional view of a filter wafer level package structure according to one embodiment of the present utility model;
FIG. 3 is a schematic cross-sectional view of a filter wafer level package structure according to another embodiment of the present utility model;
FIG. 4 is a schematic cross-sectional view of a filter wafer level package structure according to yet another embodiment of the present utility model;
FIG. 5 is a schematic cross-sectional view of a filter wafer level package structure according to yet another embodiment of the present utility model;
FIG. 6 is a schematic cross-sectional view of a filter wafer level package structure according to yet another embodiment of the present utility model;
FIG. 7 is a schematic cross-sectional view of a filter wafer level package structure according to yet another embodiment of the present utility model;
FIG. 8 is a schematic cross-sectional view of a filter wafer level package structure according to yet another embodiment of the present utility model;
fig. 9 is a schematic cross-sectional view of a filter wafer level package structure according to yet another embodiment of the present utility model.
The same or similar reference numbers in the drawings refer to the same or similar parts.
Detailed Description
For a better understanding and explanation of the present utility model, reference will be made to the following detailed description of the utility model taken in conjunction with the accompanying drawings.
The utility model provides a semiconductor wafer-level packaging structure, which comprises:
the semiconductor chip comprises a semiconductor chip, a cap, a connecting structure, a conductive structure and a solder ball, wherein the cap is of a multilayer film structure;
the front surface of the semiconductor chip is opposite to the front surface of the cap, and connection is formed through the connection structure arranged between the front surface and the front surface of the cap;
the connecting structure comprises a first connecting part and a second connecting part, the first connecting part is electrically connected with the semiconductor chip, the second connecting part, the semiconductor chip and the cap enclose a sealing cavity, and a device area of the semiconductor chip is positioned in the sealing cavity;
a first through hole is formed in the position, corresponding to the first connecting part, of the cap, and the conductive structure is arranged in the first through hole and is electrically connected with the first connecting part;
the solder balls are formed on the back surface of the cap and are electrically connected with the conductive structures.
The above-described respective components of the present utility model will be described in detail below with reference to fig. 2 to 5, using a filter wafer level package structure as a typical representative of a semiconductor wafer level package structure.
Specifically, the filter wafer level packaging structure provided by the utility model comprises a filter chip. As shown in the drawing, in the present embodiment, the filter chip includes a substrate 100 provided with a plurality of grooves, and a laminated structure 101 formed on the substrate 100 in one-to-one correspondence with the plurality of grooves. Each laminated structure 101 is formed above its corresponding recess, and the lower surface of each laminated structure 101 and the inner wall of the recess below it enclose an air gap 102. Further, each of the stacked structures 101 includes at least a lower electrode, a piezoelectric layer, and an upper electrode from bottom to top, and the upper electrode, the piezoelectric layer, the lower electrode, and the air gap 102 thereunder have an overlapping structure in the device thickness direction. Each of the laminated structures and the portion of the substrate 100 located under the laminated structure and the air gap 102 located therebetween constitute an air gap type bulk acoustic wave resonator, i.e., the filter chip in this embodiment includes a plurality of air gap type bulk acoustic wave resonators. It should be noted that (1) for simplicity, only one bulk acoustic wave resonator is drawn on the filter chip shown in fig. 2 to 5 as a schematic example. Those skilled in the art will appreciate that the specific number of resonators on a filter chip and the connection relationship are determined by the actual design requirements. (2) In this embodiment, the resonator on the filter chip is an air gap bulk acoustic wave resonator, and in other embodiments, the resonator on the filter chip may be another type of bulk acoustic wave resonator (such as a bragg reflection bulk acoustic wave resonator or a back side etched bulk acoustic wave resonator), or another type of resonator (such as a surface acoustic wave resonator). Furthermore, the resonators on the filter chip may be of the same type or of different types, and are not limited in any way herein. (3) The materials, dimensions, and the like of the substrate 100 and the layers in the stacked structure 101 may be conventionally designed, and are not particularly limited herein.
The wafer level packaging structure of the filter provided by the utility model further comprises a cap matched with the filter chip, wherein the front surface of the cap is opposite to the front surface (namely, the surface formed with the laminated structure) of the filter chip, and the cap is in a multi-layer film structure, namely, at least comprises two film layers. To meet the radio frequency requirements of the filter wafer level package structure, the overall thickness of the multilayer thin film structure is typically not less than 10 μm, preferably 10 μm to 20 μm, e.g. 10 μm, 15 μm, 20 μm, etc. It will be appreciated by those skilled in the art that the above-described thickness range of 10 μm to 20 μm is only a preferred embodiment and should not be taken as limiting the cap thickness. In structural terms, the multilayer thin film structure comprises a first thin film layer and a second thin film layer stacked along its thickness, or the multilayer thin film structure comprises alternately arranged first thin film layers and second thin film layers (i.e., the total number of layers of the first thin film layer and the second thin film layer is at least three); wherein the materials of the first thin film layer and the second thin film layer have opposite stresses. The materials of the first film layer and the second film layer in the multilayer film structure have opposite stress, so that the multilayer film structure can be in a low-stress state, the warping of the multilayer film structure is effectively prevented, and the yield of the wafer-level packaging structure of the filter is improved. The constitution of the multilayer film structure will be described below with specific examples.
In one embodiment, as shown in fig. 2, the multi-layered thin film structure includes a first thin film layer 201a and a second thin film layer 201b stacked along the thickness thereof, or as shown in fig. 3, the multi-layered thin film structure includes the first thin film layer 201a and the second thin film layer 201b alternately arranged along the thickness thereof, wherein the materials of the first thin film layer 201a and the second thin film layer 201b are inorganic insulating materials. It should be noted that the two first thin film layers and the one second thin film layer shown in fig. 3 are merely illustrative examples of the first thin film layers and the second thin film layers that are alternately arranged, and should not be construed as limiting the present utility model. In other embodiments, two first thin film layers and two second thin film layers may be alternately arranged, or three first thin film layers and two second thin film layers may be alternately arranged, which is not limited in this utility model. For the case where the materials of the first thin film layer and the second thin film layer are both inorganic insulating materials, in a preferred embodiment, one of the first thin film layer and the second thin film layer is a silicon oxide layer and the other is a silicon nitride layer (wherein the silicon nitride layer is used to adjust the stress so that the multilayer thin film structure is in a low stress state). That is, the first thin film layer 201a may be a silicon oxide layer, the second thin film layer 201b may be a silicon nitride layer, the first thin film layer 201a may be a silicon nitride layer, and the second thin film layer 201b may be a silicon oxide layer. It will be appreciated by those skilled in the art that the silicon dioxide layer and the silicon nitride layer are only preferred embodiments, and in other embodiments, other inorganic insulating materials having opposite stress and suitable for the cap may be used, and all possible materials for the first thin film layer and the second thin film layer are not listed here for the sake of brevity. In addition, the specific thicknesses of the first film layer and the second film layer are not limited, and the specific thicknesses and the specific layer numbers of the film layers can be correspondingly formulated according to the radio frequency requirements of the filter wafer level packaging structure, the film layer manufacturing process and the specific materials and the specific layer numbers of the film layers. In a preferred embodiment, the multilayer thin film structure comprises alternating silicon dioxide and silicon nitride layers, wherein each silicon dioxide layer has a thickness in the range of 1 μm to 2 μm and each silicon nitride layer has a thickness in the range of 0.5 μm to 1 μm. It is to be noted that, in the case where one of the first thin film layer and the second thin film layer is a silicon oxide layer and the other is a silicon nitride layer, it is preferable that the silicon nitride layer has an excellent stress adjusting effect on the multilayer thin film structure when the ratio of the total thickness of the silicon oxide layer to the total thickness of the silicon nitride layer in the multilayer thin film structure is more than 2.
In another embodiment, the multi-layered thin film structure includes first and second thin film layers 201a and 201b stacked along the thickness thereof, and an insulating layer 202 formed at the side wall of the first via hole, as shown in fig. 4, or the multi-layered thin film structure includes first and second thin film layers 201a and 202b alternately arranged along the thickness thereof, and an insulating layer 202 formed at the side wall of the first via hole, as shown in fig. 5, wherein one of the first and second thin film layers 201a and 201b is a low-resistance semiconductor material and the other is an inorganic insulating material. It should be noted that the two first thin film layers and the one second thin film layer shown in fig. 5 are merely illustrative examples of the first thin film layers and the second thin film layers that are alternately arranged, and should not be construed as limiting the present utility model. For the case where one of the first thin film layer and the second thin film layer is a low resistance semiconductor material and the other is an inorganic insulating material, in a preferred embodiment, one of the first thin film layer and the second thin film layer is a low resistance silicon layer and the other is a silicon dioxide layer (wherein the silicon dioxide layer is used to regulate stress to place the multilayer thin film structure in a low stress state). That is, the first thin film layer 201a may be a low-resistance silicon layer, the second thin film layer 201b may be a silicon dioxide layer, or the first thin film layer 201a may be a silicon dioxide layer and the second thin film layer 201b may be a low-resistance silicon layer. It will be appreciated by those skilled in the art that the low resistance silicon layer and the silicon dioxide layer are only preferred embodiments, and in other embodiments, other low resistance semiconductor materials and inorganic insulating materials having opposite stress and suitable for the cap may be used, and for the sake of brevity, all possible materials for the first thin film layer and the second thin film layer are not listed here. In addition, the specific thicknesses of the first film layer and the second film layer are not limited, and the specific thicknesses and the specific layer numbers of the film layers can be correspondingly formulated according to the radio frequency requirements of the filter wafer level packaging structure, the film layer manufacturing process and the specific materials and the specific layer numbers of the film layers. Since the low-resistance semiconductor material is included in the multi-layered thin film structure, forming the insulating layer 202 on the inner wall of the first via hole of the cap can effectively avoid unnecessary electrical connection. The material of the insulating layer 202 is not limited in any way, and may be implemented by using conventional insulating materials such as silicon dioxide, photoresist, and the like.
The filter chip and the cap are connected by a connection structure provided therebetween. In the present embodiment, the connection structure includes a first connection portion 300a and a second connection portion 300b. The first connection parts 300a are distributed between the filter chip and the cap in a block or point-like discrete manner, and have one end connected to the cap and the other end electrically connected to the filter chip for extracting signals from the filter chip. The second connection part 300b is formed in a ring shape at edge regions of the filter chip and the cap, and both ends thereof are respectively connected with the cap and the filter chip and form a sealing cavity with both of them, and the device region of the filter chip is sealed in the sealing cavity to be protected. In the present embodiment, the first connection portion 300a and the second connection portion 300b are each implemented with a metal bonding structure, such as an au—au bonding structure, a cu—cu bonding structure, or the like.
The wafer level package structure of the filter provided by the utility model further comprises a conductive structure 400, wherein the conductive structure 400 is formed in the first through hole of the cap and is electrically connected with the first connection part 300a, so that signals of the filter chip are led out of the wafer level package structure of the filter. The conductive structure 400 is implemented using a metal such as Cu.
The filter wafer level package structure provided by the present utility model further includes solder balls 402, and the solder balls 402 are formed on the back surface of the cap and electrically connected to the conductive structure 400. In this embodiment, solder balls 402 are formed on the back of the cap at a location directly above the conductive structure 400, as shown. An under bump metallization layer 401 is preferably formed between the solder balls 402 and the conductive structure 400. Those skilled in the art will appreciate that in other embodiments, the solder balls 402 may be formed at other locations on the back of the cap, in which case the connection between the conductive structure 400 and the solder balls 402 may be achieved by providing a metal redistribution layer between the two.
It should be noted that the semiconductor wafer level package structure should not be limited to the above-mentioned filter wafer level package structure, and any semiconductor wafer level package structure that packages a semiconductor chip by using a cap falls within the scope of the present utility model, and all possible types of semiconductor wafer level package structures are not listed here for brevity.
The cap in the semiconductor wafer level packaging structure provided by the utility model is realized by adopting a multilayer film structure, so that the use of high-resistance silicon is avoided, and correspondingly, the through holes are formed in the cap and the conductive structure is filled without using a through silicon hole technology, so that the manufacturing cost of the semiconductor wafer level packaging structure can be effectively reduced. Compared with the prior art, the semiconductor wafer level packaging structure provided by the utility model has the advantage of low manufacturing cost.
Preferably, the multi-layer thin film structure further includes a photoresist layer (hereinafter referred to as a first photoresist layer 203), which is formed on the back surface of the structure formed by the first thin film layer and the second thin film layer (i.e., the surface facing away from the semiconductor chip), which is also understood as the back surface of the layer of the first thin film layer and the second thin film layer farthest from the semiconductor chip. The filter wafer level package structure is still described as an example. In one embodiment, as shown in fig. 6, the multi-layered thin film structure includes a first thin film layer 201a, a second thin film layer 201b, and a first photoresist layer 203 in this order along the front to back direction of the cap. In another embodiment, as shown in fig. 7, the multi-layered thin film structure includes a first thin film layer 201a, a second thin film layer 201b, a first thin film layer 201a, and a first photoresist layer 203 in this order along the front to back direction of the cap. The material of the first photoresist layer is not limited in any way, and can be implemented by adopting a conventional photoresist material, for example, one or any combination of benzocyclobutene, dry film and polyimide. The use of the first photoresist layer can protect the back surface of the cap (i.e., the surface of the wafer-level packaging structure of the filter) on the one hand; on the other hand, the thickness of the structure formed by the first film layer and the second film layer can be reduced. The manufacturing process of the photoresist layer is lower than that of the inorganic insulating material layer and the low-resistance semiconductor layer, so that the manufacturing difficulty of the cap can be effectively reduced by using the first photoresist layer. In addition, for the case where one of the first thin film layer and the second thin film layer is a low-resistance silicon layer and the other is a silicon oxide layer, the low-resistance silicon layer and the silicon oxide layer may be realized by selecting a top layer of silicon on insulator (i.e., a silicon layer) and an intermediate layer (i.e., a silicon oxide layer). Considering that the total thickness of the top layer and the middle layer in the silicon on insulator is generally relatively thin, the rf requirement of the wafer level package structure of the filter cannot be well met, so the first photoresist layer in this case mainly plays a role in ensuring that the thickness of the cap meets the rf requirement of the wafer level package structure of the filter. For the case where one of the first thin film layer and the second thin film layer is implemented with a low-resistance semiconductor material in the multi-layered thin film structure, it is preferable that, as shown in fig. 8, the first photoresist layer 203 extends into the first through hole of the cap to form a cover on the inner wall thereof, i.e., the portion of the first photoresist layer 203 extending into the first through hole of the cap serves as an insulating layer.
Preferably, as shown in fig. 9, the first connection portion includes a metal layer 301a and a photoresist layer 302a (hereinafter, referred to as a second photoresist layer 302 a) that form a connection by bonding. The metal layer 301a is located on the filter chip side and the second photoresist layer 302a is located on the cap side. The metal layer 301a is electrically connected to the filter chip, a second through hole corresponding to the conductive structure 400 in the cap is formed in the second photoresist layer 302a, and the conductive structure 400 in the cap extends from the first through hole to the second through hole of the cap until the conductive structure is electrically connected to the metal layer 301a, so that signal extraction of the filter chip is realized. The second connection portion includes a photoresist layer 300b (hereinafter, referred to as a third photoresist layer 300 b). In this embodiment, the metal layer 301a may be implemented using a conventional connection metal such as Au, cu, or the like; the second photoresist layer 302a and the third photoresist layer 300b may be implemented using conventional photoresist materials, such as benzocyclobutene, dry film, polyimide, or any combination thereof. Compared with the prior art that the connecting structure is realized by adopting metals such as Au, the utility model adopts the photoresist and the metal layer to form the connecting structure together, so that the cost of the connecting structure can be effectively reduced, and the cost of the packaging structure is reduced.
The following is a brief description of the manufacturing process of the semiconductor wafer level package structure provided by the present utility model, taking the filter wafer level package structure shown in fig. 9 as an example.
In step S100, a filter chip is provided, and a metal layer electrically connected to the device is formed on the filter chip.
In step S101, a low-resistance silicon wafer is provided, and a second thin film layer and a first thin film layer are sequentially deposited on the low-resistance silicon wafer. It should be noted that, for the case where the first thin film layer is a low-resistance silicon layer and the second thin film layer is a silicon dioxide layer, this step may be directly implemented by using silicon on insulator.
In step S102, a second photoresist layer and a third photoresist layer are formed on the first thin film layer. The third photoresist layer is annular and is formed in the edge area of the first film layer, the second photoresist layer is formed at a position corresponding to the metal layer on the filter chip, and a second through hole corresponding to the conductive structure to be formed later is formed in the second photoresist layer.
In step S103, the low-resistance silicon wafer and the filter chip are disposed opposite to each other, the second photoresist layer and the third photoresist layer are oriented to the surface of the filter chip on which the device is formed, and the second photoresist layer and the third photoresist layer are connected by low-temperature bonding. The second photoresist layer is bonded and connected with the metal layer on the surface of the filter chip to form a first connecting part, and the third photoresist layer is directly bonded and connected with the substrate of the filter chip to form a second connecting part.
In step S104, the low-resistance silicon wafer is removed by a thinning process.
In step S105, a first photoresist layer is formed on a surface of the second thin film layer facing away from the filter chip, and the first photoresist layer is patterned to expose a region of the second thin film layer where the first through hole is to be formed.
In step S106, the second thin film layer and the first thin film layer are etched with the first photoresist layer as a mask, so as to form a first through hole penetrating through the second through hole in the second photoresist layer.
In step S107, a conductive material is filled in the second via hole and the first via hole to form a conductive structure.
In step S108, an under bump metallization layer and solder balls electrically connected to the conductive structures are formed.
It will be evident to those skilled in the art that the utility model is not limited to the details of the foregoing illustrative embodiments, and that the present utility model may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the utility model being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned. Furthermore, it is evident that the word "comprising" does not exclude other elements, units or steps, and that the singular does not exclude a plurality. Various components, units or means recited in the system claims may also be implemented by means of software or hardware by means of one component, unit or means.
The foregoing disclosure is only illustrative of the preferred embodiments of the present utility model and is not to be construed as limiting the scope of the utility model, which is defined by the appended claims.
Claims (10)
1. A semiconductor wafer level package structure, the semiconductor wafer level package structure comprising:
the semiconductor chip comprises a semiconductor chip, a cap, a connecting structure, a conductive structure and a solder ball, wherein the cap is of a multilayer film structure;
the front surface of the semiconductor chip is opposite to the front surface of the cap, and connection is formed through the connection structure arranged between the front surface and the front surface of the cap;
the connecting structure comprises a first connecting part and a second connecting part, the first connecting part is electrically connected with the semiconductor chip, the second connecting part, the semiconductor chip and the cap enclose a sealing cavity, and a device area of the semiconductor chip is positioned in the sealing cavity;
a first through hole is formed in the position, corresponding to the first connecting part, of the cap, and the conductive structure is arranged in the first through hole and is electrically connected with the first connecting part;
the solder balls are formed on the back surface of the cap and are electrically connected with the conductive structures.
2. The semiconductor wafer level package according to claim 1, wherein the thickness of the multi-layer thin film structure is in the range of 10 μm to 20 μm.
3. The semiconductor wafer level package of claim 1, wherein:
the multilayer thin film structure includes a first thin film layer and a second thin film layer stacked along a thickness thereof, or the multilayer thin film structure includes first thin film layers and second thin film layers alternately arranged along a thickness thereof; wherein the materials of the first thin film layer and the second thin film layer have opposite stresses.
4. A semiconductor wafer level package according to claim 3, wherein:
the materials of the first film layer and the second film layer are inorganic insulating materials.
5. The semiconductor wafer level package according to claim 4, wherein:
one of the first thin film layer and the second thin film layer is a silicon dioxide layer, and the other is a silicon nitride layer.
6. The semiconductor wafer level package according to claim 5, wherein:
the ratio of the total thickness of the silicon dioxide layer to the total thickness of the silicon nitride layer in the multilayer thin film structure is greater than 2.
7. A semiconductor wafer level package according to claim 3, wherein:
the multi-layered thin film structure further includes an insulating layer formed on the first via sidewall, wherein one of the first thin film layer and the second thin film layer is a low-resistance semiconductor material and the other is an inorganic insulating material.
8. The semiconductor wafer level package of claim 7, wherein:
one of the first thin film layer and the second thin film layer is a low-resistance silicon layer, and the other is a silicon dioxide layer.
9. The semiconductor wafer level package according to any one of claims 3 to 8, wherein:
the multi-layer thin film structure further comprises a first photoresist layer formed on a surface of the structure formed by the first thin film layer and the second thin film layer, which is away from the semiconductor chip.
10. The semiconductor wafer level package of claim 1, wherein:
the first connecting part comprises a metal layer and a second photoresist layer which are connected through bonding, wherein the metal layer is positioned on the side of the semiconductor chip, the second photoresist layer is positioned on the side of the cap, a second through hole corresponding to the conductive structure is formed on the second photoresist layer, and the conductive structure extends from the first through hole to the second through hole and is electrically connected with the metal layer;
the second connection portion includes a third photoresist layer.
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| CN202223439266.5U CN219372401U (en) | 2022-12-20 | 2022-12-20 | Semiconductor wafer level packaging structure |
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| CN202223439266.5U CN219372401U (en) | 2022-12-20 | 2022-12-20 | Semiconductor wafer level packaging structure |
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