CN219372398U - Filtering net gape circuit - Google Patents

Filtering net gape circuit Download PDF

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Publication number
CN219372398U
CN219372398U CN202320547491.6U CN202320547491U CN219372398U CN 219372398 U CN219372398 U CN 219372398U CN 202320547491 U CN202320547491 U CN 202320547491U CN 219372398 U CN219372398 U CN 219372398U
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network interface
port
connecting end
signal connecting
capacitor
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邢省委
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Lingsi Innovation Shenzhen Co ltd
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Lingsi Innovation Shenzhen Co ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E40/00—Technologies for an efficient electrical power generation, transmission or distribution
    • Y02E40/40—Arrangements for reducing harmonics

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  • Filters And Equalizers (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Details Of Connecting Devices For Male And Female Coupling (AREA)

Abstract

The embodiment of the utility model discloses a filter network port circuit, which comprises a network interface chip, a filter circuit module and a network interface; the filter circuit module comprises a high-frequency filter unit, an electrical isolation unit and a common mode noise filter unit; a plurality of first patch capacitors are arranged in the high-frequency filtering unit; a plurality of second patch capacitors are arranged in the electrical isolation unit; a plurality of patch common-mode inductors are arranged in the common-mode noise filtering unit; the network interface chip, the filter circuit module and the network interface are sequentially and bidirectionally electrically connected; the high-frequency filtering unit, the electrical isolation unit and the common mode noise filtering unit can be matched to form a filtering circuit module according to different orders. The filter network port circuit provided by the utility model consists of the network interface chip, the filter circuit module and the network interface, and has simpler circuit structure and lower production cost.

Description

Filtering net gape circuit
Technical Field
The utility model relates to the technical field of electronic circuits, in particular to a filter network port circuit.
Background
With the development of communication technology, the home network of a common user has been in the giga ethernet age, and the distribution of the home internal network after the optical fiber is taken into the home is generally completed through devices such as a light cat, a router, a switch and the like, and the devices such as the light cat, the router, the switch and the like are all provided with network interfaces, because the wired network interfaces (also called network interfaces) are necessary interfaces for carrying out wired network transmission between the devices.
The traditional network port circuit generally comprises a network port transformer, a terminating resistor and a high-voltage capacitor, and is formed by interconnecting a network interface and a network interface chip, and the circuit structure is relatively complex. The traditional network port circuit can inhibit electromagnetic interference of a network port and ensure effective transmission of network port data. However, the size of the network port transformer is large, winding of the inner magnetic ring enameled wires and the like are basically finished manually, the production efficiency is low, and the positions of the winding of the magnetic rings and the placement of the magnetic rings in the network port transformer are not uniform, so that the consistency of products is difficult to ensure, and in addition, when the communication rate of the network port is increased to 2.5Gbps or more, the model selection difficulty of the network port transformer is high, so that the circuit cost is difficult to reduce. Therefore, a network port circuit needs to be redesigned, so that the circuit structure is simpler and the cost is lower.
Disclosure of Invention
In view of the above, the present utility model provides a filtering network port circuit, which is used for solving the problems of complex circuit structure and high production cost of the network port circuit in the prior art.
A filtering network port circuit comprises a network interface chip, a filtering circuit module and a network interface;
the filter circuit module comprises a high-frequency filter unit, an electrical isolation unit and a common mode noise filter unit;
a plurality of first patch capacitors are arranged in the high-frequency filtering unit; the method is used for restraining high-frequency components and noise of the network port signals;
a plurality of second patch capacitors are arranged in the electrical isolation unit; the method is used for inhibiting low-frequency noise of the network port signal;
a plurality of patch common-mode inductors are arranged in the common-mode noise filtering unit; the method is used for suppressing common mode noise of the network port signals;
the network interface chip, the filter circuit module and the network interface are sequentially and bidirectionally electrically connected;
the high-frequency filtering unit, the electrical isolation unit and the common mode noise filtering unit can be matched to form a filtering circuit module according to different orders.
Further, when the network interface chip and the network interface transmit network port signals, the data receiving and transmitting port of the network interface chip is in bidirectional electrical connection with the first signal connecting end of the high-frequency filtering unit, the second signal connecting end of the high-frequency filtering unit is in bidirectional electrical connection with the first signal connecting end of the electrical isolation unit, the second signal connecting end of the electrical isolation unit is in bidirectional electrical connection with the first signal connecting end of the common-mode noise filtering unit, and the second signal connecting end of the common-mode noise filtering unit is in bidirectional electrical connection with the data transmitting port of the network interface.
Further, when the network interface chip and the network interface transmit network port signals, the data receiving and transmitting port of the network interface chip is in bidirectional electrical connection with the first signal connecting end of the high-frequency filtering unit, the second signal connecting end of the high-frequency filtering unit is in bidirectional electrical connection with the first signal connecting end of the common-mode noise filtering unit, the second signal connecting end of the common-mode noise filtering unit is in bidirectional electrical connection with the first signal connecting end of the electrical isolation unit, and the second signal connecting end of the electrical isolation unit is in bidirectional electrical connection with the data transmission port of the network interface.
Further, when the network interface chip and the network interface transmit network port signals, the data receiving and transmitting port of the network interface chip is in bidirectional electrical connection with the first signal connecting end of the electrical isolation unit, the second signal connecting end of the electrical isolation unit is in bidirectional electrical connection with the first signal connecting end of the high-frequency filtering unit, the second signal connecting end of the high-frequency filtering unit is in bidirectional electrical connection with the first signal connecting end of the common-mode noise filtering unit, and the second signal connecting end of the common-mode noise filtering unit is in bidirectional electrical connection with the data transmission port of the network interface.
Further, when the network interface chip and the network interface transmit network port signals, the data receiving and transmitting port of the network interface chip is in bidirectional electrical connection with the first signal connecting end of the electrical isolation unit, the second signal connecting end of the electrical isolation unit is in bidirectional electrical connection with the first signal connecting end of the common mode noise filtering unit, the second signal connecting end of the common mode noise filtering unit is in bidirectional electrical connection with the first signal connecting end of the high frequency filtering unit, and the second signal connecting end of the high frequency filtering unit is in bidirectional electrical connection with the data transmission port of the network interface.
Further, when the network interface chip and the network interface transmit network port signals, the data receiving and transmitting port of the network interface chip is in bidirectional electrical connection with the first signal connecting end of the common mode noise filtering unit, the second signal connecting end of the common mode noise filtering unit is in bidirectional electrical connection with the first signal connecting end of the high frequency filtering unit, the second signal connecting end of the high frequency filtering unit is in bidirectional electrical connection with the first signal connecting end of the electrical isolation unit, and the second signal connecting end of the electrical isolation unit is in bidirectional electrical connection with the data transmission port of the network interface.
Further, when the network interface chip and the network interface transmit network port signals, the data receiving and transmitting port of the network interface chip is in bidirectional electrical connection with the first signal connecting end of the common mode noise filtering unit, the second signal connecting end of the common mode noise filtering unit is in bidirectional electrical connection with the first signal connecting end of the electrical isolation unit, the second signal connecting end of the electrical isolation unit is in bidirectional electrical connection with the first signal connecting end of the high frequency filtering unit, and the second signal connecting end of the high frequency filtering unit is in bidirectional electrical connection with the data transmitting port of the network interface.
Further, the capacity of each of the first patch capacitors is 0.1pF-1uF.
Further, the capacity of each second patch capacitor is 1nF-10uF.
The implementation of the embodiment of the utility model has the following beneficial effects:
1. the patch common-mode inductor provided by the utility model replaces a network port transformer in the prior art, and because the patch common-mode inductor is automatically produced by special equipment without manual intervention, the produced patch common-mode inductor has good consistency, small volume and low production cost;
2. the filter network port circuit provided by the utility model consists of the network interface chip, the filter circuit module and the network interface, and has simpler circuit structure and lower production cost.
Drawings
In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the utility model, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a first circuit schematic diagram of a filter port circuit in the present application;
FIG. 2 is a second circuit schematic of the filter port circuit of the present application;
FIG. 3 is a third circuit schematic of the filter port circuit of the present application;
FIG. 4 is a fourth schematic diagram of a filter port circuit of the present application;
FIG. 5 is a fifth circuit schematic of the filter port circuit of the present application;
fig. 6 is a sixth circuit schematic of the filtering network port circuit in the present application.
Reference numerals:
10 a network interface chip; 20. a filter circuit module; 30. a network interface;
21. a high-frequency filtering unit; 22. an electrical isolation unit; 23. and a common mode noise filtering unit.
Detailed Description
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used in the description of the applications herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application; the terms "comprising" and "having" and any variations thereof in the description and claims of the present application and in the description of the figures above are intended to cover non-exclusive inclusions. The terms first, second and the like in the description and in the claims or in the above-described figures, are used for distinguishing between different objects and not necessarily for describing a sequential or chronological order.
Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the present application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.
In order to better understand the technical solutions of the present application, the following description will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the accompanying drawings.
Referring to fig. 1-6, as an embodiment, a filter network interface circuit includes a network interface chip 10, a filter circuit module 20, and a network interface 30;
the filter circuit module 20 includes a high-frequency filter unit 21, an electrical isolation unit 22, and a common mode noise filter unit 23;
a plurality of first patch capacitors are arranged in the high-frequency filtering unit 21; the method is used for restraining high-frequency components and noise of the network port signals;
a plurality of second patch capacitors are arranged in the electrical isolation unit 22; the method is used for inhibiting low-frequency noise of the network port signal;
a plurality of patch common mode inductors are arranged in the common mode noise filtering unit 23; the method is used for suppressing common mode noise of the network port signals;
the network interface chip 10, the filter circuit module 20 and the network interface 30 are sequentially and bi-directionally electrically connected;
the high frequency filtering unit 21, the electrical isolation unit 22 and the common mode noise filtering unit 23 may be mated in different orders to form the filtering circuit module 20.
In this embodiment, the network interface circuit in the prior art is composed of a network interface chip, a network interface transformer, a BOB-SMITH termination resistor, a 2KV high-voltage capacitor, and a network interface. Therefore, compared with the network port circuit in the prior art, the filtering network port circuit has the effects of inhibiting electromagnetic interference of a network port and guaranteeing effective transmission of network port data, but the high-frequency filtering unit 21 and the electric isolation unit 22 can replace a BOB-SMITH terminating resistor and a 2KV high-voltage capacitor, and the common mode noise filtering unit 23 can replace a network port transformer, so that a large number of BOB-SMITH terminating resistors and 2KV high-voltage capacitors are saved, the circuit structure of the filtering network port circuit is simpler, and the production and maintenance cost is lower.
The network interface chip 10 can transmit the network interface signal to the network interface 30, and the network interface chip 10 can also receive the network interface signal sent by the network interface 30.
The network interface chip 10 is an ethernet physical layer chip, and has any of MT7621A chip, MT7631A chip, RTL8367 chip, RTL8198 chip, RTL8211 chip, and QCA8337 chip, and has a plurality of data transceiver ports, for clarity of description, 8 data transceiver ports are described as B1 pin, B2 pin, B3 pin, B4 pin, B5 pin, B6 pin, B7 pin, and B8 pin, respectively; the network interface 30 is an RJ45 interface having eight pins, A1 pin, A2 pin, A3 pin, A4 pin, A5 pin, A6 pin, A7 pin, and A8 pin, respectively.
The high-frequency filter unit 21 has eight first patch capacitors, namely a capacitor C11, a capacitor C12, a capacitor C13, a capacitor C14, a capacitor C15, a capacitor C16, a capacitor C17 and a capacitor C18; the electrical isolation unit 22 has eight second patch capacitors, which are a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, and a capacitor C8; the common mode noise filtering unit 23 has four patch common mode inductances, which are respectively an inductance CMC1, an inductance CMC2, an inductance CMC3 and an inductance CMC4, wherein each inductance has four ports, which are respectively a first port, a second port, a third port and a fourth port, and the first port and the second port belong to the same name end. The filter network port circuit is a passive circuit, so that the first patch capacitor, the second patch capacitor and the patch common mode inductance are all nonpolar.
Referring to fig. 1, as an embodiment, when the network interface chip 10 and the network interface 30 bidirectionally transmit the network interface signal, the data transceiver port of the network interface chip 10 is bidirectionally electrically connected to the first signal connection end of the high-frequency filtering unit 21, the second signal connection end of the high-frequency filtering unit 21 is bidirectionally electrically connected to the first signal connection end of the electrical isolation unit 22, the second signal connection end of the electrical isolation unit 22 is bidirectionally electrically connected to the first signal connection end of the common-mode noise filtering unit 23, and the second signal connection end of the common-mode noise filtering unit 23 is bidirectionally electrically connected to the data transmission port of the network interface 30.
The first signal connection end and the second signal connection end of the high-frequency filtering unit 21, the first signal connection end and the second signal connection end of the electrical isolation unit 22, and the first signal connection end and the second signal connection end of the common mode noise filtering unit 23 are all used for transmitting network port signals.
In this embodiment, pin B8 of the network interface chip 10 is connected to one end of the capacitor C1, while pin B8 is connected to one end of the capacitor C11, the other end of the capacitor C11 is grounded, the other end of the capacitor C1 is connected to the first port of the inductor CMC1, the third port of the inductor CMC1 is connected to pin A8 of the network interface 30, pin A7 of the network interface 30 is connected to the fourth port of the inductor CMC1, the second port of the inductor CMC1 is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to pin B7 of the network interface chip 10, while pin B7 is connected to one end of the capacitor C12, and the other end of the capacitor C12 is grounded;
the pin B6 of the network interface chip 10 is connected with one end of a capacitor C3, meanwhile, the pin B6 is connected with one end of a capacitor C13, the other end of the capacitor C13 is grounded, the other end of the capacitor C3 is connected with a first port of an inductor CMC2, a third port of the inductor CMC2 is connected with the pin A5 of the network interface 30, the pin A4 of the network interface 30 is connected with a fourth port of the inductor CMC2, a second port of the inductor CMC2 is connected with one end of a capacitor C4, the other end of the capacitor C4 is connected with the pin B5 of the network interface chip 10, meanwhile, the pin B5 is connected with one end of a capacitor C14, and the other end of the capacitor C14 is grounded;
the pin B4 of the network interface chip 10 is connected with one end of a capacitor C5, meanwhile, the pin B4 is connected with one end of a capacitor C15, the other end of the capacitor C15 is grounded, the other end of the capacitor C5 is connected with a first port of an inductance CMC3, a third port of the inductance CMC3 is connected with the pin A6 of the network interface 30, the pin A3 of the network interface 30 is connected with a fourth port of the inductance CMC3, a second port of the inductance CMC3 is connected with one end of the capacitor C6, the other end of the capacitor C6 is connected with the pin B3 of the network interface chip 10, meanwhile, the pin B3 is connected with one end of a capacitor C16, and the other end of the capacitor C16 is grounded;
the pin B2 of the network interface chip 10 is connected with one end of a capacitor C7, meanwhile, the pin B2 is connected with one end of a capacitor C17, the other end of the capacitor C17 is grounded, the other end of the capacitor C7 is connected with a first port of an inductance CMC4, a third port of the inductance CMC4 is connected with the pin A2 of the network interface 30, the pin A1 of the network interface 30 is connected with a fourth port of the inductance CMC4, a second port of the inductance CMC4 is connected with one end of a capacitor C8, the other end of the capacitor C8 is connected with the pin B1 of the network interface chip 10, meanwhile, the pin B1 is connected with one end of a capacitor C18, and the other end of the capacitor C18 is grounded.
Referring to fig. 2, as an embodiment, when the network interface chip 10 and the network interface 30 bidirectionally transmit the network interface signal, the data transceiver port of the network interface chip 10 is bidirectionally electrically connected to the first signal connection end of the high-frequency filtering unit 21, the second signal connection end of the high-frequency filtering unit 21 is bidirectionally electrically connected to the first signal connection end of the common-mode noise filtering unit 23, the second signal connection end of the common-mode noise filtering unit 23 is bidirectionally electrically connected to the first signal connection end of the electrical isolation unit 22, and the second signal connection end of the electrical isolation unit 22 is bidirectionally electrically connected to the data transmission port of the network interface 30.
In this embodiment, pin B8 of the network interface chip 10 is connected to the first port of the inductance CMC1, while pin B8 is connected to one end of the capacitor C11, the other end of the capacitor C11 is grounded, the third port of the inductance CMC1 is connected to one end of the capacitor C1, the other end of the capacitor C1 is connected to pin A8 of the network interface 30, pin A7 of the network interface 30 is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the fourth port of the inductance CMC1, the second port of the inductance CMC1 is connected to pin B7 of the network interface chip 10, while pin B7 is connected to one end of the capacitor C12, and the other end of the capacitor C12 is grounded;
the pin B6 of the network interface chip 10 is connected with a first port of the inductance CMC2, meanwhile, the pin B6 is connected with one end of a capacitor C13, the other end of the capacitor C13 is grounded, a third port of the inductance CMC2 is connected with one end of a capacitor C3, the other end of the capacitor C3 is connected with the pin A5 of the network interface 30, the pin A4 of the network interface 30 is connected with one end of the capacitor C4, the other end of the capacitor C4 is connected with a fourth port of the inductance CMC2, a second port of the inductance CMC2 is connected with the pin B5 of the network interface chip 10, meanwhile, the pin B5 is connected with one end of a capacitor C14, and the other end of the capacitor C14 is grounded;
the pin B4 of the network interface chip 10 is connected with a first port of the inductance CMC3, meanwhile, the pin B4 is connected with one end of a capacitor C15, the other end of the capacitor C15 is grounded, a third port of the inductance CMC3 is connected with one end of a capacitor C5, the other end of the capacitor C5 is connected with the pin A6 of the network interface 30, the pin A3 of the network interface 30 is connected with one end of the capacitor C6, the other end of the capacitor C6 is connected with a fourth port of the inductance CMC3, a second port of the inductance CMC3 is connected with the pin B3 of the network interface chip 10, meanwhile, the pin B3 is connected with one end of a capacitor C16, and the other end of the capacitor C16 is grounded;
the pin B2 of the network interface chip 10 is connected with the first port of the inductance CMC4, meanwhile, the pin B2 is connected with one end of the capacitor C17, the other end of the capacitor C17 is grounded, the third port of the inductance CMC4 is connected with one end of the capacitor C7, the other end of the capacitor C7 is connected with the pin A2 of the network interface 30, the pin A1 of the network interface 30 is connected with one end of the capacitor C8, the other end of the capacitor C8 is connected with the fourth port of the inductance CMC4, the second port of the inductance CMC4 is connected with the pin B1 of the network interface chip 10, meanwhile, the pin B1 is connected with one end of the capacitor C18, and the other end of the capacitor C18 is grounded.
Referring to fig. 3, as an embodiment, when the network interface chip 10 and the network interface 30 bidirectionally transmit the network interface signal, the data transceiver port of the network interface chip 10 is bidirectionally electrically connected to the first signal connection end of the electrical isolation unit 22, the second signal connection end of the electrical isolation unit 22 is bidirectionally electrically connected to the first signal connection end of the high-frequency filtering unit 21, the second signal connection end of the high-frequency filtering unit 21 is bidirectionally electrically connected to the first signal connection end of the common-mode noise filtering unit 23, and the second signal connection end of the common-mode noise filtering unit 23 is bidirectionally electrically connected to the data transmission port of the network interface 30.
In this embodiment, pin B8 of the network interface chip 10 is connected to one end of capacitor C1, the other end of capacitor C1 is connected to a first port of capacitor C1, while the other end of capacitor C1 is connected to one end of capacitor C11, the other end of capacitor C11 is grounded, a third port of capacitor C1 is connected to pin A8 of the network interface 30, pin A7 of the network interface 30 is connected to a fourth port of capacitor CMC1, a second port of capacitor CMC1 is connected to one end of capacitor C2, while the second port of capacitor CMC1 is connected to one end of capacitor C12, the other end of capacitor C12 is grounded, and the other end of capacitor C2 is connected to pin B7 of the network interface chip 10;
the pin B6 of the network interface chip 10 is connected with one end of a capacitor C3, the other end of the capacitor C3 is connected with a first port of an inductance CMC2, meanwhile, the other end of the capacitor C3 is connected with one end of a capacitor C13, the other end of the capacitor C13 is grounded, a third port of the inductance CMC2 is connected with the pin A5 of the network interface 30, the pin A4 of the network interface 30 is connected with a fourth port of the inductance CMC2, a second port of the inductance CMC2 is connected with one end of the capacitor C4, meanwhile, a second port of the inductance CMC1 is connected with one end of the capacitor C14, the other end of the capacitor C14 is grounded, and the other end of the capacitor C4 is connected with the pin B5 of the network interface chip 10;
the pin B4 of the network interface chip 10 is connected with one end of a capacitor C5, the other end of the capacitor C5 is connected with a first port of an inductance CMC3, meanwhile, the other end of the capacitor C5 is connected with one end of a capacitor C15, the other end of the capacitor C15 is grounded, a third port of the inductance CMC3 is connected with the pin A6 of the network interface 30, the pin A3 of the network interface 30 is connected with a fourth port of the inductance CMC3, a second port of the inductance CMC3 is connected with one end of the capacitor C6, meanwhile, the second port of the inductance CMC3 is connected with one end of the capacitor C16, the other end of the capacitor C16 is grounded, and the other end of the capacitor C6 is connected with the pin B3 of the network interface chip 10;
the pin B2 of the network interface chip 10 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with a first port of an inductance CMC4, meanwhile, the other end of the capacitor C7 is connected with one end of a capacitor C17, the other end of the capacitor C17 is grounded, a third port of the inductance CMC4 is connected with the pin A2 of the network interface 30, the pin A1 of the network interface 30 is connected with a fourth port of the inductance CMC4, a second port of the inductance CMC4 is connected with one end of a capacitor C8, meanwhile, the second port of the inductance CMC4 is connected with one end of a capacitor C18, the other end of the capacitor C18 is grounded, and the other end of the capacitor C8 is connected with the pin B1 of the network interface chip 10.
Referring to fig. 4, as an embodiment, when the network interface chip 10 and the network interface 30 bidirectionally transmit the network interface signal, the data transceiver port of the network interface chip 10 is bidirectionally and electrically connected to the first signal connection end of the electrical isolation unit 22, the second signal connection end of the electrical isolation unit 22 is bidirectionally and electrically connected to the first signal connection end of the common mode noise filter unit 23, the second signal connection end of the common mode noise filter unit 23 is bidirectionally and electrically connected to the first signal connection end of the high frequency filter unit 21, and the second signal connection end of the high frequency filter unit 21 is bidirectionally and electrically connected to the data transmission port of the network interface 30.
In this embodiment, pin B8 of the network interface chip 10 is connected to one end of capacitor C1, the other end of capacitor C1 is connected to the first port of inductor CMC1, the third port of inductor CMC1 is connected to pin A8 of the network interface 30, while pin A8 is connected to one end of capacitor C11, the other end of capacitor C11 is grounded, pin A7 of the network interface 30 is connected to the fourth port of inductor CMC1, while pin A7 is connected to one end of capacitor C12, the other end of capacitor C12 is grounded, the second port of inductor CMC1 is connected to one end of capacitor C2, and the other end of capacitor C2 is connected to pin B7 of the network interface chip 10;
the pin B6 of the network interface chip 10 is connected with one end of a capacitor C3, the other end of the capacitor C3 is connected with a first port of an inductance CMC2, a third port of the inductance CMC2 is connected with the pin A5 of the network interface 30, meanwhile, the pin A5 is connected with one end of a capacitor C13, the other end of the capacitor C13 is grounded, the pin A4 of the network interface 30 is connected with a fourth port of the inductance CMC2, meanwhile, the pin A4 is connected with one end of a capacitor C14, the other end of the capacitor C14 is grounded, a second port of the inductance CMC2 is connected with one end of a capacitor C4, and the other end of the capacitor C4 is connected with the pin B5 of the network interface chip 10;
the pin B4 of the network interface chip 10 is connected with one end of a capacitor C5, the other end of the capacitor C5 is connected with a first port of an inductance CMC3, a third port of the inductance CMC3 is connected with the pin A6 of the network interface 30, meanwhile, the pin A6 is connected with one end of a capacitor C15, the other end of the capacitor C15 is grounded, the pin A3 of the network interface 30 is connected with a fourth port of the inductance CMC3, meanwhile, the pin A3 is connected with one end of a capacitor C16, the other end of the capacitor C16 is grounded, a second port of the inductance CMC3 is connected with one end of a capacitor C6, and the other end of the capacitor C6 is connected with the pin B3 of the network interface chip 10;
the pin B2 of the network interface chip 10 is connected with one end of a capacitor C7, the other end of the capacitor C7 is connected with a first port of an inductance CMC4, a third port of the inductance CMC4 is connected with the pin A2 of the network interface 30, meanwhile, the pin A2 is connected with one end of a capacitor C17, the other end of the capacitor C17 is grounded, the pin A1 of the network interface 30 is connected with a fourth port of the inductance CMC4, meanwhile, the pin A1 is connected with one end of a capacitor C18, the other end of the capacitor C18 is grounded, a second port of the inductance CMC4 is connected with one end of a capacitor C8, and the other end of the capacitor C8 is connected with the pin B1 of the network interface chip 10.
Referring to fig. 5, as an embodiment, when the network interface chip 10 and the network interface 30 bidirectionally transmit the network interface signal, the data transceiver port of the network interface chip 10 is bidirectionally electrically connected to the first signal connection end of the common mode noise filter unit 23, the second signal connection end of the common mode noise filter unit 23 is bidirectionally electrically connected to the first signal connection end of the high frequency filter unit 21, the second signal connection end of the high frequency filter unit 21 is bidirectionally electrically connected to the first signal connection end of the electrical isolation unit 22, and the second signal connection end of the electrical isolation unit 22 is bidirectionally electrically connected to the data transmission port of the network interface 30.
In this embodiment, pin B8 of the network interface chip 10 is connected to the first port of the inductance CMC1, the third port of the inductance CMC1 is connected to one end of the capacitor C1, while the third port of the inductance CMC1 is connected to one end of the capacitor C11, the other end of the capacitor C11 is grounded, the other end of the capacitor C1 is connected to pin A8 of the network interface 30, pin A7 of the network interface 30 is connected to one end of the capacitor C2, the other end of the capacitor C2 is connected to the fourth port of the inductance CMC1, while the fourth port of the inductance CMC1 is connected to one end of the capacitor C12, the other end of the capacitor C12 is grounded, and the second port of the inductance CMC1 is connected to pin B7 of the network interface chip 10;
the pin B6 of the network interface chip 10 is connected with the first port of the inductance CMC2, the third port of the inductance CMC2 is connected with one end of the capacitor C3, meanwhile, the third port of the inductance CMC2 is connected with one end of the capacitor C13, the other end of the capacitor C13 is grounded, the other end of the capacitor C3 is connected with the pin A5 of the network interface 30, the pin A4 of the network interface 30 is connected with one end of the capacitor C4, the other end of the capacitor C4 is connected with the fourth port of the inductance CMC2, meanwhile, the fourth port of the inductance CMC2 is connected with one end of the capacitor C14, the other end of the capacitor C14 is grounded, and the second port of the inductance CMC2 is connected with the pin B5 of the network interface chip 10;
the pin B4 of the network interface chip 10 is connected with the first port of the inductance CMC3, the third port of the inductance CMC3 is connected with one end of a capacitor C5, meanwhile, the third port of the inductance CMC3 is connected with one end of a capacitor C15, the other end of the capacitor C15 is grounded, the other end of the capacitor C5 is connected with the pin A6 of the network interface 30, the pin A3 of the network interface 30 is connected with one end of the capacitor C6, the other end of the capacitor C6 is connected with the fourth port of the inductance CMC3, meanwhile, the fourth port of the inductance CMC3 is connected with one end of a capacitor C16, the other end of the capacitor C16 is grounded, and the second port of the inductance CMC3 is connected with the pin B3 of the network interface chip 10;
the pin B2 of the network interface chip 10 is connected with the first port of the inductance CMC4, the third port of the inductance CMC4 is connected with one end of the capacitor C7, the third port of the inductance CMC4 is connected with one end of the capacitor C17, the other end of the capacitor C17 is grounded, the other end of the capacitor C7 is connected with the pin A2 of the network interface 30, the pin A1 of the network interface 30 is connected with one end of the capacitor C8, the other end of the capacitor C8 is connected with the fourth port of the inductance CMC4, the fourth port of the inductance CMC4 is connected with one end of the capacitor C18, the other end of the capacitor C18 is grounded, and the second port of the inductance CMC4 is connected with the pin B1 of the network interface chip 10.
Referring to fig. 6, as an embodiment, when the network interface chip 10 and the network interface 30 bidirectionally transmit the network interface signal, the data transceiver port of the network interface chip 10 is bidirectionally electrically connected to the first signal connection end of the common mode noise filter unit 23, the second signal connection end of the common mode noise filter unit 23 is bidirectionally electrically connected to the first signal connection end of the electrical isolation unit 22, the second signal connection end of the electrical isolation unit 22 is bidirectionally electrically connected to the first signal connection end of the high frequency filter unit 21, and the second signal connection end of the high frequency filter unit 21 is bidirectionally electrically connected to the data transmission port of the network interface 30.
In this embodiment, pin B8 of the network interface chip 10 is connected to the first port of the inductance CMC1, the third port of the inductance CMC1 is connected to one end of the capacitance C1, the other end of the capacitance C1 is connected to pin A8 of the network interface 30, while pin A8 is connected to one end of the capacitance C11, the other end of the capacitance C11 is grounded, pin A7 of the network interface 30 is connected to one end of the capacitance C2, while pin A7 is connected to one end of the capacitance C12, the other end of the capacitance C12 is grounded, the other end of the capacitance C2 is connected to the fourth port of the inductance CMC1, and the second port of the inductance CMC1 is connected to pin B7 of the network interface chip 10;
the pin B6 of the network interface chip 10 is connected with the first port of the inductance CMC2, the third port of the inductance CMC2 is connected with one end of the capacitance C3, the other end of the capacitance C3 is connected with the pin A5 of the network interface 30, the pin A5 is connected with one end of the capacitance C13, the other end of the capacitance C13 is grounded, the pin A4 of the network interface 30 is connected with one end of the capacitance C4, the pin A4 is connected with one end of the capacitance C14, the other end of the capacitance C14 is grounded, the other end of the capacitance C4 is connected with the fourth port of the inductance CMC2, and the second port of the inductance CMC2 is connected with the pin B5 of the network interface chip 10;
the pin B4 of the network interface chip 10 is connected with the first port of the inductance CMC3, the third port of the inductance CMC3 is connected with one end of a capacitor C5, the other end of the capacitor C5 is connected with the pin A6 of the network interface 30, the pin A6 is connected with one end of a capacitor C15, the other end of the capacitor C15 is grounded, the pin A3 of the network interface 30 is connected with one end of a capacitor C6, the pin A3 is connected with one end of a capacitor C16, the other end of the capacitor C16 is grounded, the other end of the capacitor C6 is connected with the fourth port of the inductance CMC3, and the second port of the inductance CMC3 is connected with the pin B3 of the network interface chip 10;
the pin B2 of the network interface chip 10 is connected with the first port of the inductance CMC4, the third port of the inductance CMC4 is connected with one end of the capacitance C7, the other end of the capacitance C7 is connected with the pin A2 of the network interface 30, meanwhile, the pin A2 is connected with one end of the capacitance C17, the other end of the capacitance C17 is grounded, the pin A1 of the network interface 30 is connected with one end of the capacitance C8, meanwhile, the pin A1 is connected with one end of the capacitance C18, the other end of the capacitance C18 is grounded, the other end of the capacitance C8 is connected with the fourth port of the inductance CMC4, and the second port of the inductance CMC4 is connected with the pin B1 of the network interface chip 10.
Referring to fig. 1-6, as an example, each of the first patch capacitors has a capacity of 0.1pF-1uF; the capacity of each second patch capacitor is 1nF-10uF.
The patch common-mode inductor is automatically produced by special equipment without manual intervention, so that the produced patch common-mode inductor has better consistency than a network port transformer in the prior art, smaller volume and lower production cost (the special equipment is a common-mode inductor intelligent winding machine).
It is apparent that the embodiments described above are only some embodiments of the present application, but not all embodiments, the preferred embodiments of the present application are given in the drawings, but not limiting the patent scope of the present application. This application may be embodied in many different forms, but rather, embodiments are provided in order to provide a more thorough understanding of the present disclosure. Although the present application has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing, or equivalents may be substituted for elements thereof. All equivalent structures made by the specification and the drawings of the application are directly or indirectly applied to other related technical fields, and are also within the protection scope of the application.

Claims (9)

1. The filtering network port circuit is characterized by comprising a network interface chip (10), a filtering circuit module (20) and a network interface (30);
the filter circuit module (20) comprises a high-frequency filter unit (21), an electrical isolation unit (22) and a common mode noise filter unit (23);
a plurality of first patch capacitors are arranged in the high-frequency filtering unit (21); the method is used for restraining high-frequency components and noise of the network port signals;
a plurality of second patch capacitors are arranged in the electrical isolation unit (22); the method is used for inhibiting low-frequency noise of the network port signal;
a plurality of patch common mode inductors are arranged in the common mode noise filtering unit (23); the method is used for suppressing common mode noise of the network port signals;
the network interface chip (10), the filter circuit module (20) and the network interface (30) are sequentially and bidirectionally electrically connected;
the high-frequency filtering unit (21), the electrical isolation unit (22) and the common-mode noise filtering unit (23) can be matched to form a filtering circuit module (20) according to different orders.
2. The filter port circuit of claim 1, wherein,
when network interface signals are transmitted between the network interface chip (10) and the network interface (30), a data receiving and transmitting port of the network interface chip (10) is in bidirectional electrical connection with a first signal connecting end of the high-frequency filtering unit (21), a second signal connecting end of the high-frequency filtering unit (21) is in bidirectional electrical connection with a first signal connecting end of the electrical isolation unit (22), a second signal connecting end of the electrical isolation unit (22) is in bidirectional electrical connection with a first signal connecting end of the common-mode noise filtering unit (23), and a second signal connecting end of the common-mode noise filtering unit (23) is in bidirectional electrical connection with a data transmission port of the network interface (30).
3. The filter port circuit of claim 1, wherein,
when network interface signals are transmitted between the network interface chip (10) and the network interface (30), a data receiving and transmitting port of the network interface chip (10) is in bidirectional electrical connection with a first signal connecting end of the high-frequency filtering unit (21), a second signal connecting end of the high-frequency filtering unit (21) is in bidirectional electrical connection with a first signal connecting end of the common-mode noise filtering unit (23), a second signal connecting end of the common-mode noise filtering unit (23) is in bidirectional electrical connection with a first signal connecting end of the electrical isolation unit (22), and a second signal connecting end of the electrical isolation unit (22) is in bidirectional electrical connection with a data transmission port of the network interface (30).
4. The filter port circuit of claim 1, wherein,
when network interface signals are transmitted between the network interface chip (10) and the network interface (30), the data receiving and transmitting port of the network interface chip (10) is in bidirectional electrical connection with the first signal connecting end of the electrical isolation unit (22), the second signal connecting end of the electrical isolation unit (22) is in bidirectional electrical connection with the first signal connecting end of the high-frequency filtering unit (21), the second signal connecting end of the high-frequency filtering unit (21) is in bidirectional electrical connection with the first signal connecting end of the common-mode noise filtering unit (23), and the second signal connecting end of the common-mode noise filtering unit (23) is in bidirectional electrical connection with the data transmission port of the network interface (30).
5. The filter port circuit of claim 1, wherein,
when network interface signals are transmitted between the network interface chip (10) and the network interface (30), the data receiving and transmitting port of the network interface chip (10) is in bidirectional electrical connection with the first signal connecting end of the electrical isolation unit (22), the second signal connecting end of the electrical isolation unit (22) is in bidirectional electrical connection with the first signal connecting end of the common mode noise filtering unit (23), the second signal connecting end of the common mode noise filtering unit (23) is in bidirectional electrical connection with the first signal connecting end of the high frequency filtering unit (21), and the second signal connecting end of the high frequency filtering unit (21) is in bidirectional electrical connection with the data transmission port of the network interface (30).
6. The filter port circuit of claim 1, wherein,
when network interface signals are transmitted between the network interface chip (10) and the network interface (30), a data receiving and transmitting port of the network interface chip (10) is in bidirectional electrical connection with a first signal connecting end of the common mode noise filtering unit (23), a second signal connecting end of the common mode noise filtering unit (23) is in bidirectional electrical connection with a first signal connecting end of the high frequency filtering unit (21), a second signal connecting end of the high frequency filtering unit (21) is in bidirectional electrical connection with a first signal connecting end of the electrical isolation unit (22), and a second signal connecting end of the electrical isolation unit (22) is in bidirectional electrical connection with a data transmission port of the network interface (30).
7. The filter port circuit of claim 1, wherein,
when network interface signals are transmitted between the network interface chip (10) and the network interface (30), a data receiving and transmitting port of the network interface chip (10) is in bidirectional electrical connection with a first signal connecting end of the common mode noise filtering unit (23), a second signal connecting end of the common mode noise filtering unit (23) is in bidirectional electrical connection with a first signal connecting end of the electrical isolation unit (22), a second signal connecting end of the electrical isolation unit (22) is in bidirectional electrical connection with a first signal connecting end of the high frequency filtering unit (21), and a second signal connecting end of the high frequency filtering unit (21) is in bidirectional electrical connection with a data transmission port of the network interface (30).
8. The filter portal circuit of any of claims 1-7,
the capacity of each first patch capacitor is 0.1pF-1uF.
9. The filter portal circuit of any of claims 1-7,
the capacity of each second patch capacitor is 1nF-10uF.
CN202320547491.6U 2023-03-20 2023-03-20 Filtering net gape circuit Active CN219372398U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202320547491.6U CN219372398U (en) 2023-03-20 2023-03-20 Filtering net gape circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202320547491.6U CN219372398U (en) 2023-03-20 2023-03-20 Filtering net gape circuit

Publications (1)

Publication Number Publication Date
CN219372398U true CN219372398U (en) 2023-07-18

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Family Applications (1)

Application Number Title Priority Date Filing Date
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