CN219370312U

CN219370312U - Host system and power supply control circuit thereof

Info

Publication number: CN219370312U
Application number: CN202320261649.3U
Authority: CN
Inventors: 吴景芳; 易博; 罗七一
Original assignee: Cardiopower Medtech Shanghai Co ltd
Current assignee: Cardiopower Medtech Shanghai Co ltd
Priority date: 2023-02-20
Filing date: 2023-02-20
Publication date: 2023-07-18
Anticipated expiration: 2033-02-20

Abstract

The utility model provides a host system and a power supply control circuit thereof. The power switch is pressed again after the host module is started to enable the power control circuit to run a shutdown mode, the processing module detects that the power switch is pressed again to generate a shutdown instruction, a user can determine whether the host module is required to be shut down according to the shutdown instruction, if the user determines to perform shutdown processing, the processing module controls the host module to shut down, and the processing module drives the driving module to output a cutoff signal after the host module is shut down, so that the power tube is cut off, and further the first voltage can not supply power to the processing module and the host module any more, so that the shutdown instruction for confirming shutdown by the user and the process for confirming that the processing module drives the driving module to cut off the power tube in a feedback manner after the shutdown are increased, the safety of the shutdown process of the system is ensured, and the host module is prevented from being accidentally powered down due to the fact that the power switch is pressed by mistake.

Description

Host system and power supply control circuit thereof

Technical Field

The present utility model relates to the field of power control technologies, and in particular, to a host system and a power control circuit thereof.

Background

At present, a power switch of a computer host is a hard switch, a user can start a computer by pressing the hard switch, and can shut down the computer by pressing the hard switch again, and the set operation mode is not suitable for equipment with higher safety requirements, because the hard switch is easily pressed by mistake to cause the computer host to be started or shut down by accident, thereby causing serious consequences. In addition, the current computer host needs to occupy an I/O interface with respect to power on, power off and power switch detection, which is not beneficial to saving hardware interface resources.

Disclosure of Invention

The utility model aims to provide a host system and a power supply control circuit thereof, which are used for solving the problem that the current operation setting mode of a power supply switch of a computer host easily causes the computer host to be started or shut down by mistake.

In order to solve the above technical problem, according to a first aspect of the present utility model, there is provided a power supply control circuit, comprising:

the input end of the power tube is used for acquiring a first voltage, and the output end of the power tube is used for being externally connected with a host module;

the driving module outputs a conducting signal to conduct the power tube or outputs a cutting-off signal to cut off the power tube; the driving module is provided with a power switch, and the driving module outputs the conducting signal after the power switch is pressed;

The processing module is connected to the output end of the power tube and externally connected with the host module, and is used for detecting the pressing state of the power switch;

the power supply control circuit is provided with a startup mode and a shutdown mode;

the boot-up mode is configured to: the power switch is pressed, the driving module outputs the conduction signal to enable the processing module to be powered by the first voltage, and then the processing module drives the driving module to continuously output the conduction signal, and the processing module starts the host module;

the shutdown mode is configured to: the processing module detects that the power switch is pressed after the host module is started, and then the processing module generates a shutdown instruction for indicating or driving the host module to shutdown, and drives the driving module to output the shutdown signal after the host module is shut down.

Optionally, the boot-up mode is further configured to: and after the processing module detects that the pressed time of the power switch reaches the preset time, the processing module starts the host module.

Optionally, the processing module includes a voltage adjustment unit and a logic processor; the voltage adjusting unit is connected between the output end of the power tube and the logic processor, and the logic processor is used for externally connecting the host module; the voltage adjusting unit is used for adjusting the first voltage to a third voltage so as to supply power to the logic processor.

Optionally, the driving module includes a first sub-stage circuit and a second sub-stage circuit;

the first sub-stage circuit is used for being connected with a power supply, the power supply is used for providing the first voltage, the first sub-stage circuit is provided with a second diode, the power switch is arranged on the first sub-stage circuit, and when the power switch is pressed, the first sub-stage circuit forms a closed loop, so that the conducting signal is generated at the forward end of the second diode; when the power switch is not pressed, the first sub-stage circuit is open circuit so as to generate the cut-off signal;

the second sub-stage circuit is provided with a first switching tube, and when the first switching tube is conducted, the second sub-stage circuit is provided with a closed loop so as to generate the conducting signal; when the first switching tube is cut off, the second sub-stage circuit is opened so as to generate the cut-off signal; the processing module controls the first switching tube to be switched on or switched off.

Optionally, the first sub-level circuit includes first resistance, second diode and second resistance, first voltage is obtained to the one end of first resistance, the other end of first resistance is connected the forward end of second diode, the reverse end of second diode is used for passing through switch ground connection, the one end of second resistance is connected the forward end of second diode, the other end of second resistance is connected the drive end of power tube.

Optionally, the second sub-stage circuit further includes a sixth resistor and a seventh resistor, where the sixth resistor and the seventh resistor are connected in series, and then the first voltage is obtained through the sixth resistor, and one end of the seventh resistor, which is not connected to the sixth resistor, is used for grounding through the first switch tube.

Optionally, the first resistor and the sixth resistor are the same resistor, and the second resistor and the seventh resistor are the same resistor.

Optionally, the processing module generates a second voltage after the power tube is turned on, and the processing module provides a first reference voltage or a second reference voltage after the power tube is turned on;

when the processing module generates the second voltage and provides the first reference voltage, the processing module conducts the first switching tube;

the processing module turns off the first switching tube when the processing module generates the second voltage and provides the second reference voltage.

Optionally, the second voltage and the third voltage are the same voltage.

Optionally, the processing module includes a third sub-stage circuit, a first end of the third sub-stage circuit is connected to the second voltage, and a second end of the third sub-stage circuit is connected to the first reference voltage or the second reference voltage; when the third sub-stage circuit is connected to the first reference voltage, the third sub-stage circuit forms a closed loop to generate a first bias signal for conducting the first switch tube; when the third sub-stage circuit is connected to the second reference voltage, the third sub-stage circuit is opened to generate a second bias signal for cutting off the first switching tube.

Optionally, the third sub-stage circuit includes a third resistor, a first diode, a fourth resistor and a third diode, where two ends of the third resistor are respectively connected to the second voltage and a forward end of the first diode, a reverse end of the first diode is connected to the forward end of the third diode through the fourth resistor, and a reverse end of the third diode is used to connect to the first reference voltage or the second reference voltage; the voltage signal of one circuit node of the third sub-stage circuit is provided for the driving end of the first switching tube.

Optionally, the first switching tube is an NPN triode, an emitter and a collector of the first switching tube are located on the second sub-stage circuit, and a voltage signal of one circuit node of the third sub-stage circuit is provided to the base of the first switching tube.

Optionally, the first diode is a light emitting diode, the first diode faces the base electrode of the first switch tube, and the first diode and the first switch tube form a first optocoupler element.

Optionally, the processing module includes a fourth sub-stage circuit, the fourth sub-stage circuit has a second switching tube, and when the second switching tube is turned on, the fourth sub-stage circuit forms a closed loop to generate a first state signal; when the second switching tube is cut off, the fourth sub-stage circuit is opened so as to generate a second state signal; the processing module detects that the power switch is pressed according to the first state signal and detects that the power switch is not pressed according to the second state signal; wherein, the first sub-stage circuit generates a third bias signal for conducting the second switching tube when a closed loop is formed; the first sub-stage circuit generates a fourth bias signal for turning off the second switching tube when it is open.

Optionally, the fourth sub-stage circuit further includes a fifth resistor, one end of the fifth resistor is connected to the second voltage, the other end of the fifth resistor is grounded through the second switch, and the other end of the fifth resistor is used for outputting the first state signal or the second state signal.

Optionally, the processing module includes a logic processor externally connected to the host module, the logic processor has a common port, the logic processor switches the common port to a signal input state or a signal output state, and provides the first reference voltage or the second reference voltage to the third sub-stage circuit through the common port in the signal output state, and receives the first state signal or the second state signal provided by the fourth sub-stage circuit through the common port in the signal input state; the third sub-stage circuit further comprises a capacitor, and the capacitor is led out from between the first end and the second end of the third sub-stage circuit and is grounded.

Optionally, the second switching tube is an NPN triode, an emitter and a collector of the second switching tube are located on the fourth sub-stage circuit, and a voltage signal of one of the circuit nodes on the first sub-stage circuit is provided to the base of the second switching tube.

Optionally, the second diode is a light emitting diode, the second diode faces the base electrode of the second switching tube, and the second diode and the second switching tube form a second optocoupler element.

Optionally, the power tube is a PMOS tube, the input end of the power tube is a source electrode of the PMOS tube, the output end of the power tube is a drain electrode of the PMOS tube, and the gate electrode of the power tube is connected with the driving module; or the power tube is a PNP triode, the input end of the power tube is an emitter of the PNP triode, the output end of the power tube is a collector of the PNP triode, and the base electrode of the power tube is connected with the driving module.

Based on a second aspect of the present utility model, the present utility model also provides a host system comprising a host module and a power control circuit as described above, the host module being communicatively connected to the processing module.

In summary, in the host system and the power control circuit thereof provided by the present utility model, the power control circuit includes a power tube, a driving module and a processing module: the input end of the power tube acquires a first voltage, and the output end of the power tube is connected with the processing module and is used for being externally connected with the host module; the driving module outputs a conducting signal to conduct the power tube or outputs a cut-off signal to cut off the power tube, the driving module is provided with a power switch, and the driving module outputs the conducting signal after the power switch is pressed; the processing module is externally connected with the host module to start or shut down the host module, and is used for detecting the pressing state of the power switch; the power control circuit has a power-on mode and a power-off mode.

So configured, in the first aspect, the power switch is pressed to enable the power control circuit to operate in a startup mode, the driving module outputs a conduction signal to conduct the power tube, so that the first voltage can supply power to the processing module and the host module, and the processing module can work after power is supplied to drive the driving module to continuously output the conduction signal to ensure that the power tube is continuously conducted, and the processing module starts the host module to ensure that the host module is normally started, so that even if the subsequent power switch is not pressed, the power tube can be continuously conducted under the cooperation of the processing module and the driving module. In a second aspect, the power switch is pressed again to enable the power control circuit to operate in a shutdown mode, the processing module detects that the power switch is pressed again after the host module is started to generate a shutdown instruction, a user can determine whether the host module needs to be shut down according to the shutdown instruction, if the user determines to perform shutdown processing, the processing module drives the host module to shut down, and the processing module drives the driving module to output a shutdown signal after the host module is shut down, so that the power tube is shut down, and further the first voltage can not supply power to the processing module and the host module any more.

Further, the boot-mode is further configured to: after the processing module detects that the pressed time of the power switch reaches the preset time, the processing module starts the host module. Therefore, the processing module detects the pressed time of the power switch, and starts the host module after the preset time is reached, so that the situation that the host module is accidentally started due to the fact that the power switch is pressed by mistake can be avoided.

Drawings

It will be appreciated by those skilled in the art that the drawings are provided for a better understanding of the utility model and do not constitute any limitation on the scope of the utility model. Wherein:

FIG. 1 is a schematic diagram of a host system according to an embodiment of the utility model.

In the accompanying drawings:

10-a driving module; 11-a first sub-stage circuit; 12-a second sub-stage circuit;

20-a processing module; a 21-logic processor; 22-a voltage regulation unit; 23-a third sub-stage circuit; 24-fourth sub-stage circuit;

30-a computer host; 40-a display;

s-power switch; q0-power tube; u1-a first optocoupler element; q1-a first switching tube; d1-a first diode; u2-a second optocoupler; q2-a second switching tube; d2—a second diode; d3-a third diode; c-capacitance; r1-a first resistor; r2-a second resistor; r3-a third resistor; r4-fourth resistor; r5-fifth resistor; r6-sixth resistance; r7-seventh resistor; p1-a first port; p2-second port; p3-third port; p4-fourth port; v1-a first voltage; v2-second voltage.

Detailed Description

The utility model will be described in further detail with reference to the drawings and the specific embodiments thereof in order to make the objects, advantages and features of the utility model more apparent. It should be noted that the drawings are in a very simplified form and are not drawn to scale, merely for convenience and clarity in aiding in the description of embodiments of the utility model. Furthermore, the structures shown in the drawings are often part of actual structures. In particular, the drawings are shown with different emphasis instead being placed upon illustrating the various embodiments.

As used in this disclosure, the singular forms "a," "an," and "the" include plural referents, the term "or" are generally used in the sense of comprising "and/or" and the term "several" are generally used in the sense of comprising "at least one," the term "at least two" are generally used in the sense of comprising "two or more," and the term "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying any relative importance or number of features indicated. Thus, a feature defining "first," "second," "third," or "third" may explicitly or implicitly include one or at least two such features, with "one end" and "another end" and "proximal end" and "distal end" generally referring to the respective two portions, including not only the endpoints, but also the terms "mounted," "connected," "coupled," and "connected" are to be construed broadly, e.g., as being either a fixed connection, a removable connection, or as being integral therewith; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. Furthermore, as used in this disclosure, an element disposed on another element generally only refers to a connection, coupling, cooperation or transmission between two elements, and the connection, coupling, cooperation or transmission between two elements may be direct or indirect through intermediate elements, and should not be construed as indicating or implying any spatial positional relationship between the two elements, i.e., an element may be in any orientation, such as inside, outside, above, below, or on one side, of the other element unless the context clearly indicates otherwise. The specific meaning of the above terms in the present utility model can be understood by those of ordinary skill in the art according to the specific circumstances.

FIG. 1 is a schematic diagram of a host system according to an embodiment of the utility model. As shown in fig. 1, an embodiment of the present utility model schematically proposes a host system, the host system includes a power control circuit and a host module communicatively connected to the power control circuit, the power control circuit is used for powering on or powering off the host module, further, the host module includes a host 30 communicatively connected to the power control circuit and a display 40 communicatively connected to the host 30, the power control circuit powers on the host 30 to turn on the display 40, and the power control circuit powers off the host 30 to turn off the display 40. The power control circuit includes a power transistor Q0, a driving module 10, and a processing module 20, and each of the power control circuit is described in detail below.

Regarding the power tube Q0, the input end of the power tube Q0 obtains the first voltage V1, the output end of the power tube Q0 is connected with the processing module 20 and the external host module, and the driving end of the power tube Q0 is connected with the driving module 10. Regarding the driving module 10, the driving module 10 is configured to control the power tube Q0 to be turned on or off, it is understood that when the driving module 10 controls the power tube Q0 to be turned on, the first voltage V1 can supply power to the processing module 20 and the host module through the turned-on power tube Q0, so that it is ensured that the processing module 20 and the host module can perform subsequent starting operation after being powered on; when the driving module 10 turns off the power tube Q0, the first voltage V1 cannot supply power to the processing module 20 and the host module. Specifically, the driving module 10 outputs an on signal to the driving end of the power tube Q0 to turn on the power tube Q0 or outputs an off signal to the driving end of the power tube Q0 to turn off the power tube Q0. Further, the driving module 10 has a power switch S, and when the power switch S is pressed, the driving module 10 can output a conducting signal to conduct the power tube Q0.

In an embodiment, the power tube Q0 is a PMOS tube, the input end of the power tube Q0 is a source electrode of the PMOS tube, the output end of the power tube Q0 is a drain electrode of the PMOS tube, and the driving end of the power tube Q0 is a gate electrode of the PMOS tube. In an alternative embodiment, the power transistor Q0 is a PNP type transistor, the input end of the power transistor Q0 is an emitter of the PNP type transistor, the output end of the power transistor Q0 is a collector of the PNP type transistor, and the driving end of the power transistor Q0 is a base of the PNP type transistor. In this way, the driving module 10 can output the on signal as a low level to turn on the power transistor Q0, and output the off signal as a high level to turn off the power transistor Q0.

Regarding the processing module 20, the processing module may be powered by the first voltage V1 to operate normally after the power tube Q0 is turned on, and the processing module 20 is externally connected to the host module, specifically, the processing module 20 is communicatively connected to the host computer 30 (an embodiment of the host module), and performs a startup process or a shutdown process on the host computer 30. The processing module 20 is connected to the driving module 10 to detect the pressing state of the power switch S, including detecting whether the power switch S is pressed, the time of being pressed, and the like. The processing module 20 includes a logic processor 21 (for example, a single-chip microcomputer), and the logic processor 21 controls the computer host 30 to be turned on or turned off.

It should be noted that the voltages required by the logic processor 21 and the computer host 30 are not necessarily equal, for example, the computer host 30 requires 24V, and the logic processor 21 requires 5V. As a further implementation detail, the processing module 20 further includes a voltage adjustment unit 22, where the voltage adjustment unit 22 is connected between the output end of the power tube Q0 and the logic processor 21, and the voltage adjustment unit 22 may obtain the first voltage V1 after the power tube Q0 is turned on, and adjust the first voltage V1 to a third voltage to supply power to the logic processor 21. For example, the voltage adjusting unit 22 adjusts the first voltage V1 of 24V to the third voltage of 5V, thereby supplying the logic processor 21 with the 5V voltage. The voltage regulating unit 22 may be, for example, a DC-DC converter or a DC-DC circuit.

As a further implementation detail, the logic processor 21 has a first port P1, a second port P2, a third port P3, and a fourth port P4, wherein the logic processor 21 can output a first reference voltage or a second reference voltage through the first port P1 after power is supplied, detect the pressing state of the power switch S in the driving module 10 through the second port P2, perform information interaction with the computer host 30 through the third port P3, such as performing interaction of a shutdown command, and output a corresponding signal through the fourth port P4 to control the computer host 30 to be turned on or turned off.

The power control circuit has a power-on mode and a power-off mode. Wherein the boot-up mode is configured to: the power switch S is pressed, the driving module 10 outputs a conducting signal to enable the power tube Q0 to be powered by the first voltage V1 after being conducted, so that the processing module 20 drives the driving module 10 to continuously output the conducting signal to ensure that the power tube Q0 is continuously conducted, that is, the output end of the power tube Q0 can continuously output the first voltage V1, and the processing module 20 starts up the host module. The shutdown mode is configured to: the processing module 20 detects that the power switch S is pressed after the host module is turned on, so that the processing module 20 generates a shutdown instruction for indicating or driving the host module to shutdown, and the processing module 20 drives the driving module 10 to output a shutdown signal to shut down the power tube Q0 after the host module is turned off. It should be noted that, the shutdown instruction generated by the processing module 20 may be, for example, an information prompt box in the display 40, and if the user selects shutdown, the user may click to confirm the shutdown instruction to feed back to the processing module 20 through the third port P3, and the processing module 20 then drives the host module to shutdown according to the shutdown instruction, and if the user selects not to shutdown, the user considers that the power switch S is pressed by mistake, the shutdown instruction may not be processed, and the host module is still in a startup running state.

In the first aspect, when the user needs to start the host module, the user presses the power switch S to enable the power control circuit to operate in the start-up mode, then the driving module 10 outputs a conduction signal to conduct the power tube Q0 after the power switch S is pressed, so that the first voltage V1 can supply power to the processing module 20 and the host module, the logic processor 21 of the processing module 20 can obtain electric operation, and then the processing module 20 detects that the power switch S is pressed and then drives the driving module 10 to continuously output the conduction signal to ensure that the power tube Q0 is continuously conducted, and the processing module 20 further starts the host module to ensure that the host module is normally started after being supplied with power by the first voltage V1, so that even if the subsequent power switch S is not pressed, the power tube Q0 can be continuously conducted under the cooperation control of the processing module 20 and the driving module 10.

The boot-mode is further configured to: after the processing module 20 detects that the time when the power switch S is pressed reaches the preset time (for example, 5S), the processing module 20 starts the host module, so that the processing module 20 detects the time when the power switch S is pressed, starts the host module after the preset time is reached, and the situation that the host module is started accidentally due to the fact that the power switch S is pressed by mistake can be avoided. In a specific implementation, the processing module 20 may be, for example, a built-in timing unit, where the timing unit starts timing after the power switch S is pressed, and the processing module 20 starts the host module after the timing reaches a preset time.

In a second aspect, when the user needs to power off the host module, the user presses the power switch S again in the power-on state of the host module to enable the power control circuit to operate in the power-off mode, the processing module 20 detects that the power switch S is pressed again to generate a power-off instruction, the user can determine whether the host module needs to be powered off according to the power-off instruction, if the user determines to power off the host module, the power-off instruction is confirmed and fed back to the logic processor 21 of the processing module 20 through the third port P3, and then the processing module 20 controls the host module to power off, and the processing module drives the driving module 10 to output a cut-off signal after the host module is powered off, so that the power tube Q0 is cut off, the power-off instruction confirmed by the user and the power-off after-process module 20 is confirmed to feed back to control the driving module 10 to cut off the power tube Q0 can be increased, the security of the system power-off process is ensured, and the host module is prevented from being accidentally powered off due to the power switch S being pressed by mistake. In addition, the power tube Q is cut off after the host module is shut down, so that unexpected power-off and shutdown caused by cut-off of the power tube Q0 in the normal shutdown process of the computer host 30 can be avoided. Regarding the embodiment of whether the host module is powered off, considering that in actual situations, the power-off process of the host computer 30 needs a certain time, and the running systems installed by different host computers 30 are different (for example, windows systems are installed but versions are different), so that the time of the power-off process is also different, for example, the processing module may have a timing unit built in, and the timing unit starts to time after the user confirms the power-off instruction, but after the time reaches the set time, the processing module 20 drives the driving module 10 to cut off the power tube Q0.

As such, it is understood that the shutdown instruction instructs or forces the host module to shutdown, i.e., the signal class of the shutdown instruction is a combination of an instruction class signal (e.g., a sensory signal) and a communication class signal. The indication type signal is used to make the user feel that the processing module 20 generates a shutdown instruction (such as an information prompt box in the display 40 to prompt the user in this embodiment); after the function of the communication signal, that is, the shutdown command is confirmed, the processing module 20 can be considered to output the shutdown command as an electrical signal to the host module through the P4 port, so as to drive the host module to shutdown.

The circuit configuration of the driving module 10 for outputting the on signal or the off signal. With continued reference to fig. 1, the drive module 10 includes a first sub-stage 11 and a second sub-stage 12; the first sub-stage circuit 11 is used for being connected with a power supply, the power supply can provide a first voltage V1, the first sub-stage circuit is provided with a second diode D2, a power switch S is arranged on the first sub-stage circuit 11, and when the power switch S is pressed, the first sub-stage circuit 11 forms a closed loop, so that a conducting signal is generated at the forward end of the second diode D2 and is output to the driving end of the power tube Q0. It can be understood that the on signal is a low level signal obtained by processing the forward voltage drop of the second diode D2, so as to control the power tube Q0 to be turned on, for example, a diode with a forward voltage drop of 1.5V can be selected as the second diode D2, that is, the computer host 30 is not turned on, when the power switch S is pressed, the driving module 10 outputs the on signal, and the power tube Q0 is turned on to enable the processing module 20 to be powered on, so that the processing module 20 starts to work. When the power switch S is not pressed, the first sub-stage 11 is opened to generate a cut-off signal and output the cut-off signal to the driving end of the power transistor Q0. The second sub-stage circuit 12 has a first switching tube Q1, and when the first switching tube Q1 is turned on, the second sub-stage circuit 12 forms a closed loop to generate a conduction signal and output the conduction signal to the driving end of the power tube Q0; when the first switching tube Q1 is turned off, the second sub-stage circuit 12 is opened to generate a turn-off signal and output the turn-off signal to the driving end of the power tube Q0, and the processing module 20 is configured to control the first switching tube Q1 to be turned on or turned off after power is obtained.

The first sub-stage circuit 11 includes a first resistor R1, a second diode D2, and a second resistor R2, where one end of the first resistor R1 obtains a first voltage V1, the other end of the first resistor R1 is connected to a forward end of the second diode D2, a reverse end of the second diode D2 is connected to the ground through a power switch S, one end of the second resistor R2 is connected to the forward end of the second diode D2, and the other end of the second resistor R2 is the driving end of the power tube Q0. Thus, after the power switch S is pressed, the first voltage V1, the first resistor R1, the second diode D2, the power switch S and the ground end form a closed loop, a potential of a forward voltage drop is formed at the forward end of the second diode D2, and the potential is considered to be output as a low-level conduction signal to the power tube Q0 through the second resistor R2 so as to conduct the power tube Q0; when the power switch S is not pressed, the first voltage V1, the first resistor R1, the second diode D2, the power switch S, and the ground form an open circuit, and the first voltage V1 is connected to the power tube Q0 through the first resistor R1 and the second resistor R2, which is considered to be a high-level cut-off signal to cut off the power tube Q0. The second sub-stage circuit 12 further includes a sixth resistor R6 and a seventh resistor R7, where after the sixth resistor R6 and the seventh resistor R7 are connected in series, the first voltage V1 is obtained through the sixth resistor R6, one end of the seventh resistor R7, which is not connected to the sixth resistor R6, is grounded through the first switching tube Q1, and line portions of the seventh resistor R7 and the first switching tube Q1 are used for outputting an on signal or an off signal. After the first switching tube Q1 is turned on, the first voltage V1, the sixth resistor R6, the seventh resistor R7, the first switching tube Q1, and the ground form a closed loop, and the end of the seventh power tube Q0, to which the sixth resistor R6 is not connected, outputs a low-level on signal to turn on the power tube Q0; after the first switching tube Q1 is turned off, the first voltage V1, the sixth resistor R6, the seventh resistor R7, the first switching tube Q1, and the ground terminal are open circuits, and the first voltage V1 is provided to the driving terminal of the power tube Q0 through the sixth resistor R6 and the seventh resistor R7, and can be regarded as a high-level cut-off signal to be output to the power tube Q0. Preferably, in order to save component resources, the first resistor R1 and the sixth resistor R6 are the same resistor, and the second resistor R2 and the seventh resistor R7 are the same resistor.

The first switching tube Q1 is an NPN-type triode, the emitter and collector of the first switching tube Q1 are located on the second sub-stage circuit 12, the driving end of the first switching tube Q1 is a base of the NPN-type triode, and the first switching tube Q1 is used for providing the first bias signal as a high level to turn on itself by the acquisition processing module 20, and providing the second bias signal as a low level to turn off itself by the acquisition processing module 20.

Regarding the embodiment in which the processing module 20 controls the first switching tube Q1 to be turned on or off, the processing module 20 generates the second voltage V2 after the power tube Q0 is turned on. Preferably, the second voltage V2 and the third voltage are the same voltage, and the processing module 20 outputs the second voltage V2 according to the first voltage V1 after acquiring the first voltage V1. And after the power tube Q0 is turned on to be supplied with the first voltage V1, the processing module 20 itself operates to provide the first reference voltage or the second reference voltage. Further, the first reference voltage is less than the second reference voltage. Specifically, the first reference voltage or the second reference voltage is provided through the first port P1. When the processing module 20 generates the second voltage V2 and provides the first reference voltage, the processing module 20 may turn on the first switching tube Q1, for example, generate a first bias signal for turning on the first switching tube Q1; when the processing module 20 generates the second voltage V2 and provides the second reference voltage, the processing module 20 turns off the first switching tube Q1, for example, generates a second bias signal that turns off the first switching tube Q1. Specifically, for example, the circuit state (such as a loop) of the circuit structure in the processing module 20 after the second voltage V2 and the first reference voltage are connected is different from the circuit state (such as an open circuit) of the circuit structure after the second voltage V2 and the second reference voltage are connected, so that the signals output by the circuits in different circuit states are also different, for example, when the circuit state is a loop, the circuit structure of the processing module 20 outputs the first bias signal to the driving end of the first switching tube Q1, and when the circuit state is an open circuit, the circuit structure of the processing module 20 outputs the second bias signal to the driving end of the first switching tube Q1. In other embodiments, the processing module 20 may also have a built-in operation unit, where the operation unit is configured to output a comparison result of the second voltage V2 and the first reference voltage or a comparison result of the second voltage V2 and the second reference voltage, and when the comparison result of the second voltage V2 and the first reference voltage is output, the processing module 20 outputs a first bias signal to the driving end of the first switching tube Q1; when the comparison result of the second voltage V2 and the second reference voltage is outputted, the processing module 20 outputs the second bias signal to the driving terminal of the first switching tube Q1.

Further, regarding the circuit configuration in which the processing module 20 outputs the first bias signal or the second bias signal to drive the first switching tube Q1 to be turned on or off. The processing module 20 includes a third sub-stage circuit 23, a first end of the third sub-stage circuit 23 is connected to the second voltage V2, and a second end of the third sub-stage circuit 23 is connected to the first port P1 of the logic processor 21 to obtain the first reference voltage or the second reference voltage; when the third sub-stage circuit 23 is connected to the first reference voltage, the third sub-stage circuit 23 forms a closed loop to generate a first bias signal; when the third sub-stage 23 is connected to the second reference voltage, the third sub-stage 23 is opened to generate the second bias signal.

The third sub-stage circuit 23 includes a third resistor R3, a first diode D1, a fourth resistor R4, and a third diode D3, wherein two ends of the third resistor R3 are respectively connected to the second voltage V2 and a forward end of the first diode D1, a reverse end of the first diode D1 is connected to the forward end of the third diode D3 through the fourth resistor R4, and a reverse end of the third diode D3 is connected to the first port P1 to obtain the first reference voltage or the second reference voltage; the voltage signal of one of the circuit nodes of the third sub-stage circuit 23 is supplied to the driving terminal of the first switching tube Q1. The first reference voltage is at a low level, and the second reference voltage is at a high level. When the two ends of the third sub-stage circuit 23 are respectively connected to the second voltage V2 and the first reference voltage, the first reference voltage as a low level is equivalent to providing a reference ground terminal for the third sub-stage circuit 23, so that the third sub-stage circuit 23 is a closed loop, thereby forming a current, and further forming a high-level first bias signal, and one circuit node is provided for the driving terminal of the first switching tube Q1, so as to conduct the first switching tube Q1, for example, a line can be led out from the third resistor R3 and the forward terminal of the first diode D1 to be connected to the driving terminal of the first switching tube Q1; when the two ends of the third sub-stage circuit 23 are respectively connected to the second voltage V2 and the second reference voltage, the second reference voltage as a high level makes the third sub-stage circuit 23 unable to form a potential difference therebetween, so that no current is generated in the third sub-stage circuit 23, and it can be considered that the third sub-stage circuit 23 outputs the second bias signal as a low level to the first switching tube Q1 to turn off the first switching tube Q1.

Preferably, the first switching tube Q1 is an NPN triode, an emitter and a collector of the first switching tube Q1 are located on the second sub-stage circuit 12, further, a collector of the first switching tube Q1 is connected to the seventh resistor R7, and the emitter of the first switching tube Q1 is grounded; the first diode D1 is a light emitting diode, the first diode D1 faces the base electrode of the first switch Q1, and the first diode D1 and the first switch Q1 form a first optocoupler U1. In this way, the first optocoupler element U1 is adopted in the circuit, so that the possibility of fluctuation and burr interference of the input power supply (namely the first voltage V1) of the system can be reduced through the photoelectric isolation of the optocoupler.

The processing module 20 detects the circuit configuration of the pressed state of the power switch S. The processing module 20 comprises a fourth sub-stage 24, the fourth sub-stage 24 being connected to the second port P2 of the logic processor 21, the fourth sub-stage 24 having a second switching tube Q2; when the second switching tube Q2 is turned on, the fourth sub-stage circuit 24 forms a closed loop to generate a first status signal, and inputs the first status signal to the logic processor 21 through the second port P2; when the second switching tube Q2 is turned off, the fourth sub-stage circuit 24 is opened to generate a second status signal, and the second status signal is input to the logic processor 21 through the second port P2. The processing module 20 (i.e. the logic processor 21 of the processing module 20) detects that the power switch S is pressed according to the first status signal and that the power switch S is not pressed according to the second status signal. Wherein, when the first sub-stage circuit 11 forms a closed loop, a third bias signal for turning on the second switching tube Q2 is generated; the first sub-stage circuit 11 generates a fourth bias signal for turning off the second switching tube Q2 when it is open. As such, when the logic processor 21 detects the first status signal through the second port P2, it can be considered that the power switch S is pressed, and further the time when the power switch S is pressed can be obtained by detecting the duration of the first status signal; when the logic processor 21 detects the second status signal through the second port P2, the power switch S may be considered not to be pressed.

The fourth sub-stage circuit 24 further includes a fifth resistor R5, one end of the fifth resistor R5 is connected to the second voltage V2, the other end of the fifth resistor R5 is grounded through the second switching tube Q2, and the other end of the fifth resistor R5 is connected to the second port P2 for outputting the first status signal or the second status signal. Thus, when the second switching tube Q2 is turned on, the second voltage V2, the fifth resistor R5, the second switching tube Q2 and the ground form a closed loop, so that the first state signal as a low level is output at the other end of the fifth resistor R5 to be provided to the logic processor 21; when the second switching tube Q2 is turned off, the second voltage V2, the fifth resistor R5, the second switching tube Q2, and the ground terminal are open, and the second voltage V2 is provided to the second port P2 through the fifth resistor R5, which can be considered to provide the second port P2 with the second status signal as a high level.

The second switching tube Q2 is an NPN-type triode, the emitter and the collector of the second switching tube Q2 are located on the fourth sub-stage circuit 24, specifically, the emitter of the second switching tube Q2 is grounded, the collector of the second switching tube Q2 is connected to the fifth resistor R5, the driving end of the second switching tube Q2 is the base of the NPN-type triode, and the second switching tube Q2 is used for acquiring the third bias signal provided by the first sub-stage circuit 11 as a high level to turn on itself, and acquiring the second bias signal provided by the first sub-stage circuit 11 as a low level to turn off itself. Further, the voltage signal of one of the circuit nodes on the first sub-stage 11 is provided as a third bias signal or a second bias signal to the base electrode of the second switching tube Q2, for example, the base electrode of the second switching tube Q2 is connected between the second diode D2 and the first resistor R1, so that when the power switch S is pressed, the first sub-stage 11 forms a closed loop to generate a current, so that the base electrode of the second switching tube Q2 is considered to be provided with the third bias signal as a high level to turn on the second switching tube Q2, and the fourth sub-stage 24 forms a closed loop to generate the first status signal; when the power switch S is not pressed, the first sub-stage circuit 11 is open, no current is generated, so that the base of the second switching tube Q2 is considered to be provided with the fourth bias signal as a low level to turn off the second switching tube Q2, and the fourth sub-stage circuit 24 is open to generate the second state signal.

Preferably, the second switching tube Q2 is an NPN triode, an emitter and a collector of the second switching tube Q2 are located on the second sub-stage circuit 12, further, a collector of the second switching tube Q2 is connected to the fifth resistor R5, and the emitter of the second switching tube Q2 is grounded; the second diode D2 is a light emitting diode, the second diode D2 faces the base electrode of the second switching tube Q2, and the second diode D2 and the second switching tube Q2 form a second optocoupler U2. In this way, the second optocoupler element U2 is adopted in the circuit, and the possibility of fluctuation and burr interference of the input power supply (namely the first voltage V1) of the system can be reduced through the photoelectric isolation effect of the optocoupler.

Preferably, the logic processor 21 has the first port P1 and the second port P2 which are the same port, named common port, and the logic processor 21 can switch the common port to the signal input state (having the function of the second port P2 at this time) or the signal output state (having the function of the first port P1 at this time), and supply the first reference voltage or the second reference voltage to the third sub-stage 23 through the common port in the signal output state, and receive the first state signal or the second state signal supplied from the fourth sub-stage 24 through the common port in the signal input state. The third sub-stage circuit 23 further includes a capacitor C, where the capacitor C is led out between the first end and the second end of the third sub-stage circuit 23 and grounded, for example, between the first diode D1 and the fourth resistor R4. It should be noted that, in one state operation period of the common port, the time of the common port in the signal output state is much longer than the time of the common port in the signal input state, for example, the ratio of the time of the signal output state to the time of the signal input state is 99:1 in one state operation period of the common port, for example, one state period of the common port is 10ms, the time of the signal output state is 9.9ms, and the time of the signal input state is 0.1ms. The first port P1 and the second port P2 are used as common ports to realize multiplexing of signals, port resources of the logic processor 21 are saved, the system overhead is low, a new additional process or thread is not required to be created by the system, the operation of the processes and the threads is not required to be maintained, the maintenance workload of the system is reduced, and the system resources are saved.

As can be understood, referring to fig. 1, when the common port is in the signal output state and outputs the first reference voltage, the third sub-stage 23 forms a closed loop, and the third sub-stage 23 generates the first bias signal for turning on the first switch Q1 to ensure that the second sub-stage 12 forms a loop, so that the second sub-stage 12 generates the conduction signal for turning on the power transistor Q0, and the capacitor C discharges. When the common port is in the signal input state, the common port cannot supply the first reference voltage to the third sub-stage 23, but the second voltage V2, the third resistor R3, the first diode D1, the capacitor C and the branch formed by the ground terminal will charge the capacitor C, and during the charging process of the capacitor C, a current flows through the branch to supply the first bias signal to the driving terminal of the first switching tube Q1. When the common port is switched to the signal output state again to output the first reference voltage, the capacitor C is discharged again, so that the third sub-stage circuit 23 is ensured to continuously provide the first bias signal for the first switching tube Q1 in the periodic charging and discharging process of the capacitor C, so that the second sub-stage circuit 12 is ensured to be continuously closed to output the conducting signal to the power tube Q0, and further, the power switch S is ensured to be continuously conducted even if the power tube Q0 is not pressed. When the common port is in the signal input state and the second state signal provided by the fourth sub-stage 24 is detected, a shutdown command is generated on the display 40, if the shutdown command is not processed by the user, the common port will switch between the signal input state and the signal output state according to the time duty ratio in the originally set state operation cycle, if the user confirms the shutdown command and feeds back to the logic processor 21, the logic processor 21 switches the host 30 to the signal output state to output the second reference voltage after the host 30 is shut down, the capacitor C charges, and during the gradual rising of the voltage of the capacitor C, the voltage difference across the first diode D1 will gradually decrease until the voltage difference across the first diode D1 is smaller than the forward voltage drop of the first diode D1 itself, the third sub-stage 23 has no current to generate the first bias signal for turning on the first switch Q1, the first switch Q1 will be turned off, and the second sub-stage 12 is turned off, so that the whole power transistor Q0 is turned off.

Based on the same inventive concept as the power control circuit, the present embodiment also provides a startup and shutdown method of a host system, where the host system includes a power tube Q0, a power switch S, a host module, and a controller, and the controller of the present embodiment can be understood as the driving module 10 and the processing module 20 described above, where the input end of the power tube Q0 obtains a first voltage V1, the output end of the power tube Q0 is connected to the host module, and the power tube Q0 transmits the first voltage V1 to the host module and the controller when being turned on, so as to supply power to the host module and the controller. The on-off method comprises the following steps:

the power switch S is pressed to enable the controller to be electrified (namely, the controller is powered by the first voltage V1 to start working);

the controller is configured to detect a pressing state of the power switch S (including, but not limited to, detecting whether the power switch S is pressed, and a time when the power switch S is pressed, etc.), and if the power switch S is detected to be pressed, control the power tube Q0 to be continuously turned on, and control the host module to be turned on; and/or the number of the groups of groups,

when the power switch S is detected to be pressed after the host module is started, a shutdown instruction is generated (for example, the controller can generate the shutdown instruction), and whether the host module is shut down or not is judged according to the shutdown instruction; if yes, the host module is controlled to be shut down, and the power tube Q0 is controlled to be cut off after the host module is shut down.

Further, after detecting that the time when the power switch S is pressed reaches the preset time, the power tube Q0 is controlled to be turned on and the host module is controlled to be turned on.

It should be noted that, those skilled in the art can further understand the power on/off method of the host system according to the foregoing power control circuit of the host system, and the description will not be repeated here.

Based on the above-mentioned method for powering on and powering off the host system, the present embodiment further provides a storage medium, on which a readable and writable program is stored, which when executed implements the above-mentioned method for powering on and powering off the host system. Specifically, the method for switching on/off the host system provided by the utility model can be programmed or software, and is stored on a readable storage medium, and in actual use, each step of the method for switching on/off the host system is executed by using the program stored on the readable storage medium. And the readable storage medium may be integrated in the host system or may be provided separately in other hardware.

The foregoing description is only illustrative of the preferred embodiments of the present utility model, and is not intended to limit the scope of the present utility model in any way, and any changes and modifications made by those skilled in the art in light of the foregoing disclosure will be deemed to fall within the scope and spirit of the present utility model.

Claims

1. A power supply control circuit, comprising;

2. The power control circuit of claim 1, wherein the power-on mode is further configured to: and after the processing module detects that the pressed time of the power switch reaches the preset time, the processing module starts the host module.

3. The power control circuit of claim 1, wherein the processing module comprises a voltage adjustment unit and a logic processor; the voltage adjusting unit is connected between the output end of the power tube and the logic processor, and the logic processor is used for externally connecting the host module; the voltage adjusting unit is used for adjusting the first voltage to a third voltage so as to supply power to the logic processor.

4. The power control circuit of claim 1, wherein the drive module comprises a first sub-stage circuit and a second sub-stage circuit;

5. The power control circuit of claim 4, wherein the first sub-stage circuit further comprises a first resistor and a second resistor, wherein a first voltage is obtained at one end of the first resistor, the other end of the first resistor is connected to the forward end of the second diode, the reverse end of the second diode is connected to the ground through the power switch, one end of the second resistor is connected to the forward end of the second diode, and the other end of the second resistor is connected to the driving end of the power tube.

6. The power control circuit of claim 4, wherein the second sub-stage circuit further comprises a sixth resistor and a seventh resistor, the sixth resistor and the seventh resistor are connected in series and then the first voltage is obtained through the sixth resistor, and one end of the seventh resistor, which is not connected to the sixth resistor, is used for grounding through the first switch tube.

7. The power control circuit of claim 4, wherein the processing module generates a second voltage after the power tube is turned on, and wherein the processing module provides either a first reference voltage or a second reference voltage after the power tube is turned on;

8. The power control circuit of claim 7, wherein the processing module comprises a third sub-stage circuit, a first terminal of the third sub-stage circuit being connected to the second voltage, a second terminal of the third sub-stage circuit being connected to the first reference voltage or the second reference voltage;

when the third sub-stage circuit is connected to the first reference voltage, the third sub-stage circuit forms a closed loop to generate a first bias signal for conducting the first switch tube; when the third sub-stage circuit is connected to the second reference voltage, the third sub-stage circuit is opened to generate a second bias signal for cutting off the first switch tube.

9. The power control circuit of claim 8, wherein the third sub-stage circuit comprises a third resistor, a first diode, a fourth resistor and a third diode, wherein two ends of the third resistor are respectively connected to the second voltage and a forward end of the first diode, a reverse end of the first diode is connected to the forward end of the third diode through the fourth resistor, and the reverse end of the third diode is used for being connected to the first reference voltage or the second reference voltage; the voltage signal of one circuit node of the third sub-stage circuit is provided for the driving end of the first switching tube.

10. The power control circuit of claim 9, wherein the first switching tube is an NPN transistor, an emitter and a collector of the first switching tube are located on the second sub-stage circuit, and a voltage signal of one of the circuit nodes of the third sub-stage circuit is provided to the base of the first switching tube.

11. The power control circuit of claim 10, wherein the first diode is a light emitting diode, the first diode faces the base of the first switching tube, and the first diode and the first switching tube form a first optocoupler.

12. The power control circuit of claim 8, wherein the processing module comprises a fourth sub-stage circuit having a second switching tube, the fourth sub-stage circuit forming a closed loop when the second switching tube is on to generate the first status signal; when the second switching tube is cut off, the fourth sub-stage circuit is opened so as to generate a second state signal; the processing module detects that the power switch is pressed according to the first state signal and detects that the power switch is not pressed according to the second state signal;

wherein, the first sub-stage circuit generates a third bias signal for conducting the second switching tube when a closed loop is formed; the first sub-stage circuit generates a fourth bias signal for turning off the second switching tube when it is open.

13. The power control circuit of claim 12, wherein the fourth sub-stage circuit further comprises a fifth resistor, one end of the fifth resistor is connected to the second voltage, the other end of the fifth resistor is grounded through the second switch tube, and the other end of the fifth resistor is used for outputting the first state signal or the second state signal.

14. The power control circuit of claim 12, wherein the processing module includes a logic processor circumscribing the host module, the logic processor having a common port, the logic processor switching the common port to a signal input state or a signal output state and providing the first reference voltage or the second reference voltage to the third sub-stage circuit through the common port in the signal output state, and receiving the first status signal or the second status signal provided by the fourth sub-stage circuit through the common port in the signal input state;

the third sub-stage circuit further comprises a capacitor, and the capacitor is led out from between the first end and the second end of the third sub-stage circuit and is grounded.

15. The power control circuit of claim 12 wherein the second switching tube is an NPN transistor, an emitter and a collector of the second switching tube being located on the fourth sub-stage circuit, a voltage signal at one of the circuit nodes on the first sub-stage circuit being provided to the base of the second switching tube.

16. The power control circuit of claim 15, wherein the second diode is a light emitting diode, the second diode faces the base of the second switching tube, and the second diode and the second switching tube form a second optocoupler.

17. The power control circuit of claim 1, wherein the power tube is a PMOS tube, the input end of the power tube is a source electrode of the PMOS tube, the output end of the power tube is a drain electrode of the PMOS tube, and the gate electrode of the power tube is connected with the driving module;

or the power tube is a PNP triode, the input end of the power tube is an emitter of the PNP triode, the output end of the power tube is a collector of the PNP triode, and the base electrode of the power tube is connected with the driving module.

18. A host system comprising a host module and a power control circuit according to any one of claims 1-17, the host module being communicatively coupled to the processing module.