CN219329613U - Overvoltage protection circuit for power supply - Google Patents
Overvoltage protection circuit for power supply Download PDFInfo
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- CN219329613U CN219329613U CN202222918464.3U CN202222918464U CN219329613U CN 219329613 U CN219329613 U CN 219329613U CN 202222918464 U CN202222918464 U CN 202222918464U CN 219329613 U CN219329613 U CN 219329613U
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- resistor
- triode
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- power supply
- pmos tube
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Abstract
The utility model relates to the field of circuits and discloses a power supply overvoltage protection circuit which comprises a voltage stabilizing diode D1, a triode Q2, the voltage stabilizing diode D2 and a PMOS tube Q1. The source S of the PMOS transistor Q1 is connected with the power input end Vin, the drain D is connected with the power output end Vout, and the grid G is connected with the collector C of the triode Q2 and connected with GND. The base B of the triode Q2 is connected with the shunt resistor and then is connected with the input end Vin of the power supply, and the emitter E of the triode Q2 is connected with the input end Vin of the power supply. The anode of the zener diode D1 is connected with GND, and the cathode is respectively connected with the power input end Vin and the base B of the triode Q2. The anode of the voltage stabilizing diode D2 is connected with the collector C of the triode Q2, and the cathode is connected with the power input end Vin for protecting the PMOS tube Q1. The grid G of the PMOS tube is connected with a plurality of voltage dividing resistors. The circuit has a simple structure, needs fewer devices and nodes, reduces cost and power consumption, and reduces the risk of dead spots.
Description
Technical Field
The utility model relates to the field of circuits, in particular to a power supply overvoltage protection circuit.
Background
Overvoltage protection refers to a protection mode in which a power supply is disconnected or the voltage of a controlled device is reduced when the voltage of a protected line exceeds a predetermined maximum value. The overvoltage protection circuit is a necessary circuit for solving the problem of overvoltage, although the overvoltage protection circuit in the prior art can play a role in protecting a power supply, important components in the circuit cannot be protected in place, or the structure of the circuit is complex, more devices and nodes are needed, more devices cause higher cost and power consumption, and more nodes cause high risk of dead spots.
Disclosure of Invention
The utility model aims to solve the problems that the existing overvoltage protection circuit is complex in structure or components in the circuit cannot be protected in place, and provides a power supply overvoltage protection circuit which is simple in circuit structure, fewer in required components and nodes and capable of protecting the components in the circuit.
In order to achieve the above purpose, the present utility model adopts the following technical scheme:
the utility model discloses a power supply overvoltage protection circuit which comprises a voltage stabilizing diode D1, a triode Q2, the voltage stabilizing diode D2 and a PMOS tube Q1.
The triode Q2 is a PNP triode. The source electrode S of the PMOS tube Q1 is connected with the power input end Vin, the drain electrode D is connected with the power output end Vout, and the grid electrode G is connected with the collector electrode C of the triode Q2 and connected with GND. When Ug < Us, ugs < Ugs (th), the PMOS tube Q1 is conducted, namely the source electrode S and the drain electrode D are conducted, and the power circuit is communicated and works normally; on the contrary, the PMOS tube Q1 is not conducted, the power circuit is disconnected, and overvoltage protection is realized.
The base electrode B of the triode Q2 is connected with the shunt resistor and then connected with the input end Vin of the power supply, and the emitter electrode E of the triode Q2 is connected with the input end Vin of the power supply. The anode of the voltage stabilizing diode D1 is connected with GND, and the cathode of the voltage stabilizing diode D is connected with the power input end Vin and the base B of the triode Q2 respectively. And a grid electrode G of the PMOS tube is connected with a plurality of voltage dividing resistors.
When the input voltage Vin is greater than the normal input voltage, the input voltage is greater than the breakdown voltage Ubr of the zener diode D1, and the zener diode is broken down, and the upper voltage thereof is Ubr. The triode Q2 is conducted, uce is approximately equal to 0, therefore Ugs of Q1 is approximately equal to 0, the PMOS tube Q1 is not conducted, and the power circuit is disconnected, so that overvoltage protection is realized.
When Vin voltage is input into the normal range, the zener diode D1 is not broken down and does not enter a regulated state. The current through the shunt resistor is substantially 0. Ube=0 of transistor Q2, when transistor Q2 is in the off state. The Ugs of the PMOS tube Q1 is divided by a voltage dividing resistor, ug < Us, ugs < Ugs (th), and the PMOS tube is conducted, namely the power supply works normally.
The anode of the voltage stabilizing diode D2 is connected with the collector C of the triode Q2, and the cathode of the voltage stabilizing diode D is connected with the power input end Vin and used for protecting the PMOS tube Q1 to play a role in stabilizing and clamping voltage.
Further, the shunt resistor comprises a resistor R1 and a resistor R2, one end of the resistor R1 is connected with the power input end Vin, the other end of the resistor R1 is connected with one end of the resistor R2 and the cathode of the zener diode D1 respectively, and the other end of the resistor R2 is connected with the base electrode of the triode Q2.
Further, the voltage dividing resistor includes a resistor R3 and a resistor R4. One end of the resistor R3 is connected with the power input end Vin, and the other end of the resistor R is connected with the grid electrode G of the PMOS tube; one end of the resistor R4 is connected with the grid G of the PMOS tube Q1, and the other end of the resistor R is connected with GND.
The utility model has the advantages that:
the utility model controls the on-off of the triode by stabilizing the secondary clamping voltage, controls the on-off of the PMOS tube by the on-off of the triode, controls the on-off of the power supply circuit by the PMOS tube, limits the output voltage within the safe value range, and protects the post-stage electric equipment from damage. When the input voltage is greater than the normal voltage, the PMOS tube is disconnected, and the power supply circuit is disconnected, so that overvoltage protection is realized; when the input voltage is in the normal range, the PMOS tube is conducted, and the power supply circuit works normally. Meanwhile, a voltage stabilizing diode D2 is connected in parallel beside the PMOS, so that the PMOS is subjected to double protection.
Drawings
Fig. 1 is a circuit diagram of the present utility model.
Detailed Description
In order to enable those skilled in the art to better understand the technical solutions of the present utility model, the present utility model will be described in further detail with reference to the accompanying drawings and specific embodiments.
As shown in fig. 1, the utility model discloses a power supply overvoltage protection circuit, which comprises a zener diode D1, a triode Q2, a zener diode D2, a PMOS transistor Q1, a shunt resistor and a divider resistor. Wherein the triode Q2 is a PNP triode.
The concrete connection is as follows:
the source S of the PMOS tube Q1 is connected with the power input end Vin, the drain D is connected with the power output end Vout, the grid G is connected with the collector C of the triode Q2, and the grid G of the PMOS tube is connected with a plurality of voltage dividing resistors. Specifically, the voltage dividing resistor includes a resistor R3 and a resistor R4. One end of the resistor R3 is connected with the power input end Vin, and the other end of the resistor R is connected with the grid G of the PMOS tube; one end of the resistor R4 is connected with the grid G of the PMOS tube Q1, and the other end of the resistor R is connected with GND. When Ug < Us, ugs < Ugs (th), the PMOS tube Q1 is conducted, namely the source electrode S and the drain electrode D are conducted, and the power circuit is communicated and works normally; on the contrary, the PMOS tube Q1 is not conducted, the power circuit is disconnected, and overvoltage protection is realized.
The base B of the triode Q2 is connected with the shunt resistor and then is connected with the input end Vin of the power supply. Specifically, the shunt resistor comprises a resistor R1 and a resistor R2, one end of the resistor R1 is connected with the power input end Vin, the other end of the resistor R1 is respectively connected with one end of the resistor R2 and the cathode of the zener diode D1, and the other end of the resistor R2 is connected with the base electrode of the triode Q2. The anode of the zener diode D1 is connected to GND. An emitter E of the triode Q2 is connected with a power input end Vin, and a collector C of the triode Q2 is connected with a grid G of the PMOS tube Q1.
When the input voltage Vin is greater than the normal input voltage, the input voltage is greater than the breakdown voltage Ubr of the zener diode D1, and the zener diode is broken down, and the upper voltage thereof is Ubr. The triode Q2 is conducted, uce is approximately equal to 0, therefore Ugs of Q1 is approximately equal to 0, the PMOS tube Q1 is not conducted, and the power circuit is disconnected, so that overvoltage protection is realized.
When Vin voltage is input into the normal range, the zener diode D1 is not broken down and does not enter a regulated state. The current flowing through the resistors R1 and R2 is substantially 0. Ube=0 of transistor Q2, when transistor Q2 is in the off state. After the Ugs of the PMOS tube Q1 is divided by the divider resistor, ugs is smaller than Ugs (th), and the PMOS tube is conducted, namely the power supply works normally.
The anode of the voltage stabilizing diode D2 is connected with the collector C of the triode Q2, and the cathode of the voltage stabilizing diode D is connected with the power input end Vin and used for protecting the PMOS tube Q1 to play a role in stabilizing and clamping voltage.
In summary, the utility model controls the on-off of the power supply circuit through the PMOS tube, limits the output voltage within the safe value range, and protects the electric equipment at the later stage from damage. When the input voltage is greater than the normal voltage, the PMOS tube is disconnected, and the power supply circuit is disconnected, so that overvoltage protection is realized; when the input voltage is in the normal range, the PMOS tube is conducted, and the power supply circuit works normally. Meanwhile, a voltage stabilizing diode D2 is connected in parallel beside the PMOS, so that the PMOS is subjected to double protection.
The present utility model is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present utility model are intended to be included in the scope of the present utility model.
Claims (3)
1. The utility model provides a power overvoltage protection circuit which characterized in that: the transistor comprises a voltage stabilizing diode D1, a triode Q2, a voltage stabilizing diode D2 and a PMOS tube Q1; the triode Q2 is a PNP triode; the source electrode S of the PMOS tube Q1 is connected with the power input end Vin, the drain electrode D is connected with the power output end Vout, the grid electrode G is connected with the collector electrode C of the triode Q2 and connected with GND; the base electrode B of the triode Q2 is connected with the shunt resistor and then connected with the input end Vin of the power supply, and the emitter electrode E of the triode Q2 is connected with the input end Vin of the power supply; the anode of the voltage stabilizing diode D1 is connected with GND, and the cathode of the voltage stabilizing diode D is respectively connected with the power input end Vin and the base B of the triode Q2; the positive pole of zener diode D2 is connected with triode Q2's collecting electrode C, and the negative pole is connected with power input Vin for protection PMOS pipe Q1, PMOS pipe's grid G is connected with a plurality of bleeder resistors.
2. The power supply overvoltage protection circuit of claim 1, wherein: the shunt resistor comprises a resistor R1 and a resistor R2, one end of the resistor R1 is connected with a power input end Vin, the other end of the resistor R1 is connected with one end of the resistor R2 and a cathode of a zener diode D1 respectively, and the other end of the resistor R2 is connected with a base electrode of a triode Q2.
3. The power supply overvoltage protection circuit of claim 1, wherein: the voltage dividing resistor comprises a resistor R3 and a resistor R4; one end of the resistor R3 is connected with the power input end Vin, and the other end of the resistor R is connected with the grid electrode G of the PMOS tube; one end of the resistor R4 is connected with the grid G of the PMOS tube Q1, and the other end of the resistor R is connected with GND.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222918464.3U CN219329613U (en) | 2022-10-31 | 2022-10-31 | Overvoltage protection circuit for power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202222918464.3U CN219329613U (en) | 2022-10-31 | 2022-10-31 | Overvoltage protection circuit for power supply |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN219329613U true CN219329613U (en) | 2023-07-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202222918464.3U Active CN219329613U (en) | 2022-10-31 | 2022-10-31 | Overvoltage protection circuit for power supply |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN219329613U (en) |
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2022
- 2022-10-31 CN CN202222918464.3U patent/CN219329613U/en active Active
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