CN219320766U - Double MIPI transmission circuit board - Google Patents

Double MIPI transmission circuit board Download PDF

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Publication number
CN219320766U
CN219320766U CN202320326727.3U CN202320326727U CN219320766U CN 219320766 U CN219320766 U CN 219320766U CN 202320326727 U CN202320326727 U CN 202320326727U CN 219320766 U CN219320766 U CN 219320766U
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interface module
circuit board
transmission circuit
interface
mipi
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黎威
王江
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Shenzhen Shenghangte Technology Co ltd
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Shenzhen Shenghangte Technology Co ltd
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The utility model provides a double MIPI transmission circuit board, which comprises a first interface module, a second interface module and a main control component; the main control component is electrically connected with the first interface module and the second interface module respectively; the first interface module is used for receiving the graphic image signal of the tablet personal computer and outputting a first electric signal after the graphic image signal is subjected to signal processing; the main control assembly is used for receiving the first electric signal of the first interface module and outputting a corresponding second electric signal to the second interface module; the second interface module is used for receiving a second electric signal of the main control assembly and outputting a display signal to an external display screen after the second electric signal is subjected to signal processing. According to the utility model, the FPGA chip is used as a bridge circuit between the first interface module and the second interface module, so that the signal transmission efficiency of MIPI on the circuit board is improved.

Description

Double MIPI transmission circuit board
Technical Field
The utility model relates to the technical field of circuit boards, in particular to a double MIPI transmission circuit board.
Background
With the development of intelligent mobile devices, the frequency of a processor of the mobile device is continuously increased, the amount of data to be transmitted is also continuously increased, and the traditional data interface cannot meet the requirements of high performance and high speed. The MIPI (Mobile Industry Processor Interface is abbreviated as MIPI) protocol promotes the establishment of the interface specification of the mobile application processor, for example, CSI (camera interface)/DSI (double MIPI output screen interface) is widely applied in the fields of virtual reality helmets, unmanned aerial vehicles, smart phones, tablet computers, cameras, wearable devices, human-computer interfaces and the like. The application of the CSI/DSI interface mainly realizes the data transmission between the image sensor and the processor as well as between the processor and the display, and a bridge circuit is needed to be added for realizing the data output between the processor and the image sensor as well as between the processor and the display. The bridge circuit is usually implemented by a main control component, however, signal interference and shielding heat dissipation phenomena are inevitably encountered in the process of signal transmission by the main control component, so that the signal transmission efficiency of the MIPI circuit board is reduced.
Disclosure of Invention
The utility model aims to provide a double MIPI transmission circuit board, aiming at improving the signal transmission efficiency of MIPI on the circuit board.
Therefore, the utility model provides a double MIPI transmission circuit board, which comprises a first interface module, a second interface module and a main control component; the main control component is electrically connected with the first interface module and the second interface module respectively;
the first interface module is used for receiving a graphic image signal of the tablet personal computer, and outputting a first electric signal after the graphic image signal is subjected to signal processing;
the main control assembly is used for receiving the first electric signal of the first interface module and outputting a corresponding second electric signal to the second interface module;
the second interface module is used for receiving the second electric signal of the main control assembly and outputting a display signal to an external display screen after the second electric signal is subjected to signal processing.
Optionally, the MIPI transmission circuit board further includes a power management component;
the power management component is respectively connected with a power end and the second interface module;
the power management component is used for converting the voltage of the power supply end to output analog voltage, first pixel voltage and second pixel voltage to the second interface module respectively.
Optionally, the MIPI transmission circuit board further includes a voltage conversion component;
the voltage conversion component is connected with the power supply end;
the voltage conversion component is used for boosting or reducing the voltage of the power supply end and then outputting the voltage to the second interface module.
Optionally, the MIPI transmission circuit board further includes a conversion socket;
the conversion socket is arranged between the second interface module and an external display screen;
the conversion socket is used for enabling the second interface module to be compatible with an external display screen.
Optionally, the dual MIPI transmission circuit board further includes:
MIPI transmission circuit board body;
the first interface module, the second interface module and the main control component are all arranged on the surface of the MIPI transmission circuit board.
Optionally, a metal sheet is arranged on the back surface of the MIPI transmission circuit board.
Optionally, the first interface module includes a camera interface;
the camera interface is used for being connected with the tablet personal computer.
Optionally, the second interface module includes a dual MIPI output screen interface;
the dual MIPI output screen interface is used for being connected with an external display screen.
Optionally, the camera interface includes at least one set of differential data signal lines and at least one set of differential clock lines.
Optionally, the dual MIPI output screen interface includes at least one set of differential data signal lines and at least one set of differential clock lines.
The utility model provides a double MIPI transmission circuit board, which comprises a first interface module, a second interface module and a main control component; the main control component is electrically connected with the first interface module and the second interface module respectively; the first interface module is used for receiving the graphic image signal of the tablet personal computer and outputting a first electric signal after the graphic image signal is subjected to signal processing; the main control assembly is used for receiving the first electric signal of the first interface module and outputting a corresponding second electric signal to the second interface module; the second interface module is used for receiving a second electric signal of the main control assembly and outputting a display signal to an external display screen after the second electric signal is subjected to signal processing. The first interface module comprises a camera interface, and the second interface module comprises a double MIPI output screen interface; the camera interface is used for receiving a graphic image signal of the tablet personal computer and outputting a first electric signal after the graphic image signal is subjected to signal processing; the double MIPI output screen interface is used for receiving a second electric signal of the main control assembly, and outputting a display signal to an external display screen after the second electric signal is subjected to signal processing; the utility model takes the FPGA chip as the main control component to become a bridge circuit between the camera interface and the double MIPI output screen interface, thereby improving the signal transmission efficiency of MIPI on the circuit board.
Drawings
In order to more clearly illustrate the embodiments of the present utility model or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, and it is obvious that the drawings in the following description are only some embodiments of the present utility model, and other drawings may be obtained according to the structures shown in these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a circuit function module of a dual MIPI transmission circuit board according to the present utility model;
fig. 2 is a schematic diagram of a circuit function module of another embodiment of the dual MIPI transmission circuit board of the present utility model;
fig. 3 is a schematic diagram of a circuit function module of another embodiment of the dual MIPI transmission circuit board of the present utility model;
fig. 4 is a schematic circuit diagram of a dual MIPI transmission circuit board according to the present utility model;
fig. 5 is a circuit structure diagram of another embodiment of the dual MIPI transmission circuit board of the present utility model.
The achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the utility model. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It should be noted that, if directional indications (such as up, down, left, right, front, and rear … …) are included in the embodiments of the present utility model, the directional indications are merely used to explain the relative positional relationship, movement conditions, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indications are correspondingly changed.
In addition, if there is a description of "first", "second", etc. in the embodiments of the present utility model, the description of "first", "second", etc. is for descriptive purposes only and is not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, if the meaning of "and/or" is presented throughout this document, it is intended to include three schemes in parallel, taking "a and/or B" as an example, including a scheme, or B scheme, or a scheme where a and B meet simultaneously. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be considered to be absent and not within the scope of protection claimed in the present utility model.
It should be understood that, with the development of intelligent mobile devices, the frequency of the processor of the mobile device is continuously increased, and the amount of data to be transmitted is also continuously increased, so that the conventional data interface cannot meet the requirements of high performance and high speed. The MIPI (Mobile Industry Processor Interface is abbreviated as MIPI) protocol promotes the establishment of the interface specification of the mobile application processor, for example, CSI (camera interface)/DSI (double MIPI output screen interface) is widely applied in the fields of virtual reality helmets, unmanned aerial vehicles, smart phones, tablet computers, cameras, wearable devices, human-computer interfaces and the like. The application of the CSI/DSI interface mainly realizes the data transmission between the image sensor and the processor as well as between the processor and the display, and a bridge circuit is needed to be added for realizing the data output between the processor and the image sensor as well as between the processor and the display. The bridge circuit is usually implemented by a main control component, however, signal interference and shielding heat dissipation phenomena are inevitably encountered in the process of signal transmission by the main control component, so that the signal transmission efficiency of the MIPI circuit board is reduced.
The utility model provides a double MIPI transmission circuit board, which comprises a first interface module 20, a second interface module 40 and a main control component 30; the main control assembly 30 is electrically connected with the first interface module 20 and the second interface module 40 respectively;
the first interface module 20 is configured to receive a graphic image signal of the tablet pc 10, and output a first electrical signal after the graphic image signal is subjected to signal processing;
the main control assembly 30 is configured to receive the first electrical signal of the first interface module 20 and output a corresponding second electrical signal to the second interface module 40;
the second interface module 40 is configured to receive the second electrical signal of the main control assembly 30, and output a display signal to the external display screen 50 after the second electrical signal is subjected to signal processing.
It will be appreciated that in this embodiment, the first interface module 20 is implemented using a camera interface CSI, and the second interface module 40 is implemented using a dual MIPI output screen interface DSI. The camera interface CSI is a bridge for establishing communication between the tablet computer 10 and the main control component 30, and can be understood as an input interface of graphic image data. Specifically, the camera interface CSI is used for transmitting the graphic image data input by the tablet pc 10 to the main control component 30, and outputting the graphic image data to the dual MIPI output screen interface DSI after the signal processing of the main control component 30. Further, the dual MIPI output screen interface DSI is a bridge for establishing communication between the main control component 30 and the external display screen 50, and can be understood as an output interface of graphic image data, and specifically, the dual MIPI output screen interface DSI is configured to output corresponding display data to the external display screen 50 after the graphic image data of the main control component 30 is subjected to signal processing, so that the external display screen 50 performs corresponding image display according to the received display data.
In this embodiment, the graphic image signal corresponds to the graphic image data input by the tablet pc 10, and can be used for being received and read by the camera interface CSI; the first electrical signal is a graphic image signal after signal processing, and can be received and read by the main control component 30; the second electric signal corresponds to the first electric signal after signal processing and can be used for being received and read by the double MIPI output screen interface DSI; the display signal corresponds to a second electrical signal after signal processing, and can be used for being received and read by the external display screen 50.
Alternatively, the master control assembly 30 may be implemented using a master control chip, such as an MCU, a DSP (Digital Signal Process, digital signal processing chip), an FPGA (Field Programmable Gate Array, programmable gate array chip), or the like. In this embodiment, the main control component 30 is implemented by using an FPGA chip, so that the FPGA chip has abundant on-chip resources, so that the high-speed data transmission function of the camera interface CSI and the dual MIPI output screen interface DSI can be implemented, and the device has the characteristics of fast operation speed, high performance, low power consumption, low cost and the like.
Specifically, in practical application of the dual MIPI transmission circuit board, the camera interface CSI receives the graphics image signal input by the tablet pc 10, processes the graphics image signal, outputs a first electrical signal that can be received and read by the FPGA chip, and outputs the first electrical signal to the FPGA chip. Further, after receiving the first electrical signal, the FPGA chip outputs a second electrical signal corresponding to the first electrical signal to the dual MIPI output screen interface DSI, so that the dual MIPI output screen interface DSI can receive and read the second electrical signal, and output the second electrical signal to the dual MIPI output screen interface DSI. Further, the dual MIPI output screen interface DSI outputs a display signal that can be received and read by the external display screen 50 after receiving the second electrical signal, and outputs the display signal to the external display screen 50, so that the external display screen 50 displays a graphic image corresponding to the display signal.
The utility model provides a double MIPI transmission circuit board, which comprises a first interface module 20, a second interface module 40 and a main control component 30; the main control assembly 30 is electrically connected with the first interface module 20 and the second interface module 40 respectively; the first interface module 20 is configured to receive a graphics image signal of the tablet computer 10, and output a first electrical signal after the graphics image signal is subjected to signal processing; the main control assembly 30 is configured to receive the first electrical signal of the first interface module 20 and output a corresponding second electrical signal to the second interface module 40; the second interface module 40 is configured to receive the second electrical signal of the main control assembly 30, and output a display signal to the external display screen 50 after the second electrical signal is subjected to signal processing. Wherein the first interface module 20 includes a camera interface CSI, and the second interface module 40 includes a dual MIPI output screen interface DSI; the camera interface CSI is used for receiving a graphic image signal of the tablet personal computer, and outputting a first electric signal after the graphic image signal is subjected to signal processing; the dual MIPI output screen interface DSI is configured to receive the second electrical signal of the main control assembly 30, and output a display signal to the external display screen 50 after the second electrical signal is subjected to signal processing; the utility model takes the FPGA chip as the main control component 30 to become a bridging circuit between the CSI double MIPI output screen interface of the camera interface and the DSI, thereby improving the signal transmission efficiency of MIPI on the circuit board.
In this embodiment, referring to fig. 3 and 4, the MIPI transmission circuit board further includes a power management component 60;
the power management component 60 is connected with a power end and the second interface module 40 respectively;
the power management component 60 is configured to convert a voltage of a power supply terminal to output an analog voltage, a first pixel voltage, and a second pixel voltage to the second interface module 40.
It should be appreciated that the external display screen 50 in this embodiment is implemented using an OLED. For the external display screen OLED, the analog voltage AVDD is supplied to the internal analog circuit portion of the display screen, and the voltage is usually 5.6-7.9 v. The first pixel voltage ELVDD and the second pixel voltage ELVSS supply power to a display pixel circuit of the display screen, and in addition, the first pixel voltage ELVDD is fixed and not adjustable, and is 4.6V; the second pixel voltage ELVSS is adjustable, typically at-1.4 to-5.4V, and can be changed by ESWIRE pin communication.
In this embodiment, the power management component 60 is implemented by using a power management chip U1, where the power management chip U1 has a power pin, an analog voltage pin, a first pixel voltage pin, and a second pixel voltage pin, and the first power pin SW1, the second power pin SW2, and the third power pin SW3 are all power pins of the power management chip U1. Specifically, in practical application, the 3.3V voltage output by the power supply terminal is output to the power supply pin of the power management chip U1 through the first inductor L1, the second inductor L2 and the third inductor L3, respectively; the power management chip U1 converts the 3.3V power voltage received by the power pin into an analog voltage AVDD, and outputs the analog voltage AVDD to the dual MIPI output screen interface (the second interface module 40) through the analog voltage pin VO3, converts the power terminal 3.3V voltage into a first pixel voltage ELVDD, and outputs the first pixel voltage ELVDD to the dual MIPI output screen interface (the second interface module 40), and converts the power terminal 3.3V voltage into a second pixel voltage ELVSS, and outputs the second pixel voltage ELVSS to the dual MIPI output screen interface (the second interface module 40). Further, the dual MIPI output screen interface (second interface module 40) outputs the analog voltage AVDD to the internal analog circuit of the external display screen OLED, and outputs the first pixel voltage ELVDD and the second pixel voltage ELVSS to the display pixel circuit of the display screen OLED through the first pixel voltage foot VO1 and the second pixel voltage foot VO2, respectively, to supply power to the internal analog circuit and the display pixel circuit of the display screen OLED.
In this embodiment, referring to fig. 3 and 5, the MIPI transmission circuit board further includes a voltage conversion component 70;
the voltage conversion assembly 70 is connected with a power end;
the voltage conversion module 70 is configured to boost or step down the voltage of the power supply terminal, and output the boosted or stepped down voltage to the second interface module 40.
It should be understood that, for the external display screen OLED, the external display screen OLED requires the core voltage VCI, the driving voltage LDVCC, and the interface voltage VDDI in addition to the analog voltage AVDD, the first pixel voltage ELVDD, and the second pixel voltage ELVSS described above; the core voltage VCI is used to power the core circuit of the display OLED. The driving voltage LDVCC is used to power the driving circuit of the display screen OLED and the 1.8V interface voltage VDDI is used to power the dual MIPI output screen interface.
In the present embodiment, the voltage conversion assembly 70 includes a first voltage conversion chip U2; the first voltage conversion chip U2 has a power supply pin IN1 and an output pin OUT1. Specifically, IN practical application, the first voltage conversion chip U2 steps down the 3.3V power supply voltage received by the power supply pin IN1 to the 2.8V core voltage VCI, and outputs the voltage to the dual MIPI output screen interface DSI (the second interface module 40) through the output pin OUT1 after passing through the first resistor R1, so that the dual MIPI output screen interface DSI (the second interface module 40) outputs the 2.8V core voltage VCI to the core circuit of the display screen OLED to supply power to the core circuit of the display screen OLED.
Further, the voltage conversion assembly 70 further includes a second voltage conversion chip U3; the second voltage conversion chip U3 has a power supply pin IN2 and an output pin OUT2. Specifically, IN practical application, the second voltage conversion chip U3 steps down the 3.3V power supply voltage received by the power supply pin IN2 to the 2.5V driving voltage LDVCC, outputs the voltage through the output pin OUT2, and outputs the voltage to the dual MIPI output screen interface DSI (the second interface module 40) after passing through the second resistor R2, so that the dual MIPI output screen interface DSI (the second interface module 40) outputs the 2.5V driving voltage LDVCC to the driving circuit of the display screen OLED to supply power to the driving circuit of the display screen OLED.
Further, the voltage conversion assembly 70 further includes a third voltage conversion chip U4; the third voltage conversion chip U4 has a power supply pin IN3 and an output pin OUT3. Specifically, in practical application, the 3.3V power supply voltage received by the power supply pin of the third voltage conversion chip U4 is reduced to 1.8V interface voltage VDDI, and is output through the output pin OUT3, and then is output to the dual MIPI output screen interface DSI (the second interface module 40) through the third resistor R3, so that the dual MIPI output screen interface DSI (the second interface module 40) of the display screen OLED is powered.
In this embodiment, the MIPI transmission circuit board further includes a conversion socket;
the conversion socket is arranged between the second interface module 40 and the external display screen 50;
the conversion socket is used for making the second interface module 40 compatible with the external display screen 50.
It will be appreciated that the function of the conversion socket is to make the second interface module 40 of the circuit board compatible with different plugs of external devices. The conversion socket, also known as a universal plug and a three-to-two socket, means converting one plug into another. The plug is convenient for a user to use external equipment with different types of plugs so as to solve the problem that different electric appliances are not universal.
In this embodiment, referring to fig. 3, the dual MIPI transmission circuit board further includes:
a circuit board;
the first interface module 20, the second interface module 40 and the main control assembly 30 are all disposed on the surface of the circuit board.
It can be understood that the circuit board can also be called as a PCB board, and is made of an insulating board as a substrate material, cut into a certain size, attached with at least one conductive pattern, and distributed with holes, so as to replace the chassis of the electronic components of the conventional device and realize interconnection between the electronic components.
In the present embodiment, the first interface module 20, the second interface module 40 and the main control assembly 30 are all disposed on the surface of the circuit board. In addition, the power management component 60 and the voltage conversion component 70 are both disposed on the surface of the circuit board. Thereby enabling interconnection communication among the first interface module 20, the second interface module 40, the main control module 30, the power management module 60, and the voltage conversion module 70.
Further, referring to fig. 3, the back surface of the circuit board is provided with a metal sheet.
It should be understood that the main control component 30 in this embodiment is implemented by using an FPGA chip, so as to establish communication links between the camera interface CSI, the FPGA chip and the dual MIPI output screen interface DSI. However, most of the current programmable logic array (FPGA) chips are voltage sensitive chips, and have a basic unit structure, and data are volatile, work in a low-voltage state and are easily interfered, and especially in some external environments with severe electromagnetic environments, circuit coupling and clutter pulses of space radiation can affect the stability of the operation of the FPGA chips. In this embodiment, when the working stability of the FPGA chip is affected by the clutter pulses of the spatial radiation, even when the operation of the FPGA chip is interfered by the outside, and in a state where the interference exceeds a certain level, the phenomenon similar to snowflake flash appears on the screen of the external display screen OLED.
Therefore, in the present embodiment, the back surface of the circuit board is provided with a metal sheet for shielding the interference signal and dissipating heat, and the metal sheet is integrally connected to the back surface of the circuit board. The metal sheet has shielding effect on clutter pulses radiated from the external space, and reduces the influence of the clutter pulses on the operation of the FPGA chip. In addition, the metal sheet can also be used for heat dissipation, and electronic components, especially FPGA chips, are small in size and high in integration level, and can generate a large amount of heat during operation, so that the temperature of the circuit board rises, and the circuit board with too high temperature can burn out other devices, such as the first interface module 20 and the second interface module 40; the metal sheet is arranged on the back of the circuit board, so that heat generated by the FPGA chip can be conducted, and the heat is emitted to the external environment, so that the overhigh temperature of each device on the circuit board is avoided. The metal sheet provided by the embodiment has the characteristics of simple structure, interference signal shielding, heat dissipation and prolonged service life of the MIPI circuit board.
In this embodiment, referring to fig. 2, the first interface module 20 includes a camera interface;
the camera interface is used for being connected with the tablet personal computer 10.
It may be appreciated that the camera interface CSI is a camera interface of MIPI, and is used to connect to the tablet computer 10 to establish a bridge for the tablet computer 10 and the master control assembly 30 to communicate.
Specifically, in practical application, the camera interface CSI outputs a first electrical signal to the main control component 30 after processing a graphics image signal input by the tablet computer 10, and the main control component 30 outputs a corresponding second electrical signal to the dual MIPI output screen interface DSI after processing the first electrical signal.
Further, referring to fig. 2, the second interface module 40 includes a dual MIPI output screen interface;
the dual MIPI output screen interface is configured to connect to an external display screen OLED.
It will be appreciated that the dual MIPI output screen interface DSI is a dual MIPI output screen interface of MIPI for connecting to the external display screen OLED, establishing a bridge for the communication between the master control assembly 30 and the external display screen OLED.
Specifically, in practical application, the dual MIPI output screen interface DSI receives the second electrical signal of the main control assembly 30, and outputs a display signal to the external display screen OLED after the second electrical signal is subjected to signal processing, so that the external display screen OLED makes a corresponding image display according to the received display signal.
In this embodiment, referring to fig. 2, the camera interface includes at least one set of differential data signal lines and at least one set of differential clock lines.
It should be appreciated that the camera interface CSI generally includes a data bus, a clock bus, a synchronization signal line control line, and the like. Therefore, the physical interface CSI of the camera occupies more data lines, the logic design is complex, the strict synchronization is required to include horizontal synchronization signals, vertical synchronization signals and clock signals, and high requirements are provided for one end of the camera and one end of the processor. Meanwhile, in the high-speed transmission process, the direct use of the digital signal as data is easy to be interfered by other external signals, and compared with the stability of differential signals, the transmission rate of the digital signal is greatly limited, and the maximum real-time transmission graphic image quality of a camera is greatly limited.
The data transmission process based on the camera interface CSI uses the data differential signals to transmit pixel values in the video, meanwhile, the camera interface CSI can be reduced or expanded very flexibly, and for application scenes with fewer interfaces, the camera interface CSI can complete the data serial transmission process of the camera by only using one group of differential data signal lines and one group of differential clock lines, so that the load is reduced, and meanwhile, a certain transmission rate can be met. For a large-array CCD camera, the camera interface CSI can also expand differential data lines, so that the high-speed requirement of parallel transmission of multiple groups of data lines is met.
Further, referring to fig. 2, the dual MIPI output screen interface includes at least one set of differential data signal lines and at least one set of differential clock lines.
It should be appreciated that the dual MIPI output screen interface DSI generally includes a data bus, a clock bus, a synchronization signal line control line, and the like. Therefore, the display screen physical interface DSI occupies more data lines, the logic design is complex, and strict synchronization is required to include horizontal synchronization signals, vertical synchronization signals and clock signals, which puts high requirements on one end of the display screen and one end of the processor. Meanwhile, in the high-speed transmission process, the direct use of the digital signal as data is easy to be interfered by other external signals, and compared with the stability of differential signals, the transmission rate of the digital signal is greatly limited, and the maximum real-time transmission graphic image quality of a camera is greatly limited.
The data transmission process based on the double MIPI output screen interface DSI uses data differential signals to transmit pixel values in video, meanwhile, the double MIPI output screen interface DSI can be very flexible to simplify or expand, and for application scenes with fewer interfaces, the double MIPI output screen interface DSI can complete the data serial transmission process of the processor by only using one group of differential data signal lines and one group of differential clock lines, so that the load is reduced, and meanwhile, a certain transmission rate can be met. For a display screen with more interfaces, the differential data lines of the double MIPI output screen interfaces DSI can be expanded, so that the high-speed requirement of parallel transmission of multiple groups of data lines is met.
The foregoing description is only of the preferred embodiments of the present utility model and is not intended to limit the scope of the utility model, and all equivalent structural changes made by the description of the present utility model and the accompanying drawings or direct/indirect application in other related technical fields are included in the scope of the utility model.

Claims (10)

1. The double MIPI transmission circuit board is characterized by comprising a first interface module, a second interface module and a main control component; the main control component is electrically connected with the first interface module and the second interface module respectively;
the first interface module is used for receiving a graphic image signal of the tablet personal computer, and outputting a first electric signal after the graphic image signal is subjected to signal processing;
the main control assembly is used for receiving the first electric signal of the first interface module and outputting a corresponding second electric signal to the second interface module;
the second interface module is used for receiving the second electric signal of the main control assembly and outputting a display signal to an external display screen after the second electric signal is subjected to signal processing.
2. The dual MIPI transmission circuit board as defined in claim 1, wherein the MIPI transmission circuit board further comprises a power management component;
the power management component is respectively connected with a power end and the second interface module;
the power management component is used for converting the voltage of the power supply end to output analog voltage, first pixel voltage and second pixel voltage to the second interface module respectively.
3. The dual MIPI transmission circuit board as defined in claim 1, wherein the MIPI transmission circuit board further comprises a voltage conversion assembly;
the voltage conversion component is connected with the power supply end;
the voltage conversion component is used for boosting or reducing the voltage of the power supply end and then outputting the voltage to the second interface module.
4. The dual MIPI transmission circuit board as defined in claim 1, wherein the MIPI transmission circuit board further comprises a conversion socket;
the conversion socket is arranged between the second interface module and an external display screen;
the conversion socket is used for enabling the second interface module to be compatible with an external display screen.
5. The dual MIPI transmission circuit board as defined in claim 1, wherein the dual MIPI transmission circuit board further comprises:
MIPI transmission circuit board body;
the first interface module, the second interface module and the main control component are all arranged on the surface of the MIPI transmission circuit board.
6. The dual MIPI transmission circuit board as claimed in claim 1, wherein the back side of the MIPI transmission circuit board is provided with a metal foil.
7. The dual MIPI transmission circuit board as defined in claim 1, wherein the first interface module comprises a camera interface;
the camera interface is used for being connected with the tablet personal computer.
8. The dual MIPI transmission circuit board as claimed in claim 1, wherein the second interface module comprises a dual MIPI output screen interface;
the dual MIPI output screen interface is used for being connected with an external display screen.
9. The dual MIPI transmission circuit board as defined in claim 7, wherein the camera interface comprises at least one set of differential data signal lines and at least one set of differential clock lines.
10. The dual MIPI transmission circuit board of claim 8, wherein the dual MIPI output screen interface comprises at least one set of differential data signal lines and at least one set of differential clock lines.
CN202320326727.3U 2023-02-27 2023-02-27 Double MIPI transmission circuit board Active CN219320766U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202320326727.3U CN219320766U (en) 2023-02-27 2023-02-27 Double MIPI transmission circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202320326727.3U CN219320766U (en) 2023-02-27 2023-02-27 Double MIPI transmission circuit board

Publications (1)

Publication Number Publication Date
CN219320766U true CN219320766U (en) 2023-07-07

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ID=87031014

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202320326727.3U Active CN219320766U (en) 2023-02-27 2023-02-27 Double MIPI transmission circuit board

Country Status (1)

Country Link
CN (1) CN219320766U (en)

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