CN219304820U - Pull-up control circuit, I/O bus, chip system and related equipment - Google Patents

Abstract

The application provides a pull-up control circuit, I/O bus, chip system and relevant equipment, pull-up control circuit includes: a high-voltage selecting output circuit for selecting a high-voltage output from VDD and PAD; the voltage pull-up module, the voltage pull-up module includes: the source electrode of the first PMOS tube is connected with the VDD, the drain electrode of the first PMOS tube is connected with the I/O port, and the substrate is connected with the output end of the high-voltage selecting output circuit; the source electrode of the second PMOS tube is connected with the PAD, the grid electrode of the second PMOS tube is connected with the VDD, the substrate is connected with the output end of the high-voltage output circuit, and the drain electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube; the output end of the control circuit is connected with the grid electrode of the first PMOS tube and is used for outputting a low-level signal when the PAD is smaller than or equal to VDD; when PAD is greater than VDD, no signal is output. The method and the device can effectively prevent current from flowing backwards from the I/O port to the power supply when the voltage of the I/O port is larger than the voltage of the power supply, and cause disorder of the system.

Description

Pull-up control circuit, I/O bus, chip system and related equipment

Technical Field

The present disclosure relates to the field of integrated circuits, and more particularly, to a pull-up control circuit, an I/O bus, a chip, a system-on-a-chip, and related devices.

Background

As shown in fig. 1, in the design of GPIO (General-purpose input/output), a pull-up resistor R1 is generally designed to prevent IO bus (input/output bus) from being in a floating state. When TX (transmitter) is turned off, i.e. at PAD in the figure, the I/O port is in Hi-Z (high impedance state), if RX (receiver) is not turned off, there is a larger leakage current in RX, and a pull-up resistor with a larger impedance value can pull up the voltage PAD of the I/O port to VDD, eliminating Hi-Z state. In addition, in the system with the bus structure, one master control chip can control a plurality of slave chips through the bus, when a certain slave chip is not selected by the master control chip, the slave chip can be temporarily powered off to achieve the purpose of saving electricity, but at the moment, the control signal of the bus is still powered on, if a pull-up resistor is arranged on the bus, the voltage PAD on the bus can flow back into the slave chip through the pull-up resistor, and therefore the slave chip can be activated by mistake to generate system disorder.

Therefore, in the conventional pull-up resistor design, in the case of Tolerant application (i.e. the chip has power, the I/O port has power, and the voltage PAD of the I/O port is higher than the voltage VDD of the power supply of the chip), or in the case of Failsafe application (i.e. the chip has no power, the I/O port has power), there is a current flowing back from the I/O port to the power supply, which may cause system confusion.

Disclosure of Invention

An objective of the embodiments of the present application is to provide a pull-up control circuit, an I/O bus, a chip system and related devices, which are used for solving the above-mentioned problems.

The embodiment of the application provides a pull-up control circuit, which comprises: a high-voltage selection output circuit for selecting a high-voltage output from VDD (power supply voltage) and PAD (voltage of an I/O port of a bus); a voltage pull-up module, the voltage pull-up module comprising: the source electrode of the first PMOS tube is connected with the VDD, the drain electrode of the first PMOS tube is connected with the I/O port, and the substrate is connected with the output end of the high-voltage output circuit; the source electrode of the second PMOS tube is connected with the PAD, the grid electrode of the second PMOS tube is connected with the VDD, the substrate is connected with the output end of the selected high-voltage output circuit, and the drain electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube; and the output end of the control circuit is connected with the grid electrode of the first PMOS tube and is used for outputting a low-level signal when the PAD is smaller than or equal to the VDD and not outputting a signal when the PAD is larger than the VDD.

It should be understood that there are two forms of PMOS tube conduction:

1. and the conduction condition from the source electrode to the drain electrode of the PMOS tube. The conduction condition from the source electrode to the drain electrode of the PMOS tube is as follows: the source voltage V (S) is larger than the drain voltage V (D), namely V (S) > V (D), and the gate voltage V (G) -V (S) < Vthp, vthp is the threshold voltage of the PMOS tube;

2. the PMOS tube is conducted in a PN junction mode. In the process manufacturing, three ends of a source electrode, a substrate and a drain electrode of the PMOS tube are respectively P-type injection, N-type injection and P-type injection PNP-type PN junctions. So the drain to substrate is a P to N PN junction, which turns on if the drain voltage V (D) is greater than the substrate voltage V (B). At this time, since the substrate of the PMOS transistor is usually connected to the source, a current from the drain to the source is formed by conducting between the drain and the source (this also results in that if the pull-up resistor in fig. 1 is directly replaced by a conventional PMOS transistor, the current is not prevented from flowing backward from the I/O port to the power supply in the case of Tolerant application or Failsafe application).

Through the implementation structure, when the device works normally, namely the PAD is smaller than or equal to VDD, the substrate voltages of the first PMOS tube and the second PMOS tube are VDD, the second PMOS tube is closed, the grid voltage of the first PMOS tube is low, the first PMOS tube meets the first conduction condition, so that the first PMOS tube is conducted, the voltage PAD of the I/O port is pulled up to VDD, and the Hi-Z state is eliminated. When the Tolerant application condition or the Failsafe application condition occurs, that is, when the VDD is smaller than the PAD, the substrate voltages of the first PMOS tube and the second PMOS tube are PAD, the second PMOS tube is conducted, the grid voltage of the first PMOS tube is PAD, and the first conduction condition is not met. Meanwhile, as the substrate voltage of the first PMOS tube is PAD which is equal to the drain voltage of the first PMOS tube, PN junctions from the drain to the substrate cannot be conducted, and therefore the second conduction condition cannot be met. Therefore, through the implementation structure, the voltage pull-up effect of the voltage pull-up module can be ensured, and meanwhile, when the Tolerant application condition or the Failsafe application condition occurs, current is effectively prevented from flowing backwards from the I/O port to the power supply, so that the system is disordered. In addition, the substrate of the second PMOS tube is connected with the output end of the high-voltage output circuit, the second conduction condition of the second PMOS tube can be effectively prevented, and the condition that current flows backwards in the second PMOS tube is avoided.

Further, the control circuit includes: and the first switch is connected with the output end of the control circuit, the second connection end is grounded, and the control end is connected with a first control signal source.

In the above implementation structure, by controlling the first control signal source, when the PAD is less than or equal to VDD, the first switch is controlled to be turned on, so that the output end of the control circuit is grounded, and the first PMOS transistor is turned on; when the PAD is larger than the VDD, the first switch is controlled to be turned off, so that the second PMOS tube provides grid voltage for the grid electrode of the first PMOS tube, and the first PMOS tube is turned off. Therefore, the on-off control of the first PMOS tube can be easily realized through the configuration of the first switch, and the structure is simple and reliable.

Further, the control circuit further includes: the source electrode of the third PMOS tube is connected with the VDD, the grid electrode of the third PMOS tube is connected with the second control signal source, and the substrate is connected with the output end of the high-voltage output circuit; and the source electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, the drain electrode of the fourth PMOS tube is connected with the output end of the control circuit, the grid electrode of the fourth PMOS tube is connected with the third control signal source, and the substrate is connected with the output end of the high-voltage output circuit.

In the above implementation structure, through the arrangement of the third PMOS transistor and the fourth PMOS transistor, when the circuit works normally (that is, when the PAD is smaller than or equal to VDD), if the voltage pull-up module is expected to be turned off, the first switch can be turned off by the action of the first control signal source, the second control signal source and the third control signal source, and the third PMOS transistor and the fourth PMOS transistor are turned on, so that the gate voltage of the first PMOS transistor is VDD and is turned off, and the effect of turning off the voltage pull-up module when the circuit works normally is achieved. When the circuit works normally, if the voltage pull-up module is not expected to be closed, at least one of the third PMOS tube and the fourth PMOS tube is closed under the action of the second control signal source and the third control signal source, and the first switch is opened under the action of the first control signal source. Therefore, the control on whether the voltage pull-up module is closed or not can be realized when the circuit works normally through the mode.

Further, the first switch is a switch which is turned on when the voltage of the control terminal is at a high level; the second control signal source and the first control signal source are the same signal source;

the third control signal source includes: a fifth PMOS tube, wherein the source electrode is connected with the PAD, the grid electrode is connected with the VDD, the substrate is connected with the output end of the selected high voltage output circuit, and the drain electrode is connected with the grid electrode of the fourth PMOS tube; the first connecting end of the second switch is connected with the grid electrode of the fourth PMOS tube, the second connecting end of the second switch is grounded, the control end of the second switch is connected with the first control signal source, and the second switch is turned on when the voltage of the control end is high level.

In the above implementation structure, when the circuit works normally (that is, the PAD is less than or equal to VDD) and the voltage pull-up module is not turned off, the first control signal source may control the first switch and the second switch to be turned on and control the fourth PMOS transistor to be turned off by outputting a high level signal. When the circuit normally works, the voltage pull-up module is expected to be closed, the first control signal source can control the first switch and the second switch to be closed through outputting a low-level signal, and the third PMOS tube is conducted, at the moment, because the fifth PMOS tube still does not meet the conducting condition, the grid voltage of the fourth PMOS tube is in a floating state (namely, is consistent with the previous state), so that the first PMOS tube is conducted, the grid voltage of the first PMOS tube is VDD, and the first PMOS tube is closed. Thus, the circuit control can be realized by one control signal source, and the circuit design difficulty when the pull-up control circuit is applied to a chip or a chip system can be simplified.

Further, the voltage pull-up module further includes: the resistor is connected in series between the drain electrode of the first PMOS tube and the I/O port.

In the implementation structure, the resistor is connected in series, so that the current in the circuit can be reduced in the voltage pulling-up process, and the safety of the circuit is improved.

The embodiment of the application also provides an I/O bus, which comprises: the output end of the transmitter is connected with an I/O port of the I/O bus; the input end of the receiver is connected with an I/O port of the I/O bus; the drain electrode of the first PMOS tube of the pull-up control circuit is connected with the I/O port.

The I/O bus provided by the embodiment of the application can effectively prevent current from flowing backward from an I/O port to a power supply to cause system disorder when Tolerant application conditions or Failsafe application conditions occur while guaranteeing the voltage pull-up effect of the voltage pull-up module.

The embodiment of the application also provides a chip, which comprises the I/O bus.

The embodiment of the application also provides a chip system, which comprises: a master control chip and a slave chip; the master control chip is connected with the slave chip through the I/O bus.

The embodiment of the application also provides an electronic component, which comprises the chip or the chip system.

The embodiment of the application also provides electronic equipment, which comprises the chip, or comprises the chip system or comprises the electronic component.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments of the present application will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a related art I/O bus structure;

fig. 2 is a schematic diagram of a basic structure of a pull-up control circuit according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an alternative high voltage output circuit according to an embodiment of the present disclosure;

fig. 4 is a schematic structural diagram of a specific pull-up control circuit according to an embodiment of the present application;

fig. 5 is a schematic structural diagram of a pull-up control circuit according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a pull-up control circuit according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram of a basic structure of an I/O bus according to an embodiment of the present disclosure;

fig. 8 is a schematic structural diagram of a specific I/O bus according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.

In order to solve the problem that in the conventional pull-up resistor design, under the condition of Tolerant application (i.e. the chip has electricity, the I/O port has electricity, and the voltage PAD of the I/O port is higher than the voltage VDD of the power supply of the chip), or under the condition of Failsafe application (i.e. the chip is not electrified, the I/O port has electricity), current flows back to the power supply from the I/O port, so that the problem of system disorder is possibly caused. As can be seen from fig. 2 and 3, the pull-up control circuit provided in the embodiment of the present application includes: the high-voltage output circuit, the voltage pull-up module, the second PMOS tube m2 and the control circuit are selected.

The high voltage output circuit is used for selecting high voltage output from VDD (power supply voltage) and PAD (voltage of I/O port of bus). For convenience of description, the signal output from the selected high voltage output circuit is denoted NW, and the selected high voltage output circuit is denoted by NW default in fig. 2.

It should be understood that, in the embodiment of the present application, the high voltage output circuit may be implemented by using various circuits that may exist or may occur in the future, and the high voltage may be selected from the two voltages to output.

For example, as can be seen in fig. 3, the high voltage output circuit may include a sixth PMOS transistor m6 and a seventh PMOS transistor m7. The source electrode of the sixth PMOS tube m6 is connected with VDD, the grid electrode of the sixth PMOS tube m6 is connected with PAD, and the drain electrode of the sixth PMOS tube m6 is connected with the output end of the high-voltage output circuit; the source electrode of the seventh PMOS tube m7 is connected with the PAD, the grid electrode of the seventh PMOS tube m7 is connected with the VDD, and the drain electrode of the seventh PMOS tube m7 is connected with the output end of the high-voltage output circuit. Thus, a high output for PAD and VDD can be achieved.

In this embodiment of the present application, the voltage pull-up module includes a first PMOS transistor m1. The source electrode of the first PMOS tube m1 is connected with the VDD, the drain electrode of the first PMOS tube m1 is connected with the I/O port of the bus, and the substrate of the first PMOS tube m1 is connected with the output end of the high-voltage output circuit.

It should be understood that in this embodiment of the present application, the voltage pull-up module may further include a resistor, where the resistor may be connected in series between the drain of the first PMOS transistor and the I/O port of the bus, so as to reduce the current in the circuit during the voltage pull-up process, and improve the safety of the circuit.

It should also be understood that in the embodiment of the present application, the number of the first PMOS tubes m1 may be plural, and may be connected in series with each other. At this time, the connection relationship between the gate of each first PMOS transistor m1 and the second PMOS transistor m2 and the control circuit is the same as that in the case of only one first PMOS transistor m1 shown in fig. 2.

In this embodiment of the present application, as shown in fig. 2, a source electrode of the second PMOS transistor m2 is connected to a PAD, a gate electrode of the second PMOS transistor m2 is connected to a VDD, a substrate of the second PMOS transistor m2 is connected to an output end of the high-voltage output circuit, and a drain electrode of the second PMOS transistor m2 is connected to a gate electrode of the first PMOS transistor m1.

In this embodiment of the present application, as shown in fig. 2, the output end of the control circuit is connected to the gate of the first PMOS transistor m1, and is configured to output a low-level signal when the PAD is less than or equal to VDD, and not output a signal when the PAD is greater than VDD.

It should be understood that there are two forms of PMOS tube conduction:

1. and the conduction condition from the source electrode to the drain electrode of the PMOS tube. The conduction condition from the source electrode to the drain electrode of the PMOS tube is as follows: the source voltage V (S) is larger than the drain voltage V (D), namely V (S) > V (D), and the gate voltage V (G) -V (S) < Vthp, vthp is the threshold voltage of the PMOS tube;

2. the PMOS tube is conducted in a PN junction mode. In the process manufacturing, three ends of a source electrode, a substrate and a drain electrode of the PMOS tube are respectively P-type injection, N-type injection and P-type injection PNP-type PN junctions. So the drain to substrate is a P to N PN junction, which turns on if the drain voltage V (D) is greater than the substrate voltage V (B). At this time, if the substrate and the source of the PMOS transistor are connected together, a current from the drain to the source may be formed by conducting between the drain and the source, and if the substrate and the source of the PMOS transistor are not connected together, a leakage current may be formed between the drain and the gate.

In the pull-up control circuit shown in fig. 2 of the present application, when the bus is in normal operation, that is, when the PAD is less than or equal to VDD, the substrate voltages of the first PMOS transistor m1 and the second PMOS transistor m2 are VDD, the second PMOS transistor m2 is turned off, the gate voltage of the first PMOS transistor m1 is low, and the first PMOS transistor m1 meets the first conduction condition, so that the first PMOS transistor m1 is turned on, the voltage PAD of the I/O port is pulled up to VDD, and the Hi-Z state is eliminated.

When the Tolerant application condition or the Failsafe application condition occurs, that is, VDD is smaller than PAD, the substrate voltages of the first PMOS transistor m1 and the second PMOS transistor m2 are PAD, the second PMOS transistor m2 is turned on, and the gate voltage of the first PMOS transistor m1 is PAD, which does not satisfy the first conduction condition. Meanwhile, since the substrate voltage of the first PMOS transistor m1 is PAD equal to the drain voltage of the first PMOS transistor m1, the PN junction from the drain to the substrate cannot be turned on, and thus the second conduction condition cannot be satisfied. Therefore, the voltage pull-up effect of the voltage pull-up module is ensured, and when the Tolerant application condition or the Failsafe application condition occurs, current is effectively prevented from flowing backwards from the I/O port to the power supply, so that the system is disordered. In addition, in the embodiment of the application, the substrate of the second PMOS tube m2 is connected with the output end of the high-voltage output circuit, so that the second conduction condition of the second PMOS tube m2 can be effectively prevented, and the condition that the current flows backwards in the second PMOS tube m2 is avoided.

Alternatively, in the embodiment of the present application, as shown in fig. 4, the control circuit may include a first switch K1. The first connection end of the first switch K1 is connected with the output end of the control circuit, the second connection end of the first switch K1 is grounded, and the control end of the first switch K1 is connected with the first control signal source PU.

In this embodiment of the present application, the first control signal source PU may be configured, so that under the control of the first control signal source PU, the first switch K1 may be controlled to be turned on when the PAD is less than or equal to VDD, so that the output terminal of the control circuit is grounded, and the first PMOS transistor m1 is turned on; when PAD is larger than VDD, the first switch K1 is controlled to be turned off, so that the second PMOS tube provides grid voltage for the grid electrode of the first PMOS tube m1, and the first PMOS tube m1 is turned off.

In this embodiment of the present application, the first switch K1 may be a PMOS transistor, an NMOS transistor, a triode, an optical coupler, or the like, which is not limited in this embodiment of the present application.

In the embodiment of the application, it is considered that in practical application, there may be a need to actively turn off the voltage pull-up module. Therefore, in the embodiment of the present application, a circuit related to the normal use of the bus (that is, when the PAD is less than or equal to VDD) may be further designed in the control circuit, so as to control the first PMOS transistor m1 to be turned off.

As can be seen in fig. 5, the control circuit may further comprise: and the third PMOS tube m3 and the fourth PMOS tube m4. Wherein:

the source electrode of the third PMOS tube m3 is connected with the VDD, the grid electrode of the third PMOS tube m3 is connected with the second control signal source PU2, and the substrate of the third PMOS tube m3 is connected with the output end of the high-voltage selecting output circuit.

The source electrode of the fourth PMOS tube m4 is connected with the drain electrode of the third PMOS tube m3, the drain electrode of the fourth PMOS tube m4 is connected with the output end of the control circuit, the grid electrode of the fourth PMOS tube m4 is connected with the third control signal source PU3, and the substrate of the fourth PMOS tube m4 is connected with the output end of the high-voltage selecting output circuit.

In this way, when the circuit works normally (i.e. when PAD is smaller than or equal to VDD), if the voltage pull-up module is expected to be turned off, the first switch K1 can be turned off by the actions of the first control signal source PU, the second control signal source PU2 and the third control signal source PU3, the third PMOS tube m3 and the fourth PMOS tube m4 are turned on, so that the gate voltage of the first PMOS tube m1 is VDD and is turned off, and the voltage pull-up module is turned off when the circuit works normally. When the circuit works normally, if the voltage pull-up module is not expected to be turned off, at least one of the third PMOS tube m3 and the fourth PMOS tube m4 is turned off under the action of the second control signal source PU2 and the third control signal source PU3, and the first switch K1 is turned on under the action of the first control signal source PU. This realizes the control of whether the voltage pull-up module is turned off or not when the circuit works normally.

It should be understood that, in the embodiment of the present application, the first control signal source PU, the second control signal source PU2, and the third control signal source PU3 may be independent different signal sources, but the more signal sources that need to be connected to a circuit, the more difficult it is to design the whole chip that needs to be performed when the circuit is applied to the chip or the chip system. Therefore, in order to reduce the difficulty of circuit design when the pull-up control circuit is applied to a chip or a chip system, in an alternative implementation manner of this embodiment of the present application, as shown in fig. 6, the first switch K1 may be configured as a switch that is turned on when the control terminal voltage is at a high level, for example, an NMOS transistor shown in fig. 6, and setting the second control signal source and the first control signal source to be the same signal source PU, and setting the third control signal source PU3 includes:

the source electrode of the fifth PMOS tube m5 is connected with the PAD, the grid electrode of the fifth PMOS tube m5 is connected with the VDD, the substrate of the fifth PMOS tube m5 is connected with the output end of the high-voltage output circuit, and the drain electrode of the fifth PMOS tube m5 is connected with the grid electrode of the fourth PMOS tube m4.

And the first connecting end of the second switch K2 is connected with the grid electrode of the fourth PMOS tube m4, the second connecting end is grounded, and the control end is connected with the first control signal source PU. The second switch K2 is similar to the first switch K1, and is a switch that is turned on when the voltage of the control terminal is at a high level, for example, an NMOS transistor shown in fig. 6.

Thus, when the bus works normally (i.e. the PAD is less than or equal to VDD) and the voltage pull-up module is not turned off, the first control signal source PU can control the first switch K1 and the second switch K2 to be turned on and control the fourth PMOS transistor m4 to be turned off by outputting a high level signal. When the circuit normally works, the voltage pull-up module is expected to be turned off, the first control signal source PU can control the first switch K1 and the second switch K2 to be turned off through outputting a low-level signal, and the third PMOS tube m3 is turned on, at this time, because the fifth PMOS tube m5 still does not meet the conduction condition, the grid voltage of the fourth PMOS tube m4 is in a floating state (i.e. keeps consistent with the previous state), so that the grid voltage of the first PMOS tube is turned on, and the grid voltage of the first PMOS tube is VDD, so that the first PMOS tube is turned off. Thus, the circuit control can be realized by one control signal source, and the circuit design difficulty when the pull-up control circuit is applied to a chip or a chip system can be simplified.

Based on the same inventive concept, the embodiments of the present application further provide an I/O bus, for example, as shown in fig. 7, including: a transmitter TX, a receiver RX, an I/O port and a pull-up control circuit of any of the structures described above. Wherein:

the output end of the transmitter TX is connected with an I/O port of the I/O bus to realize the data input function of the I/O bus. The input end of the receiver RX is connected with the I/O port of the I/O bus, so as to realize the data output function of the I/O bus. The drain electrode of the first PMOS tube m1 of the pull-up control circuit is connected with the I/O port, so that the PAD voltage at the I/O port is pulled up.

In order to facilitate understanding of the solution of the embodiment of the present application, the circuit principle of the embodiment of the present application will be described based on the structure shown in fig. 8 as follows:

when the bus works normally and the PAD is smaller than or equal to VDD, nw=vdd, and the second PMOS transistor and the fifth PMOS transistor m5 are turned off.

Assuming that the voltage pull-up function needs to be started, the signal pu=vdd output by the first control signal source PU, at this time, the third PMOS transistor m3 is turned off, the first switch K1 is turned on, the signal pon=0 output by the output end of the control circuit, the first PMOS transistor is turned on, and the voltage pull-up function is started normally.

Assuming that the voltage pull-up function does not need to be started, the signal pu=0 output by the first control signal source PU is turned off at this time, the third PMOS transistor m3 is turned on, the second switch K2 is turned off, and since the second switch K2 and the fifth PMOS transistor m5 are both turned off, the gate voltage TG of the fourth PMOS transistor m4 is suspended, following the previous voltage situation, during normal use, the gate voltage TG of the fourth PMOS transistor m4 is 0, so that the gate voltage of the fourth PMOS transistor m4 is also approximately equal to 0 when TG is suspended, and the fourth PMOS transistor m4 is turned on, so that the pull=vdd is achieved, the first PMOS transistor is turned off, and the voltage pull-up function is turned off.

When Tolerant application occurs, PAD is greater than VDD, nw=pad, and the second PMOS transistor and the fifth PMOS transistor m5 are turned on. At this time, the signal pu=0 output by the first control signal PU, the first switch K1 is turned off, the fourth PMOS transistor m4 is turned off, the gate voltage of the first PMOS transistor is PAD, and the first PMOS transistor is turned off. No current path from PAD to VDD is available and no reverse current flow is possible.

When the Failsafe application condition occurs, vdd=0, PAD is greater than 0, nw=pad, and the second PMOS transistor and the fifth PMOS transistor m5 are turned on. At this time, the signal pu=0 output by the first control signal PU, the first switch K1 is turned off, the fourth PMOS transistor m4 is turned off, the gate voltage of the first PMOS transistor is PAD, and the first PMOS transistor is turned off. No current path from PAD to VDD is available and no reverse current flow is possible.

Obviously, by the scheme provided by the embodiment of the application, when the Tolerant application condition or the Failsafe application condition occurs, the current is effectively prevented from flowing backwards from the I/O port to the power supply, and the system disorder is caused while the voltage pull-up effect of the voltage pull-up module is ensured. Meanwhile, according to the scheme, during normal operation, no extra leakage path is generated under the application conditions of Tolerant and Failsafe.

Based on the same inventive concept, the embodiment of the application also provides a chip, wherein the chip comprises the I/O bus.

Based on the same inventive concept, the embodiments of the present application further provide a chip system, including: a master chip and a slave chip. The master control chip is connected with the slave chip through the I/O bus.

It should be appreciated that in the embodiments of the present application, the chips (including the master chip and the slave chip) may be, but are not limited to, computing chips (such as GPU (Graphics Processing Unit, graphics processor), CPU (Central Processing Unit ), MCU (Microcontroller Unit, microcontroller), AI (artificial intelligence), etc.), memory chips (such as DRAM (Dynamic Random Access Memory, dynamic random access Memory), SDRAM (Synchronous Dynamic Random Access Memory ), ROM (Read-Only Memory), NAND (computer flash Memory device), etc.), communication chips (such as bluetooth chip, wiFi chip, HDMI (High Definition Multimedia Interface, high-definition multimedia interface) chip, etc.), sensing chips (such as MEMS (Microelectro Mechanical Systems, microelectromechanical system) sensor chip, etc.).

It should also be understood that in the embodiments of the present application, the on-chip I/O bus may be used for connection of chips to other components, in addition to connection between chips.

Based on the same inventive concept, the embodiment of the application also provides an electronic component, which comprises the chip or the chip system.

It should be understood that in the embodiments of the present application, the electronic component may be, but is not limited to, a communication module, a computing module, a storage module, etc. that are manufactured for independent production.

Based on the same inventive concept, the embodiment of the application also provides electronic equipment, which comprises the chip, or the chip system or the electronic component.

In the embodiment of the application, the electronic device may be, but is not limited to, an electronic device having a chip setting requirement, such as a terminal, a server, a router, a memory, and the like.

The device embodiments described above are merely illustrative. The connections shown or discussed with respect to each other may be made through interface pads or may be electrical.

In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity from another entity without necessarily requiring or implying any actual such relationship or order between such entities.

Herein, a plurality refers to two or more.

The foregoing is merely exemplary embodiments of the present application and is not intended to limit the scope of the present application, and various modifications and variations may be suggested to one skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims (10)

1. A pull-up control circuit, comprising:

a high-voltage selecting output circuit for selecting a high-voltage output from the power supply voltage VDD and the voltage PAD of the input/output I/O port of the bus;

a voltage pull-up module, the voltage pull-up module comprising: the source electrode of the first PMOS tube is connected with the VDD, the drain electrode of the first PMOS tube is connected with the I/O port, and the substrate is connected with the output end of the high-voltage output circuit;

the source electrode of the second PMOS tube is connected with the PAD, the grid electrode of the second PMOS tube is connected with the VDD, the substrate is connected with the output end of the selected high-voltage output circuit, and the drain electrode of the second PMOS tube is connected with the grid electrode of the first PMOS tube;

and the output end of the control circuit is connected with the grid electrode of the first PMOS tube and is used for outputting a low-level signal when the PAD is smaller than or equal to the VDD and not outputting a signal when the PAD is larger than the VDD.

2. The pull-up control circuit of claim 1, wherein the control circuit comprises:

and the first switch is connected with the output end of the control circuit, the second connection end is grounded, and the control end is connected with a first control signal source.

3. The pull-up control circuit of claim 2, wherein the first switch is an NMOS transistor, the control circuit further comprising:

the source electrode of the third PMOS tube is connected with the VDD, the grid electrode of the third PMOS tube is connected with the second control signal source, and the substrate is connected with the output end of the high-voltage output circuit;

and the source electrode of the fourth PMOS tube is connected with the drain electrode of the third PMOS tube, the drain electrode of the fourth PMOS tube is connected with the output end of the control circuit, the grid electrode of the fourth PMOS tube is connected with the third control signal source, and the substrate is connected with the output end of the high-voltage output circuit.

4. The pull-up control circuit of claim 3, wherein the first switch is a switch that is turned on when the control terminal voltage is high; the second control signal source and the first control signal source are the same signal source;

the third control signal source includes:

a fifth PMOS tube, wherein the source electrode is connected with the PAD, the grid electrode is connected with the VDD, the substrate is connected with the output end of the selected high voltage output circuit, and the drain electrode is connected with the grid electrode of the fourth PMOS tube;

the first connecting end of the second switch is connected with the grid electrode of the fourth PMOS tube, the second connecting end of the second switch is grounded, and the control end of the second switch is connected with the first control signal source; the second switch is a switch which is turned on when the voltage of the control terminal is at a high level.

5. A pull-up control circuit as claimed in any one of claims 1 to 3, wherein the voltage pull-up module further comprises:

the resistor is connected in series between the drain electrode of the first PMOS tube and the I/O port.

6. An I/O bus, comprising:

the output end of the transmitter is connected with an I/O port of the I/O bus;

the input end of the receiver is connected with an I/O port of the I/O bus;

the pull-up control circuit of any one of claims 1-5, wherein a drain of the first PMOS transistor of the pull-up control circuit is connected to the I/O port.

7. A chip comprising the I/O bus of claim 6.

8. A chip system, comprising: a master control chip and a slave chip; the master chip is connected to the slave chip through the I/O bus as claimed in claim 6.

9. An electronic component comprising the chip of claim 7 or comprising the chip system of claim 8.

10. An electronic device comprising a chip as claimed in claim 7, or comprising a chip system as claimed in claim 8, or comprising an electronic component as claimed in claim 9.

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