CN219286394U

CN219286394U - Semiconductor device and semiconductor chip assembly

Info

Publication number: CN219286394U
Application number: CN202222898259.5U
Authority: CN
Inventors: 张锋; 高超; 周继峰
Original assignee: Littelfuse Semiconductor (Wuxi) Co Ltd
Current assignee: Littelfuse Semiconductor (Wuxi) Co Ltd
Priority date: 2022-11-01
Filing date: 2022-11-01
Publication date: 2023-06-30
Anticipated expiration: 2032-11-01

Abstract

Semiconductor devices and semiconductor chip assemblies are disclosed. The semiconductor device includes: a dielectric housing; a semiconductor chip disposed within the dielectric housing, the semiconductor chip having first and second metal electrodes disposed on opposite surfaces thereof, at least one of the first and second metal electrodes having a notch formed in an edge thereof; a first lead frame having a first end extending out of the dielectric housing and having a second end terminating in a die pad on which the semiconductor chip is mounted, wherein the first metal electrode is electrically connected to the die pad; a second leadframe having a first end extending out of the dielectric housing and having a second end disposed adjacent the semiconductor die; and a clip having a first end connected to the second end of the lead frame and a second end extending over the semiconductor chip and electrically connected to the second metal electrode.

Description

Semiconductor device and semiconductor chip assembly

Technical Field

The present disclosure relates generally to the field of semiconductor devices, and more particularly to a chip assembly for a Transient Voltage Suppression (TVS) device.

Background

Packaging integrated circuits is typically the final stage of semiconductor device fabrication. During packaging, a semiconductor chip representing a core of a semiconductor device is connected to die pads (pads) and clips (clips) configured to provide electrical connections between the semiconductor chip and circuitry to which the semiconductor device is connected. Typically, the die pads and clips are soldered to metal electrodes disposed on opposite sides of the semiconductor chip. The assembly is then encapsulated in a dielectric housing (e.g., plastic or epoxy) to protect the encapsulated assembly from physical damage and corrosion.

In some cases, when die pads and clips are soldered to metal electrodes of a semiconductor chip, excess solder may flow from between the metal electrodes and die pads and clips to the edges of the semiconductor chip. This may create opportunities for electrical shorts to occur around one or more edges of the semiconductor chip (i.e., shorts may occur between excess solder regions near opposite sides of the semiconductor chip). In recent years, as power requirements of semiconductor devices have increased and package sizes have decreased, the risk of solder overflow and the resultant electrical shorts has increased.

In view of these and other factors, current improvements may be useful.

Disclosure of Invention

This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the detailed description. This summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

A semiconductor device according to an exemplary embodiment of the present disclosure may include a dielectric housing, a semiconductor chip disposed within the dielectric housing, the semiconductor chip having first and second metal electrodes disposed on opposite surfaces thereof, at least one of the first and second metal electrodes having a notch formed at an edge thereof, a first lead frame having a first end extending out of the dielectric housing and having a second end terminating in a die pad on which the semiconductor chip is mounted, wherein the first metal electrode is electrically connected to the die pad, a second lead frame having a first end extending out of the dielectric housing and having a second end disposed adjacent to the semiconductor chip, and a clip having a first end connected to the second end of the lead frame and a second end extending over the semiconductor chip and electrically connected to the second metal electrode.

A semiconductor device according to another exemplary embodiment of the present disclosure may include a semiconductor chip disposed within a dielectric housing, the semiconductor chip having first and second metal electrodes disposed on opposite surfaces thereof, each of the first and second metal electrodes having a notch formed on opposite edges thereof, a first lead frame having a first end extending out of the dielectric housing and having a second end terminating in a die pad on which the semiconductor chip is mounted, wherein the first metal electrode is electrically connected to the die pad by a first amount of solder, some of the first amount of solder is disposed within the notch in the opposite edges of the first metal electrode, a second lead frame having a first end extending out of the first end of the dielectric housing and having a second end disposed adjacent to the semiconductor chip, and a clip having a first end connected to the second end of the lead frame and a second end extending over the semiconductor chip and electrically connected to the second metal electrode by a second amount of solder, some of the second amount of solder being disposed within the notch in the opposite edges of the second metal electrode.

The semiconductor chip assembly according to an exemplary embodiment of the present disclosure may include a semiconductor chip, a first metal electrode disposed on a first side of the semiconductor chip, and a second metal electrode disposed on a second side of the semiconductor chip opposite to the first side, wherein at least one of the first metal electrode and the second metal electrode has a notch formed in an edge thereof.

Drawings

Fig. 1A is a perspective view illustrating a semiconductor device according to an exemplary embodiment of the present disclosure;

fig. 1B is a cross-sectional view illustrating the semiconductor device of fig. 1A;

fig. 2 is a perspective view showing a lead frame of the semiconductor device of fig. 1A;

fig. 3 is a perspective view illustrating a clip of the semiconductor device of fig. 1A;

fig. 4 is a top view illustrating a chip assembly of the semiconductor device of fig. 1A;

fig. 5 is a top view illustrating an alternative embodiment of a chip assembly of the semiconductor device of fig. 1A.

The figures are not necessarily drawn to scale. The drawings are merely representations, not intended to portray specific parameters of the disclosure. The drawings are intended to depict example embodiments of the disclosure, and therefore should not be considered as limiting the scope. In the drawings, like numbering represents like elements.

Moreover, some elements in some of the figures may be omitted or not to scale for clarity of illustration. The cross-sectional view may be in the form of a "slice" or "near" cross-sectional view, with certain background lines visible in the "true" cross-sectional view omitted for clarity of illustration. Moreover, some reference numerals may be omitted from some of the figures for clarity.

Detailed Description

Embodiments of a semiconductor device according to the present disclosure will now be described more fully with reference to the accompanying drawings, in which preferred embodiments of the disclosure are shown. However, the semiconductor device of the present disclosure may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the semiconductor device to those skilled in the art. In the drawings, like numerals refer to like elements unless otherwise specified.

Referring to fig. 1A and 1B, an isometric view and a cross-sectional view, respectively, are provided showing a semiconductor device 10 (hereinafter "device 10") according to an exemplary embodiment of the present disclosure. For convenience and clarity, terms such as "top," "bottom," "upward," "downward," "upper," "lower," "above," and "below" may be used herein to describe the relative positions and orientations of the various components of device 10, all with respect to the geometry and orientation of device 10 shown in fig. 1A and 1B. The terminology will include the words specifically mentioned, derivatives thereof, and words of similar import.

The device 10 may generally include a semiconductor chip 12 (hereinafter "chip 12") disposed within a package 14. In various embodiments, the die 12 may be a Transient Voltage Suppression (TVS) device/die and may have first and second metal electrodes 16 and 18 disposed on opposite bottom and top surfaces 15 and 17 thereof, respectively. The chip 12 and the first and second metal electrodes 16 and 18 may be collectively referred to as a "chip assembly 19" hereinafter. The package 14 of the device 10 may include a first leadframe 20, a second leadframe 22, a clip 24, and a housing 26. The housing 26 may be formed of a dielectric material (e.g., plastic, epoxy, etc.) and may encapsulate the chip assembly 19, the clip 24, and a portion of the first and second lead frames 20, 22 for protecting the packaged assembly from physical damage and corrosion.

The first and second lead frames 20, 22 and the clip 24 may be formed of conductive materials including, but not limited to, copper alloys, silver, and the like. The first and second lead frames 20, 22 may have respective first ends 28, 30 extending out of the housing 26 for connecting the device 10 into a circuit. The second end 32 of the first leadframe 20 may terminate in a die pad 34 upon which the chip assembly 19 may be mounted and electrically connected thereto, such as with solder (as described further below). The clip 24 may be a generally L-shaped member with a first end 42 connected to a second end 44 of the second leadframe 22. In various embodiments, the first end 42 of the clip 24 can have first and second prongs 46a, 46B extending therefrom, the first and second prongs 46a, 46B fitting into complementary first and second notches 48a, 48B formed in opposite edges of the second end 44 of the second leadframe 22 (see fig. 2 and 3), with a terminal edge (terminal edge) of the first end 42 of the clip 24 disposed on a top surface of the second end 44 of the second leadframe 22 (as shown in fig. 1B). The present disclosure is not limited in this regard. The second end 46 of the clip 24 may extend over the chip assembly 19 and may be electrically connected to the second metal electrode 18, such as by solder (as described further below).

Referring to fig. 4, a top view is provided showing the chip assembly 19 (including the top surface 17 of the chip 12 and the second metal electrode 18). The bottom surface 15 of the chip 12 and the first metal electrode 16 are not shown in fig. 4, and they are substantially identical to the top surface 17 of the chip 12 and the second metal electrode 18. Accordingly, it should be appreciated that the following description of the top surface 17 of the chip 12 and the second metal electrode 18 should also apply to the bottom surface 15 of the chip 12 and the first metal electrode 16.

As shown in fig. 4, the second metal electrode 18 may have first and

second notches

50 and 52 formed in opposite first and

second edges

54 and 56, respectively. The first and

second notches

50, 52 may define a boundary of the second metal electrode 18 that is spaced farther from respective adjacent first and

second edges

58, 60 of the chip 12 than the respective first and

second edges

54, 56 of the second metal electrode 18. In various embodiments, the first and

second notches

50, 52 may be recessed from the respective first and

second edges

54, 56 of the second metal electrode 18 to a maximum depth d, where d is in the range of 0.0762 millimeters to 0.1016 millimeters. The present disclosure is not limited in this regard. The first and

second notches

50, 52 may include a plurality of serrations (serials) or scallops (scales) as shown, but this is not critical. The first slot 50 and the second slot 52 may include a variety of alternative shapes and configurations without departing from the scope of the present disclosure. For example, referring to fig. 5, an alternative embodiment of the chip assembly 19 is shown in which the first and

second notches

50, 52 are defined by a single recess of uniform depth formed in the first and

second edges

54, 56, respectively, of the second metal electrode 18. Further, while the second metal electrode 18 is depicted as forming a total of two slots therein, one in each of the first edge 54 and the second edge 56, alternative embodiments of the present disclosure are contemplated in which the second metal electrode 18 forms slots in three or four edges thereof, or only one in one edge thereof. The present disclosure is not limited in this regard.

When the device 10 is assembled as shown in fig. 1B, a quantity of solder (not shown) may be used to electrically connect the second end 46 of the clip 24 to the second metal electrode 18. During soldering, referring also to fig. 4, excess solder disposed between the second end 46 of the clip 24 and the second metal electrode 18 may flow into the first and

second notches

50, 52 in the first and

second edges

54, 56 of the second metal electrode 18 and may be collected therein, thereby preventing solder from flowing toward the first and

second edges

58, 60 of the chip 12. Also, when the first metal electrode 16 is soldered to the die pad 34, excess solder disposed between the first metal electrode 16 and the die pad 34 may flow into and may be collected in first and second notches in respective first and second edges of the second metal electrode 16. Thus, since excess solder is largely or entirely prevented from flowing from the edges of the first and second metal electrodes 16, 18 to the first and

second edges

58, 60 of the chip 12, the risk of electrical shorting around the first and

second edges

58, 60 of the chip 12 is significantly reduced relative to conventional semiconductor device configurations in which the metal electrodes of the chip assembly do not have recessed edges and thus allow excess solder to flow closer to the edges of the semiconductor chip.

As used herein, an element or step recited in the singular and proceeded with the word "a" or "an" should be understood as not excluding plural elements or steps, unless such exclusion is explicitly recited. Furthermore, references to "one embodiment" of the present disclosure are not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

Although the present disclosure has reference to certain embodiments, many modifications, alterations and changes to the described embodiments are possible without departing from the breadth and scope of the present disclosure as defined in the appended claims. Thus, the present disclosure is not limited to the embodiments described, but has the full scope defined by the language of the following claims and equivalents thereof.

Claims

1. A semiconductor device, comprising:

a dielectric housing;

a semiconductor chip disposed within the dielectric housing, the semiconductor chip having first and second metal electrodes disposed on opposite surfaces thereof, at least one of the first and second metal electrodes having a notch formed in an edge thereof;

a first lead frame having a first end extending out of the dielectric housing and having a second end terminating at a die pad on which the semiconductor chip is mounted, wherein the first metal electrode is electrically connected to the die pad;

a second leadframe having a first end extending out of the dielectric housing and having a second end disposed adjacent the semiconductor die; and

a clip having a first end connected to the second end of the leadframe and a second end extending over the semiconductor chip and electrically connected to the second metal electrode.

2. The semiconductor device of claim 1, wherein a depth of the notch is in a range of 0.0762 mm to 0.1016 mm.

3. The semiconductor device of claim 1, wherein the first metal electrode has a first notch and a second notch formed in opposite edges thereof.

4. The semiconductor device of claim 1, wherein the second metal electrode has first and second notches formed in opposite edges thereof.

5. The semiconductor device of claim 1, wherein the first metal electrode is electrically connected to the die pad by an amount of solder, wherein some of the amount of solder is disposed within the notch.

6. The semiconductor device of claim 1, wherein the second metal electrode is electrically connected to the second end of the clip by an amount of solder, wherein some of the amount of solder is disposed within the notch.

7. The semiconductor device of claim 1, wherein the notch comprises a plurality of serrations.

8. The semiconductor device of claim 1, wherein the clip is L-shaped.

9. The semiconductor device of claim 1, wherein the first end of the clip includes first and second tines that fit into complementary first and second notches formed in opposite edges of the second end of the second leadframe.

10. A semiconductor device, comprising:

a dielectric housing;

a semiconductor chip disposed within the dielectric housing, the semiconductor chip having first and second metal electrodes disposed on opposite surfaces thereof, each of the first and second metal electrodes having notches formed on opposite edges thereof;

a first lead frame having a first end extending out of the dielectric housing and having a second end terminating in a die pad on which the semiconductor chip is mounted, wherein the first metal electrode is electrically connected to the die pad by a first amount of solder, some of the solder of the first amount being disposed within notches in opposite edges of the first metal electrode;

a clip having a first end connected to the second end of the leadframe and a second end extending over the semiconductor chip and electrically connected to the second metal electrode by a second amount of solder, some of the solder of the second amount being disposed within notches in opposite edges of the second metal electrode.

11. The semiconductor device of claim 10, wherein a depth of the notch in the opposing edges of the first and second metal electrodes is in a range of 0.0762 mm to 0.1016 mm.

12. The semiconductor device of claim 10, wherein at least one of the notches in opposite edges of the first metal electrode and the second metal electrode comprises a plurality of serrations.

13. The semiconductor device of claim 10, wherein the clip is L-shaped.

14. The semiconductor device of claim 10, wherein the first end of the clip includes first and second tines that fit into complementary first and second notches formed in opposite edges of the second end of the second leadframe.

15. A semiconductor chip assembly, comprising:

a semiconductor chip;

a first metal electrode disposed on a first side of the semiconductor chip;

a second metal electrode disposed on a second side of the semiconductor chip opposite to the first side,

wherein at least one of the first metal electrode and the second metal electrode has a notch formed in an edge thereof.

16. The semiconductor chip assembly of claim 15, wherein the notch has a depth in the range of 0.0762 mm to 0.1016 mm.

17. The semiconductor chip assembly of claim 15, wherein the notch comprises a plurality of serrations.

18. The semiconductor chip assembly of claim 15, wherein each of the first and second metal electrodes has notches formed in opposite edges thereof.