CN219286010U

CN219286010U - Pixel circuit, micro light emitting diode chip, driving chip and light emitting chip

Info

Publication number: CN219286010U
Application number: CN202222959112.2U
Authority: CN
Inventors: 赵影; 籍亚男
Original assignee: Suzhou Aoshi Micro Technology Co ltd
Current assignee: Suzhou Aoshi Micro Technology Co ltd
Priority date: 2022-11-07
Filing date: 2022-11-07
Publication date: 2023-06-30
Anticipated expiration: 2032-11-07

Abstract

The application relates to a pixel circuit, little emitting diode chip, driver chip and light emitting chip, wherein, pixel circuit includes: the pixel storage circuit comprises a plurality of storage layers which are stacked, wherein each storage layer is provided with at least one storage unit, and the storage units in each storage layer are connected to the same data output end; the pixel driving circuit comprises a switching transistor unit and a light emitting device, wherein a grid electrode of the switching transistor unit is connected with the data output end, one of a source electrode and a drain electrode of the switching transistor unit is connected with a current source, and the other is connected with the light emitting device. The pixel density of the unit can be effectively improved.

Description

Pixel circuit, micro light emitting diode chip, driving chip and light emitting chip

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a pixel circuit, a micro light emitting diode chip, a driving chip, and a light emitting chip.

Background

Conventional micro Light Emitting Diodes (LEDs) typically feed n bit data into the pixel driving circuit one by one. After each subframe is displayed, a period of time is required to wait for the display of the next subframe. Therefore, the display time in each subframe has a small duty ratio, and the actual display time is shorter, thereby affecting the display brightness.

In the related art, the pixel storage circuit based on a Dynamic Random Access Memory (DRAM) and a Static Random Access Memory (SRAM) architecture stores n bits of data of each pixel, so that there is basically no waiting time between n subframes of each frame during display, and the display duty ratio and the display brightness are greatly improved.

However, the arrangement of the pixel storage circuit reduces the pixel density.

Disclosure of Invention

In view of the above, it is necessary to provide a pixel circuit, a micro light emitting diode chip, a driving chip, and a light emitting chip capable of improving the density of unit pixels.

A pixel circuit, comprising:

the pixel storage circuit comprises a plurality of storage layers which are stacked, wherein each storage layer is provided with at least one storage unit, and the storage units in each storage layer are connected to the same data output end;

the pixel driving circuit comprises a switching transistor unit and a light emitting device, wherein a grid electrode of the switching transistor unit is connected with the data output end, one of a source electrode and a drain electrode of the switching transistor unit is connected with a current source, and the other is connected with the light emitting device.

In one embodiment, the memory cell includes:

the memory cell includes a first transistor cell, a second transistor cell and a switching cell,

the grid electrode of the first transistor unit is connected with a data writing-in gate end, one of the source electrode and the drain electrode of the first transistor unit is connected with the data writing-in end, the other is connected with the grid electrode of the second transistor unit, a data storage node is formed between the grid electrode of the second transistor unit and the grid electrode of the second transistor unit,

one of a source electrode and a drain electrode of the second transistor unit is connected with a data reading and selecting end, the other is connected with the data output end through the switch unit, and the conductivity type of the second transistor unit is N type.

In one embodiment, the switching unit includes a third transistor unit, one of a source and a drain of the third transistor unit is connected to the second transistor unit, and the other is connected to the data output terminal.

In one embodiment, the gate of the third transistor unit is connected to the data read gate of the memory cell in which it is located.

In one embodiment, the first transistor unit, the second transistor unit, and the third transistor unit each include IGZO thin film transistors.

In one embodiment, the memory cells in each of the memory layers are connected to the same data write strobe.

A micro light emitting diode chip provided with a plurality of the pixel circuits described in any one of the above, and a plurality of the pixel circuits are arranged in an array.

In one embodiment, the micro light emitting diode chip includes:

a driving chip;

a light emitting chip bonded to the light emitting chip;

each storage layer of the pixel storage circuit is positioned on the driving chip and/or the light emitting chip.

A driver wafer, comprising:

a first substrate;

a switching transistor unit on the first substrate;

a pixel storage circuit according to any one of the preceding claims, wherein each storage layer of the pixel storage circuit is stacked in sequence on the switching transistor unit.

A light emitting die, comprising:

a second substrate;

a light emitting device on the second substrate;

a pixel storage circuit according to any one of the preceding claims, wherein each of the storage layers of the pixel storage circuit is laminated in sequence on the light emitting device.

According to the pixel circuit, the micro light emitting diode chip, the driving chip and the light emitting chip, the pixel storage circuit comprises a plurality of storage layers which are stacked, and each storage unit is respectively arranged on each storage layer, so that the occupied area of the pixel storage circuit can be effectively reduced. At this time, the area of the whole pixel circuit is effectively reduced at the same time, so that the unit pixel density can be effectively improved.

Drawings

In order to more clearly illustrate the technical solutions of embodiments or conventional techniques of the present application, the drawings required for the descriptions of the embodiments or conventional techniques will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person of ordinary skill in the art.

FIG. 1 is a schematic circuit diagram of a pixel circuit according to an embodiment of the present disclosure;

FIG. 2 is a schematic circuit diagram of a memory cell according to an embodiment of the present application;

fig. 3 is a schematic diagram of a pixel circuit arrangement of a micro light emitting diode chip according to an embodiment of the present application;

fig. 4 to 6 are schematic structural diagrams of a micro light emitting diode chip in a manufacturing process according to an embodiment;

fig. 7 to 9 are schematic structural diagrams of a micro light emitting diode chip in another embodiment in the process of manufacturing the micro light emitting diode chip.

Detailed Description

In order to facilitate an understanding of the present application, a more complete description of the present application will now be provided with reference to the relevant figures. Preferred embodiments of the present application are shown in the drawings. This application may, however, be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the description of the application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.

In the drawings, the size of layers and regions may be exaggerated for clarity of illustration. It will be understood that when a layer or element is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present. In addition, like reference numerals refer to like elements throughout.

In the following embodiments, when a layer, region or element is "connected," it can be construed that the layer, region or element is not only directly connected but also connected through other constituent elements interposed therebetween. For example, when a layer, region, element, etc. is described as being connected or electrically connected, the layer, region, element, etc. can be connected or electrically connected not only directly or electrically connected but also through another layer, region, element, etc. interposed therebetween.

Hereinafter, although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are used only to distinguish one component from another. It will also be understood that the use of the expression "a" or "an" includes the plural unless the singular is in a context clearly different.

When a statement such as "… …" is located after a column of elements, the entire column of elements is modified instead of modifying individual elements in the column. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," and/or the like, specify the presence of stated features, integers, steps, operations, elements, components, or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups thereof.

In one embodiment, referring to fig. 1, a pixel circuit 10 is provided, and includes a pixel storage circuit 100 and a pixel driving circuit 200.

The pixel storage circuit 100 may store nbit data of n subframes, and output a signal to the pixel driving circuit 200 through one data output terminal RBL, n being a positive integer greater than 1. The nbit data are all output through the same data output end RBL.

Specifically, the pixel memory circuit 100 includes a plurality of memory layers 100a stacked, and each memory layer 100a is provided with at least one memory cell 110. The number of layers of the memory layer 100a may be determined according to the number of bits of the memory data, the pixel size, and the like. The number of the memory units 110 on each memory layer 100a may be the same or different, and may be specifically set according to actual requirements.

As an example, referring to fig. 1, when 6bit data is stored, a 3-layer memory layer 100a may be provided, in which two memory cells are arranged per layer to store 2bit data.

Each storage unit 110 located on each storage layer 100a is used to store data of one subframe. When one pixel includes n subframes, the pixel storage circuit 100 may correspondingly include n storage units to store the nbit data of the n subframes. n memory cells may be distributed in each memory layer 100a.

The pixel driving circuit 200 includes a switching transistor unit 210 and a light emitting device 220.

The gate of the switching transistor unit 210 is connected to the data output terminal RBL of the pixel memory circuit 100. Meanwhile, one of the source and the drain of the switching transistor unit 210 is connected to a current source, and the other is connected to the light emitting device 220.

When a sub-frame of the light emitting device 220 is displayed, data on the memory cell 110 corresponding to the sub-frame may be output through the data output terminal RBL.

When the data output terminal RBL outputs data of "1", the switching transistor unit 210 is turned on. At this time, the light emitting device 220 receives a current from the current source and emits light. When the data output terminal RBL outputs data of "0", the switching transistor unit 210 is turned off. At this time, the light emitting device 220 does not emit light. When the display of all subframes of the light emitting device 220 is completed, one pixel display is completed.

In the present embodiment, by providing the pixel memory circuit 100 including a plurality of memory layers 100a stacked, each memory cell 110 is provided on each memory layer 100a, so that the area occupied by the pixel memory circuit 100 can be effectively reduced. At this time, the area of the entire pixel circuit 10 is effectively reduced at the same time, so that the unit pixel density can be effectively improved.

In one embodiment, referring to fig. 2, the memory cell 110 includes a first transistor cell 111, a second transistor cell 112, and a switch cell 113.

The gate of the first transistor unit 111 is connected to the data writing gate WWL, one of the source and the drain of the first transistor unit 111 is connected to the data writing terminal WBL, the other is connected to the gate of the second transistor unit 112, and a data storage node SN is formed between the other and the gate of the second transistor unit 112.

At this time, a data storage node SN is formed between the drain (or source) of the first transistor unit 111 and the gate of the second transistor 112. The first transistor unit 111 can be used for writing data to the pixel memory circuit 100.

The data clearing phase may be performed first before the data writing to the pixel memory circuit 100. And in the data clearing stage, the RBL potential of the data output end is cleared to a low potential.

Specifically, referring to fig. 1, the pixel driving circuit 200 may further include a clear transistor unit 230. The gate of the clear transistor unit 230 is connected to the clear signal terminal prst. Meanwhile, one of the source and the drain of the clear transistor unit 230 is connected to the data output terminal RBL, and the other is grounded.

A clear signal (e.g., a high signal) may be provided to the clear signal terminal prst before writing data to the pixel memory circuit 100, thereby turning on the clear transistor unit 230. At this time, the data output terminal RBL is grounded, and the potential is cleared.

In the data writing stage, the data writing strobe terminal WWL may be set to an on level (e.g., a high level), so that the first transistor unit 111 is turned on, and data is written to the data storage node SN by the data writing terminal WBL. Each memory cell can write related data at the same time.

After the data write phase, the data write pass WWL may be placed at an off level (e.g., low).

Here, it is understood that the conductivity type of the first transistor unit 111 may be N-type or P-type. This is not limiting here. When the conductivity type of the first transistor unit 111 is N-type, the turn-on level of the data write gate WWL is high and the turn-off level is low.

One of the source and the drain of the second transistor unit 112 is connected to the data read gate terminal RWL, and the other is connected to the data output terminal RBL through the switching unit 113. The second transistor unit 112 has an N-type conductivity.

In the data output stage, the data write strobe terminal WWL is held at an off potential. Meanwhile, the data read gate ends RWL (e.g., RWL1 to RWL 6) of the respective memory cells are sequentially gated. When the data read gate RWL of one memory cell 110 is turned on, the data read gate RWL thereof is set high and the switching unit 113 is turned on, while the data read gate RWL of the other memory cells is set low and the switching unit 113 is turned off. For example, when the data output terminal RBL1 of the first memory cell is turned on, RBL1 is set high and the switching unit 113 is turned on, and the data output terminals RBL2 to RBL6 of the other memory cells are set low and the switching unit 113 is turned off.

When one memory cell 110 is gated, if the data storage node SN of that memory cell 110 stores a low level "0", the second transistor unit 112 is turned off, and the data output terminal RBL remains low, i.e., is "0"; if a high level "1" is stored on the data storage node SN of the memory cell 110, the second transistor unit 112 is turned on, and a high level signal on the data read gate terminal RWL is transmitted to the data output terminal RBL, so that the data output terminal RBL is at a high potential, i.e., at "1".

Therefore, when one memory cell 110 is gated, data on its data storage node SN can be effectively transferred to the data output terminal RBL.

Meanwhile, each of the memory cells 110 further includes a switching unit 113. The switching unit 113 is turned off when the data read gate terminal RWL of the memory unit 110 is not turned on. Therefore, the signal of the selected memory cell 110 is not transmitted to other memory cells 110 while being transmitted to the data output terminal RBL.

For example, when the data output terminal RBL1 of the first memory cell 110 is turned on, the switching units 113 of the other memory cells 110 are all turned off. At this time, the data stored on the data storage node SN of the first storage unit 110 is not transferred to the other storage units, but is transferred only to the data output terminal RBL.

At this time, it is ensured that the signal of the selected memory cell 110 can be accurately and effectively transmitted to the data output terminal RBL. At the same time, the influence on other memory cells 110 can be effectively prevented.

In one embodiment, the switching unit 113 includes a third transistor unit. One of the source electrode and the drain electrode of the third transistor unit is connected with the second transistor unit, and the other is connected with the data output end.

As an example, the conductivity type of the third transistor unit is N-type. At this time, the gate of the third transistor unit may be connected to the data read gate RWL of the memory cell 110 where it is located. Therefore, when the data read gate RWL of one memory cell 110 is turned on, the corresponding switching cells 113 are also turned on at the same time, so that the circuit control can be simplified.

Meanwhile, when the first transistor unit, the second transistor unit and the third transistor unit of the memory cell 110 are all N-type, the process is also convenient.

Specifically, as an example, the first transistor unit, the second transistor unit, and the third transistor unit may each include an IGZO Thin Film Transistor (TFT). The IGZO TFT can effectively realize the arrangement of the memory cell 110 on the plurality of memory layers 100a arranged in a stack.

Of course, the conductivity type of the third transistor unit may be P-type. At this time, the gate of the third transistor unit may be connected to another signal terminal other than the data read gate terminal RWL. There is no limitation in this regard.

In one embodiment, referring to fig. 1, the memory cells 110 in each memory layer 100a of the pixel memory circuit 100 are all connected to the same data write gate WWL.

At this time, when the data write gate WWL is set at an on level (e.g., a high level), the first transistor unit 111 of each memory cell 110 may be turned on, so that writing of relevant data into each memory cell is effectively achieved.

In one embodiment, referring to fig. 3, a micro light emitting diode chip is also provided. The micro light emitting diode chip is provided with a plurality of any one of the pixel circuits 10 described above.

The plurality of pixel circuits 10 are arranged in an array. Specifically, the plurality of pixel circuits 10 may be arranged in a plurality of rows and a plurality of columns. The pixel circuits 10 located in the same row may share the data write and read gates WWL and RWL. The pixel circuits 10 in the same column may share the data writing terminal WBL.

In one embodiment, the micro light emitting diode chip includes a driving chip and a light emitting chip. The driving chip and the light emitting chip are bonded to form the micro light emitting diode chip.

Each memory layer 100a of the pixel memory circuit 100 may be formed on the driving chip and/or the light emitting chip.

Specifically, as an example, the method of manufacturing the micro light emitting diode chip may include:

in step S11, referring to fig. 4, a driving chip 20 and a light emitting chip 30 are provided.

The driving wafer 20 may include a first substrate 21 and a switching transistor unit 210. The first substrate 21 may include, but is not limited to, a silicon substrate. The switching transistor unit 210 is formed on the first substrate 21.

The light emitting wafer 30 may include a second substrate 31 and light emitting devices 220, and the light emitting devices 220 are formed on the second substrate 31. Specifically, the light emitting device 220 may include an N-type semiconductor layer, a light emitting layer, and a P-type semiconductor layer sequentially formed on the second substrate 31. The P-type semiconductor layer and the light emitting layer may be partially etched away to form a MESA step.

In step S12, referring to fig. 5, a plurality of storage layers 100a are sequentially formed on the driving wafer 20.

Specifically, a plurality of memory layers 100a disposed at intervals may be sequentially formed over the switching transistor unit 210. An interlayer dielectric layer may be disposed between the switching transistor unit 210 and the memory layer 100a, and between adjacent memory layers 100a.

In step S13, referring to fig. 6, the driving wafer 20 is bonded to the light emitting wafer 30.

Specifically, the first bonding layer 22 may be formed on the side of the driving wafer 20 facing the light emitting wafer 30. A first passivation layer 23 may be further provided between the first bonding layer 22 and the memory layer 100a adjacent to the light emitting wafer 30. And the first bonding layer 22 may include a first metal layer 221 and a first dielectric layer 222.

The light emitting wafer 30 side facing the driving wafer 20 may form a second bonding layer 32. A second passivation layer 33 may be further provided between the second bonding layer 32 and the MESA step of the light emitting device 220. And the second bonding layer 32 may include a second metal layer 321 and a second dielectric layer 322.

In bonding, the first metal layer 221 may be bonded to the second metal layer 321, while the first dielectric layer 222 is bonded to the second dielectric layer 322. After bonding, the source of the switching transistor unit 210 may be connected to the light emitting device 220 through a conductive plug, a metal layer, and the like.

In step S14, the bonded driving wafer 20 and light emitting wafer 30 are diced to form a plurality of micro light emitting diode chips, which are not shown.

Specifically, after dicing, the driving wafer 20 forms a plurality of driving chips, and the light emitting wafer 30 forms a plurality of light emitting chips.

Alternatively, as another example, the manufacturing method of the micro light emitting diode chip may include:

in step S21, referring to fig. 7, a driving chip 20 and a light emitting chip 30 are provided.

The driving wafer 20 may include a first substrate 21 and a switching transistor unit 210. The switching transistor unit 210 is formed on the first substrate 21. The first substrate 21 may include, but is not limited to, a silicon substrate.

The light emitting wafer 30 may include a second substrate 31 and light emitting devices 220, and the light emitting devices 220 are formed on the second substrate 31.

In step S22, referring to fig. 8, a plurality of storage layers 100a are sequentially formed on the light emitting chip 30.

Specifically, a plurality of memory layers 100a disposed at intervals may be sequentially formed over the light emitting device 220. An interlayer dielectric layer may be disposed between the light emitting device 220 and the memory layer 100a, and between adjacent memory layers 100a.

In step S23, referring to fig. 9, the driving wafer 20 is bonded to the light emitting wafer 30.

Specifically, the first bonding layer 22 may be formed on the side of the driving wafer 20 facing the light emitting wafer 30. A first passivation layer 23 may be further provided between the first bonding layer 22 and the switching transistor unit 210. And the first bonding layer 22 may include a first metal layer 221 and a first dielectric layer 222.

The light emitting wafer 30 side facing the driving wafer 20 may form a second bonding layer 32. A second passivation layer 33 may also be provided between the second bonding layer 32 and the memory layer 100a adjacent to the driver wafer 20. And the second bonding layer 32 may include a second metal layer 321 and a second dielectric layer 322.

In step S24, the bonded driving wafer 20 and light emitting wafer 30 are diced to form a plurality of micro light emitting diode chips, which are not shown.

In one embodiment, referring to fig. 5, there is also provided a driving wafer 20, comprising: a first substrate 21, a switching transistor unit 210, and any of the pixel storage circuits 100 described above. The switching transistor unit 210 is formed on the first substrate 21. Each memory layer 100a of the pixel memory circuit 100 is sequentially stacked on the switching transistor unit 210.

In one embodiment, referring to fig. 8, there is also provided a light emitting die 30, comprising: a second substrate 31, a light emitting device 220, and any of the pixel storage circuits 100 described above. The light emitting device 220 is formed on the second substrate 31. The memory layers 100a of the pixel memory circuit 100 are sequentially stacked on the light emitting device 220.

In the description of the present specification, reference to the terms "some embodiments," "other embodiments," "desired embodiments," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the utility model. In this specification, schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.

The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the utility model. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.

Claims

1. A pixel circuit, comprising:

2. The pixel circuit according to claim 1, wherein the storage unit includes:

3. The pixel circuit according to claim 2, wherein the switching unit includes a third transistor unit, one of a source and a drain of the third transistor unit being connected to the second transistor unit, the other being connected to the data output terminal.

4. A pixel circuit according to claim 3, wherein the gate of the third transistor unit is connected to the data read gate of the memory cell in which it is located.

5. The pixel circuit of claim 3, wherein the first transistor unit, the second transistor unit, and the third transistor unit each comprise IGZO thin film transistors.

6. The pixel circuit of claim 2, wherein the memory cells in each of the memory layers are connected to the same data write gate.

7. A micro light emitting diode chip characterized in that a plurality of the pixel circuits according to any one of claims 1 to 6 are provided, and a plurality of the pixel circuits are arranged in an array.

8. The micro light emitting diode chip of claim 7, wherein the micro light emitting diode chip comprises:

a driving chip;

a light emitting chip bonded to the light emitting chip;

9. A driver wafer, comprising:

a first substrate;

a switching transistor unit on the first substrate;

a pixel circuit according to any one of claims 1 to 6, wherein each of the storage layers of the pixel storage circuit is sequentially stacked on the switching transistor unit.

10. A light emitting die, comprising:

a second substrate;

a light emitting device on the second substrate;

the pixel circuit according to any one of claims 1 to 6, wherein each of the memory layers of the pixel memory circuit is sequentially stacked on the light emitting device.