CN219246042U

CN219246042U - Reset circuit and device for clearing main control chip CMOS

Info

Publication number: CN219246042U
Application number: CN202223234841.8U
Authority: CN
Inventors: 陆德艺
Original assignee: Shenzhen Inovance Technology Co Ltd
Current assignee: Shenzhen Inovance Technology Co Ltd
Priority date: 2022-12-02
Filing date: 2022-12-02
Publication date: 2023-06-23
Anticipated expiration: 2032-12-02

Abstract

The application relates to the technical field of circuit control and discloses a reset circuit and a device for clearing a main control chip CMOS, wherein the circuit comprises: the device comprises a main control chip circuit, a power supply switch circuit and a power supply module; the power supply module is respectively connected with the power supply switch circuit and the control chip circuit; the power supply switch circuit is respectively connected with the control chip circuit and the main control chip circuit; the control chip circuit is connected with the main control chip circuit, wherein the control chip circuit is used for controlling the power supply switch circuit to supply power and controlling the main control chip circuit to reset. The method and the device improve the degree of automation of clearing the CMOS of the main control chip.

Description

Reset circuit and device for clearing main control chip CMOS

Technical Field

The utility model relates to the technical field of circuit control, in particular to a reset circuit and a device for clearing a main control chip CMOS.

Background

The traditional reset mode for clearing the CMOS of the main control chip is to push the physical key by manual operation or directly remove the RTC (Real-Time Clock) battery through a circuit of the physical key, so as to realize the function of clearing the CMOS.

The existing reset mode for clearing the CMOS of the main control chip is low in automation degree and inconvenient to maintain due to manual operation.

Disclosure of Invention

The utility model mainly aims at providing a reset circuit and a reset device for clearing a main control chip CMOS, and aims at improving the degree of automation for clearing the main control chip CMOS.

In order to achieve the above purpose, the utility model provides a reset circuit for clearing a main control chip CMOS, wherein the reset circuit for clearing the main control chip CMOS comprises a main control chip circuit, a power supply switch circuit and a power supply module;

the power supply module is respectively connected with the power supply switch circuit and the control chip circuit;

the power supply switch circuit is respectively connected with the control chip circuit and the main control chip circuit; the control chip circuit is connected with the main control chip circuit, wherein the control chip circuit is used for controlling the power supply switch circuit to supply power and controlling the main control chip circuit to reset.

Optionally, the control chip circuit includes control chip, first resistance, second resistance, third resistance and mistake trigger circuit, control chip includes first control port, second control port, first receipt data port, first transmission data port and first power port, first power port with power supply module is connected, first receipt data port with the first end of first resistance is connected, the second end of first resistance with main control chip circuit connection, first transmission data port with the first end of second resistance is connected, the second end of second resistance with main control chip circuit connection, first control port with mistake trigger circuit is connected, mistake trigger circuit with main control chip circuit connection, the second control port with the first end of third resistance is connected, the second end of third resistance with power supply switch circuit connection.

Optionally, the control chip is an MCU chip or an FPGA chip.

Optionally, the false triggering circuit includes a first MOS tube, a fourth resistor and a fifth resistor, where a source of the first MOS tube is connected with a first end of the fifth resistor and the first control port, a drain of the first MOS tube is connected with the main control chip circuit, a gate of the first MOS tube is connected with a first end of the fourth resistor, and a second end of the fifth resistor and a second end of the fourth resistor are connected with the power supply module.

Optionally, the first MOS transistor is an NMOS transistor.

Optionally, the main control chip circuit includes main control chip, diode, sixth resistance and seventh resistance, main control chip includes reset port, second receipt data port, second transmission data port and second power port, the second power port with power supply switch circuit connects, the reset port with the positive pole of diode is connected, the negative pole of diode with the drain electrode of first MOS pipe is connected, the second receipt data port with the first end of sixth resistance is connected, the second end of sixth resistance with the second end of second resistance is connected, the second transmission data port with the first end of seventh resistance is connected, the second end of seventh resistance with the second end of first resistance is connected.

Optionally, the power supply switch circuit includes a second MOS tube, a third MOS tube, a fourth MOS tube, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor, the power supply module is connected to the first end of the eighth resistor, the first end of the ninth resistor, and the source of the fourth MOS tube, the drain of the fourth MOS tube is connected to the second power port, the gate of the fourth MOS tube is connected to the second end of the ninth resistor and the source of the third MOS tube, the gate of the third MOS tube is connected to the second end of the eighth resistor and the source of the second MOS tube after being connected to the first end of the twelfth resistor, the drain of the third MOS tube is connected to the second end of the twelfth resistor, the drain of the second MOS tube is connected to the second end of the eleventh resistor, and then is connected to the system power ground, the gate of the second MOS tube is connected to the first end of the eleventh resistor and the second end of the tenth resistor, and the tenth resistor are connected to the third resistor.

Optionally, the second MOS transistor and the third MOS transistor are NMOS transistors, and the fourth MOS transistor is a PMOS transistor.

Optionally, the power supply module includes a first power supply unit and a second power supply unit, the first power supply unit is connected with the first end of the eighth resistor, and the second power supply unit is connected with the second end of the fourth resistor.

In addition, the application also provides a reset device for clearing the main control chip CMOS, and the reset device for clearing the main control chip CMOS comprises the reset circuit for clearing the main control chip CMOS.

The application provides a reset circuit for clearing a main control chip CMOS, which comprises a main control chip circuit, a power supply switch circuit and a power supply module; the power supply module is respectively connected with the power supply switch circuit and the control chip circuit; the power supply switch circuit is respectively connected with the control chip circuit and the main control chip circuit; the control chip circuit is connected with the main control chip circuit, wherein the control chip circuit is used for controlling the power supply switch circuit to supply power and controlling the main control chip circuit to reset. The main control chip circuit is connected with the control chip circuit to detect whether normal communication is performed between the main control chip circuit and the control chip circuit, the main control chip in the main control chip circuit is controlled to reset the CMOS, meanwhile, the control chip circuit is connected with the power supply switch circuit, the power supply in the main control chip circuit is disconnected through the control power supply switch circuit when the main control chip is controlled to reset the CMOS, therefore, the problem that in the prior art, a physical key can only be pressed by manual operation or an RTC battery is directly removed is avoided, the phenomenon of removing the CMOS function is realized, the main control chip circuit is controlled to realize automatic CMOS reset, the power supply in the main control chip circuit is disconnected through the control chip circuit, the CMOS function is further realized, and the degree of automation of removing the CMOS of the main control chip can be improved.

Drawings

FIG. 1 is a schematic diagram of a reset circuit for clearing a CMOS of a main control chip;

FIG. 2 is a schematic diagram showing the circuit connection of a control chip in a reset circuit for clearing a CMOS of a main control chip;

FIG. 3 is a schematic diagram showing the circuit connection of a master control chip in a reset circuit for clearing the CMOS of the master control chip;

FIG. 4 is a schematic diagram showing the connection of a power supply switch circuit in a reset circuit for clearing a main control chip CMOS;

FIG. 5 is a timing chart of the normal start of the master control chip in the reset circuit for clearing the CMOS of the master control chip;

fig. 6 is a timing chart of clearing abnormal starting of the main control chip in the reset circuit of the main control chip CMOS according to the present utility model.

Reference numerals illustrate:

reference numerals	Name of the name	Reference numerals	Name of the name
				10	Main control chip circuit	20	Control chip circuit
30	Power supply switching circuit	40	Power supply module
				22	False trigger circuit	21	Control chip
R1	First resistor	R2	Second resistor
				R3	Third resistor	R4	Fourth resistor
R5	Fifth resistor	R6	Sixth resistor
				R7	Seventh resistor	R8	Eighth resistor
R9	Ninth resistor	R10	Tenth resistor
				R11	Eleventh resistor	R12	Twelfth resistor
Q1	First MOS tube	Q2	Second MOS tube
				Q3	Third MOS tube	Q4	Fourth MOS tube
VCC1	First power supply port	VCC2	Second power supply port
				RX1	First receiving data port	RX2	Second receiving data port
TX1	First transmitting data port	TX2	Second transmitting data port
				IO1	First control port	IO2	Second control port
11	Main control chip	41	First power supply unit
				42	Second power supply unit	D1	Diode
RTC	Reset port

The achievement of the objects, functional features and advantages of the present utility model will be further described with reference to the accompanying drawings, in conjunction with the embodiments.

Detailed Description

It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.

It should be noted that all directional indicators (such as up, down, left, right, front, and rear … …) in the embodiments of the present application are merely used to explain the relative positional relationship, movement, etc. between the components in a specific posture (as shown in the drawings), and if the specific posture is changed, the directional indicator is correspondingly changed.

In the present application, unless explicitly specified and limited otherwise, the terms "coupled," "secured," and the like are to be construed broadly, and for example, "secured" may be either permanently attached or removably attached, or integrally formed; can be mechanically or electrically connected; either directly or indirectly, through intermediaries, or both, may be in communication with each other or in interaction with each other, unless expressly defined otherwise. The specific meaning of the terms in this application will be understood by those of ordinary skill in the art as the case may be.

In addition, descriptions such as those related to "first," "second," and the like, are provided for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated in this application. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions of the embodiments may be combined with each other, but it is necessary to base that the technical solutions can be realized by those skilled in the art, and when the technical solutions are contradictory or cannot be realized, the combination of the technical solutions should be regarded as not exist and not within the protection scope of the present application.

The utility model provides a reset circuit for clearing a main control chip CMOS, referring to a structural schematic diagram of the reset circuit for clearing the main control chip CMOS in FIG. 1, the reset circuit for clearing the main control chip CMOS comprises a main control chip circuit 10, a control chip circuit 20, a power supply switch circuit 30 and a power supply module 40;

the power supply module 40 is connected with the power supply switch circuit 30 and the control chip circuit 20 respectively;

the power supply switch circuit 30 is respectively connected with the control chip circuit 20 and the main control chip circuit 10; the control chip circuit 20 is connected with the main control chip circuit 10, wherein the control chip circuit 20 is used for controlling the power supply switch circuit to supply power and controlling the main control chip circuit to reset.

In this embodiment, in the prior art, only a circuit of a physical key can be used to manually operate and press the physical key or directly disassemble the RTC battery, so as to implement the CMOS function, and this way has low automation degree and brings great inconvenience to maintenance.

Based on the above problems, a reset circuit for automatically clearing the CMOS of the main control chip is provided, and the main control chip can be an X86 chip, other control chips or a singlechip. The main principle is as follows: the communication connection between the main control chip circuit 10 and the control chip circuit 20 is connected with a control instruction, so that after whether normal communication between the two is detected, a corresponding control instruction is output through the control instruction connection, wherein the control instruction refers to an instruction for controlling the main control chip circuit 10 to execute processing and can be in a high-low level; on the other hand, the main control chip circuit 10 is powered off when resetting the CMOS, and is connected with the power supply switch circuit through the control chip circuit, and the power supply in the main control chip circuit is disconnected through the control power supply switch circuit when the main control chip is reset. That is to say, the implementation flow is: the control chip circuit 20 detects that the communication with the main control chip circuit 10 is normal, sends a control instruction to control the main control chip circuit 10 not to reset the CMOS, and controls the power supply switch circuit to be normally connected to supply power to the main control chip circuit 10; the control chip circuit 20 detects abnormal communication with the main control chip circuit 10, the control instruction controls the power supply switch circuit to disconnect to power off the main control chip circuit 10, then controls the main control chip circuit 10 to reset the CMOS, and further controls the power supply switch circuit to disconnect the power supply in the main control chip circuit when the control chip circuit controls the main control chip circuit to realize automatic CMOS reset, thereby realizing the function of clearing the CMOS, improving the intelligence of clearing the CMOS of the main control chip, and improving the convenience of clearing the CMOS of the main control chip based on the condition that the circuit capable of only resetting through one physical key.

Further, in still another embodiment of the reset circuit for clearing the main control chip CMOS of the present application, referring to fig. 2, fig. 2 is a schematic diagram of a circuit connection of a control chip in the reset circuit for clearing the main control chip CMOS, the control chip circuit 20 includes a control chip 21, a first resistor R1, a second resistor R2, a third resistor R3, and a false triggering circuit 22, the control chip 21 includes a first control port IO1, a second control port IO2, a first receiving data port RX1, a first transmitting data port TX1, and a first power port VCC1, the first power port VCC1 is connected with the power supply module 40, the first receiving data port RX1 is connected with a first end of the first resistor R1, a second end of the first resistor R1 is connected with a first end of the main control chip circuit 10, a second end of the second resistor R2 is connected with the main control chip circuit 10, the first control port VCC1 is connected with the false triggering circuit 22, and the third resistor R3 is connected with the first end of the false triggering circuit 10.

Specifically, the control chip 21 is an MCU chip or an FPGA chip.

Specifically, the false triggering circuit 22 includes a first MOS transistor Q1, a fourth resistor R4, and a fifth resistor R5, where a source of the first MOS transistor Q1 is connected to a first end of the fifth resistor R5 and the first control port IO1, a drain of the first MOS transistor Q1 is connected to the main control chip circuit 10, a gate of the first MOS transistor Q1 is connected to a first end of the fourth resistor R4, and a second end of the fifth resistor R5 and a second end of the fourth resistor R4 are connected to the power supply module 40.

Specifically, the first MOS transistor Q1 is an NMOS transistor.

Further, in still another embodiment of the reset circuit for clearing the main control chip CMOS of the present application, referring to fig. 3, fig. 3 is a schematic diagram of circuit connection of the main control chip in the reset circuit for clearing the main control chip CMOS, the main control chip circuit 10 includes a main control chip 11, a diode D1, a sixth resistor R6 and a seventh resistor R7, the main control chip 11 includes a reset port RTC, a second receiving data port RX2, a second transmitting data port TX2 and a second power port VCC2, the second power port VCC2 is connected with the power supply switch circuit 30, the reset port RTC is connected with an anode of the diode D1, a cathode of the diode D1 is connected with a drain of the first MOS transistor Q1, the second receiving data port RX2 is connected with a first end of the sixth resistor R6, a second end of the sixth resistor R6 is connected with a second end of the second resistor R2, the second transmitting data port TX2 is connected with a first end of the seventh resistor R7, and a second end of the seventh resistor R7 is connected with a second end of the first resistor R1.

In this embodiment, the control chip circuit 20 realizes the control based on whether to perform normal communication with the main control chip circuit 10, and further generates a control instruction to perform control, so as to realize the reset of the main control chip CMOS intelligently. The control chip 21 in the control chip circuit 20 may be an MCU chip or an FPGA chip or a single chip microcomputer, etc. When the main control chip is exemplified by X86, the control chip 21 is exemplified by an FPGA chip. Referring to fig. 5, fig. 5 is a timing chart of normal start of the master chip in the reset circuit for clearing the CMOS of the master chip, wherein TX2_rx1 and RX2_tx1 in the drawing refer to UART communication between the FPGA chip and the X86 chip, and 3A, 1B, 1C, and 4A represent connection points, for example, 3A in fig. 2 and 3A in fig. 4 are connection relations. When the x86 main control chip is started normally, the x86 main control chip and the FPGA control chip can normally complete UART communication (data transmission and reception are realized through the second receiving data port RX2, the second transmitting data port TX2, the first receiving data port RX1 and the first transmitting data port TX 1), the FPGA controls the signal of the power supply switching circuit to be low level (default value, actual second control port IO2 output), and the signal of the RTC reset circuit to be high level (default value, actual first control port IO1 output); referring to fig. 6, fig. 6 is a timing chart of clearing abnormal starting of the main control chip in the reset circuit of the CMOS main control chip, when the x86 main control chip is abnormal in starting, the x86 main control chip and the FPGA control chip cannot normally complete UART communication, after a time delay T1 set by user definition, a signal output from the FPGA second control port IO2 to the control power supply switching circuit is at a high level, power supply is turned off, and a signal output from the second control port IO2 to the reset port RTC is at a low level, the CMOS of the x86 main control chip is cleared, and after a time delay T2, the FPGA controls the RTC reset circuit signal to be at a high level, and controls the signal of the power supply switching circuit to be at a low level, so that power supply is turned on. The design of the false trigger circuit 22 and diode D1 prevents current flow back and false triggering. By means of the unidirectional conduction characteristic of the D1 diode, the current of the FPGA is prevented from flowing backward to the x86 main control chip, namely Vx86-Vfpga is larger than 0.3V and is conducted, the current direction can only be the direction from x86 to the FPGA, vx86 refers to the voltage of D1 near the x86 chip end, and Vfpga refers to the voltage of D1 near the FPGA chip end. By means of the switching characteristic of Q1, the low-level reset RTC of the FPGA control pin is realized, and the high level cannot influence the RTC (the unidirectional conduction characteristic of D1) of x 86. Vd1 and Vq1 due to conduction voltage drops of D1 and Q1, and circuit formula

Vd1+Vq1+Vfpga=Vrtc0.25v2 (Vd 1 diode conducting voltage, taking 0.3V, vq1 refers to MOS tube conducting voltage, taking 0.2V, V2 refers to voltage of accessing the main control chip 11, taking 3.3V, vrtc refers to voltage of needing to reset the main control chip), and the FPGA control pin voltage Vfpga <0.325V can drive RTC to reset, so that influence of an interference source on a circuit and false triggering are greatly reduced. That is, the whole control can not be reset due to false triggering caused by voltage fluctuation, and the intelligence of the main control chip CMOS and the control accuracy are improved.

Further, in still another embodiment of the reset circuit for clearing the main control chip CMOS according to the present application, referring to fig. 4, fig. 4 is a schematic diagram of a power supply switch circuit connection in the reset circuit for clearing the main control chip CMOS, the power supply switch circuit 30 includes a second MOS transistor Q2, a third MOS transistor Q3, a fourth MOS transistor Q4, an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11, and a twelfth resistor R12, the power supply module 40 is connected to a first end of the eighth resistor R8, a first end of the ninth resistor R9, and a source of the fourth MOS transistor Q4, a drain of the fourth MOS transistor Q4 is connected to the second power supply port VCC2, a gate of the fourth MOS transistor Q4 is connected to a second end of the ninth resistor R9 and a source of the third MOS transistor Q3, a gate of the third MOS transistor Q3 is connected to a first end of the twelfth resistor R12, and then is connected to a first end of the eighth resistor R8, a first end of the ninth resistor R9 and a first end of the fourth MOS transistor Q9 is connected to a drain of the fourth MOS transistor Q4, and a drain of the fourth MOS transistor Q4 is connected to the second end of the fourth MOS transistor Q2 and the drain of the fourth MOS transistor Q3 is connected to the second end of the tenth resistor R10.

Specifically, the second MOS transistor Q2 and the third MOS transistor Q3 are NMOS transistors, and the fourth MOS transistor Q4 is a PMOS transistor.

Specifically, the power supply module 40 includes a first power supply unit 41 and a second power supply unit 42, where the first power supply unit 41 is connected to the first end of the eighth resistor R8, and the second power supply unit 42 is connected to the second end of the fourth resistor R4.

In this embodiment, when the first end of the tenth resistor R10, i.e. 3A in the drawing, receives a high level, the gate of the second MOS transistor Q2 is at a high level to turn on the second MOS transistor Q2, so that the source of the second MOS transistor Q2 is grounded, and the second power supply unit 42 may be further connected to VCC1 of the control chip, which requires 3.3V voltage control as the second end of the fourth resistor R4. That is, the gate of the third MOS transistor Q3 is at a low level, and the third MOS transistor Q3 is turned off. That is, the gate of the fourth MOS transistor Q4 is at a high level, so that the fourth MOS transistor Q4 is turned off, the current of the first power unit 41 cannot be transmitted to the second power port VCC2 of the main control chip 11, so that the main control chip 11 is powered off and the CMOS reset can be performed. The second MOS transistor Q2 and the third MOS transistor Q3 mainly prevent fluctuations in the circuit and fluctuations in other control power supplies from affecting the accuracy of control. On the contrary, when the main control chip is normally started and the first end of the tenth resistor R10 will receive the low level by default, the gate of the second MOS transistor Q2 is turned off at the low level, the gate of the third MOS transistor Q3 is turned on at the high level, the third MOS transistor Q3 is turned on, the gate of the fourth MOS transistor Q4 is turned on at the low level, and the fourth MOS transistor Q4 is turned on, so that the normal power supply operation of the first power supply unit 41 to the second power supply port VCC2 of the main control chip 11 is realized. And further, the power supply and the disconnection of the second power supply port VCC2 of the main control chip 11 are realized by controlling the high and low levels output to the power supply switch circuit 30. The power supply module 40 supplies power to the second power supply port VCC2 of the main control chip 11 on the one hand, and supplies power to the control chip circuit 20 by 3.3V through the second power supply unit 42 on the other hand, so that the control chip circuit 20 works normally. The power supply module 40 may be powered by a 24V DC power terminal, to provide power to the main control chip circuit, and to control the chip circuit.

The foregoing description is only of the preferred embodiments of the present application and is not intended to limit the scope of the claims, and all equivalent structural changes made in the present application and the accompanying drawings or direct/indirect application in other related technical fields are included in the scope of the present application.

Claims

1. The reset circuit for clearing the CMOS of the main control chip is characterized by comprising a main control chip circuit, a power supply switch circuit and a power supply module;

2. The reset circuit for clearing the CMOS of the main control chip according to claim 1, wherein the control chip circuit comprises a control chip, a first resistor, a second resistor, a third resistor and a false triggering circuit, the control chip comprises a first control port, a second control port, a first receiving data port, a first transmitting data port and a first power supply port, the first power supply port is connected with the power supply module, the first receiving data port is connected with a first end of the first resistor, a second end of the first resistor is connected with the main control chip circuit, the first transmitting data port is connected with a first end of the second resistor, a second end of the second resistor is connected with the main control chip circuit, the first control port is connected with the false triggering circuit, the false triggering circuit is connected with the main control chip circuit, the second control port is connected with a first end of the third resistor, and a second end of the third resistor is connected with the power supply switch circuit.

3. The reset circuit for clearing the CMOS of the main control chip according to claim 2, wherein the control chip is an MCU chip or an FPGA chip.

4. The reset circuit for clearing the CMOS of the main control chip according to claim 2, wherein the false triggering circuit comprises a first MOS tube, a fourth resistor and a fifth resistor, a source electrode of the first MOS tube is connected with a first end of the fifth resistor and the first control port, a drain electrode of the first MOS tube is connected with the main control chip circuit, a grid electrode of the first MOS tube is connected with the first end of the fourth resistor, and a second end of the fifth resistor and a second end of the fourth resistor are connected with the power supply module.

5. The reset circuit for clearing a main control chip CMOS as in claim 4, wherein said first MOS transistor is an NMOS transistor.

6. The reset circuit for clearing the CMOS of the main control chip according to claim 5, wherein the main control chip circuit comprises a main control chip, a diode, a sixth resistor and a seventh resistor, the main control chip comprises a reset port, a second receiving data port, a second transmitting data port and a second power port, the second power port is connected with the power supply switch circuit, the reset port is connected with the anode of the diode, the cathode of the diode is connected with the drain electrode of the first MOS tube, the second receiving data port is connected with the first end of the sixth resistor, the second end of the sixth resistor is connected with the second end of the second resistor, the second transmitting data port is connected with the first end of the seventh resistor, and the second end of the seventh resistor is connected with the second end of the first resistor.

7. The reset circuit for removing the CMOS of the main control chip of claim 6, wherein the power supply switch circuit comprises a second MOS transistor, a third MOS transistor, a fourth MOS transistor, an eighth resistor, a ninth resistor, a tenth resistor, an eleventh resistor, and a twelfth resistor, the power supply module is connected to the first end of the eighth resistor, the first end of the ninth resistor, and the source of the fourth MOS transistor, the drain of the fourth MOS transistor is connected to the second power supply port, the gate of the fourth MOS transistor is connected to the second end of the ninth resistor and the source of the third MOS transistor, respectively, the gate of the third MOS transistor is connected to the second end of the eighth resistor and the source of the second MOS transistor after being connected to the first end of the twelfth resistor, the drain of the third MOS transistor is connected to the system power supply ground after being connected to the second end of the twelfth resistor, the drain of the second MOS transistor and the second end of the eleventh resistor, and the tenth end of the tenth resistor are connected to the second end of the tenth resistor.

8. The reset circuit for clearing a main control chip CMOS as in claim 7, wherein said second MOS transistor and said third MOS transistor are NMOS transistors, and said fourth MOS transistor is a PMOS transistor.

9. The reset circuit for clearing a main control chip CMOS as in claim 7, wherein said power supply module comprises a first power supply unit and a second power supply unit, said first power supply unit is connected to a first end of said eighth resistor, and said second power supply unit is connected to a second end of said fourth resistor.

10. A reset device for clearing a main control chip CMOS, wherein the reset device for clearing a main control chip CMOS comprises the reset circuit for clearing a main control chip CMOS according to any one of claims 1 to 9.