CN219164552U - Phase-locked loop circuit - Google Patents
Phase-locked loop circuit Download PDFInfo
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- CN219164552U CN219164552U CN202223002456.0U CN202223002456U CN219164552U CN 219164552 U CN219164552 U CN 219164552U CN 202223002456 U CN202223002456 U CN 202223002456U CN 219164552 U CN219164552 U CN 219164552U
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The utility model provides a phase-locked loop circuit which comprises a frequency detector unit, a frequency divider unit, a voltage-controlled oscillator and a charge pump, wherein the frequency detector unit is electrically connected with the frequency divider unit, the frequency divider unit is electrically connected with the voltage-controlled oscillator, the voltage-controlled oscillator is electrically connected with the charge pump, the charge pump is electrically connected with the frequency detector unit, the frequency divider unit is grounded through a first resistor, the charge pump is grounded through a first capacitor, and two ends of the first capacitor are connected with a second resistor and a second capacitor which are mutually connected in series. The utility model has the advantages of simple circuit structure, less unit components and lower power consumption.
Description
Technical Field
The utility model relates to the technical field of electronics, in particular to a phase-locked loop circuit.
Background
A phase locked loop is a negative feedback control system that uses a voltage generated by phase synchronization to tune a voltage controlled oscillator to generate a target frequency, which is a typical feedback control circuit, and uses an externally input reference signal to control the frequency and phase of an oscillation signal inside the loop, so as to realize automatic tracking of the output signal frequency to the input signal frequency, and is generally used in a closed loop tracking circuit.
The phase-locked loop circuit has very high power consumption, and because the voltage-controlled oscillator and the frequency divider work at higher working frequency, larger working current is required to be consumed to work normally; in addition, the circuit structure is complex; the design complexity is high, and the overall design of the loop is usually very complex due to the complexity of the design of the voltage controlled oscillator and the non-ideality of the charge pump and the divider speed, as well as the overall performance of the loop, which need to be considered.
Disclosure of Invention
In view of the above, the present utility model provides a phase locked loop circuit.
In order to solve the technical problems, the utility model adopts the following technical scheme: the utility model provides a phase-locked loop circuit, includes frequency detector unit, frequency divider unit, voltage controlled oscillator and charge pump, the frequency detector unit with frequency divider unit electric connection, the frequency divider unit with voltage controlled oscillator electric connection, voltage controlled oscillator with charge pump electric connection, the charge pump with frequency detector unit electric connection, the frequency divider unit passes through first resistance ground connection, the charge pump passes through first electric capacity ground connection, first electric capacity both ends connect in parallel and have established ties each other second resistance and second electric capacity.
In the present utility model, preferably, the frequency detector unit includes a first nand gate, a first input end of the first nand gate is externally connected with a FREF terminal, a second input end of the first nand gate is externally connected with an output end of the second nand gate, an output end of the second nand gate is connected with a first input end of the second nand gate, an output end of the second nand gate is externally connected with an UP terminal through the first nand gate, the second nand gate is externally connected with a first input end of a third nand gate through the second nand gate, and an output end of the second nand gate is externally connected with a second input end of a fourth nand gate through the third nand gate.
In the present utility model, preferably, the frequency divider unit includes a first flip-flop, a second flip-flop, a third flip-flop, and a multiplexer, wherein a CKB terminal of the first flip-flop is connected to a FIN terminal, a Q terminal of the first flip-flop is connected to a CKB terminal of the second flip-flop, a Q terminal of the second flip-flop is connected to a CKB terminal of the third flip-flop, and is connected to an a terminal of the multiplexer, a B terminal of the multiplexer is connected to a Q terminal of the third flip-flop, and an output terminal of the multiplexer serves as an output terminal of the frequency divider unit.
The utility model has the advantages and positive effects that: the frequency detector unit of the present utility model is used for receiving an input signal and a feedback signal, and generating a control signal based on phase comparison of the input signal and the feedback signal; the charge pump is used for receiving the control signal from the phase frequency detector and generating the control signal of the initial voltage-controlled oscillator unit based on the control signal, and has the advantages of simple circuit structure, less unit device constitution quantity and lower power consumption.
Drawings
The accompanying drawings are included to provide a further understanding of the utility model and are incorporated in and constitute a part of this specification, illustrate the utility model and together with the embodiments of the utility model, serve to explain the utility model. In the drawings:
fig. 1 is an overall block diagram of a phase-locked loop circuit of the present utility model;
fig. 2 is a schematic diagram of a frequency detector unit of a phase locked loop circuit of the present utility model;
fig. 3 is a schematic diagram of a frequency divider unit of a phase locked loop circuit of the present utility model;
fig. 4 is a diagram of a phase locked loop circuit of the present utility model.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model.
It will be understood that when an element is referred to as being "fixed to" another element, it can be directly on the other element or intervening elements may also be present. When a component is considered to be "connected" to another component, it can be directly connected to the other component or intervening components may also be present. When an element is referred to as being "disposed on" another element, it can be directly on the other element or intervening elements may also be present. The terms "vertical," "horizontal," "left," "right," and the like are used herein for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this utility model belongs. The terminology used herein in the description of the utility model is for the purpose of describing particular embodiments only and is not intended to be limiting of the utility model. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
As shown in fig. 1, the utility model provides a phase-locked loop circuit, which comprises a frequency detector unit, a frequency divider unit, a voltage-controlled oscillator and a charge pump, wherein the frequency detector unit is electrically connected with the frequency divider unit, the frequency divider unit is electrically connected with the voltage-controlled oscillator, the voltage-controlled oscillator is electrically connected with the charge pump, the charge pump is electrically connected with the frequency detector unit, the frequency divider unit is grounded through a first resistor, the charge pump is grounded through a first capacitor, and two ends of the first capacitor are connected with a second resistor and a second capacitor which are mutually connected in series.
As shown in fig. 2, in this embodiment, the frequency detector unit further includes a first nand gate, a first input end of the first nand gate is externally connected with a FREF terminal, a second input end of the first nand gate is externally connected with an output end of the second nand gate, an output end of the second nand gate is connected with a first input end of the second nand gate, an output end of the second nand gate is externally connected with an UP terminal through the first nand gate, the second nand gate is externally connected with a first input end of a third nand gate through the second nand gate, and an output end of the second nand gate is externally connected with a second input end of a fourth nand gate through the third nand gate.
As shown in fig. 3 and 4, in this embodiment, further, the frequency divider unit includes a first flip-flop, a second flip-flop, a third flip-flop, and a multiplexer, where the CKB terminal of the first flip-flop is connected to the FIN terminal, the Q terminal of the first flip-flop is connected to the CKB terminal of the second flip-flop, the Q terminal of the second flip-flop is connected to the CKB terminal of the third flip-flop, and is connected to the a terminal of the multiplexer, the B terminal of the multiplexer is connected to the Q terminal of the third flip-flop, and the output terminal of the multiplexer is used as the output terminal of the frequency divider unit.
The frequency detector unit of the present utility model is used for receiving an input signal and a feedback signal, and generating a control signal based on phase comparison of the input signal and the feedback signal; the charge pump is used for receiving the control signal from the phase frequency detector and generating the control signal of the initial voltage-controlled oscillator unit based on the control signal, and has the advantages of simple circuit structure, less unit device constitution quantity and lower power consumption.
The foregoing describes the embodiments of the present utility model in detail, but the description is only a preferred embodiment of the present utility model and should not be construed as limiting the scope of the utility model. All equivalent changes and modifications within the scope of the present utility model are intended to be covered by this patent.
Claims (3)
1. The phase-locked loop circuit is characterized by comprising a frequency detector unit, a frequency divider unit, a voltage-controlled oscillator and a charge pump, wherein the frequency detector unit is electrically connected with the frequency divider unit, the frequency divider unit is electrically connected with the voltage-controlled oscillator, the voltage-controlled oscillator is electrically connected with the charge pump, the charge pump is electrically connected with the frequency detector unit, the frequency divider unit is grounded through a first resistor, the charge pump is grounded through a first capacitor, and two ends of the first capacitor are connected with a second resistor and a second capacitor which are mutually connected in series.
2. The pll circuit of claim 1, wherein the frequency detector unit comprises a first nand gate, a first input terminal of the first nand gate is externally connected with a FREF terminal, a second input terminal of the first nand gate is externally connected with an output terminal of a second nand gate, the output terminal of the second nand gate is connected with the first input terminal of the second nand gate, an UP terminal is externally connected with the output terminal of the second nand gate through the first nand gate, the second nand gate is externally connected with the first input terminal of a third nand gate through the second nand gate, and the output terminal of the second nand gate is externally connected with the second input terminal of a fourth nand gate through the third nand gate.
3. The phase-locked loop circuit of claim 1, wherein the frequency divider unit comprises a first flip-flop, a second flip-flop, a third flip-flop, and a multiplexer, wherein a CKB terminal of the first flip-flop is connected to a FIN terminal, a Q terminal of the first flip-flop is connected to a CKB terminal of the second flip-flop, a Q terminal of the second flip-flop is connected to a CKB terminal of the third flip-flop, and is connected to an a terminal of the multiplexer, a B terminal of the multiplexer is connected to a Q terminal of the third flip-flop, and an output of the multiplexer serves as an output of the frequency divider unit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223002456.0U CN219164552U (en) | 2022-11-08 | 2022-11-08 | Phase-locked loop circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202223002456.0U CN219164552U (en) | 2022-11-08 | 2022-11-08 | Phase-locked loop circuit |
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| Publication Number | Publication Date |
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| CN219164552U true CN219164552U (en) | 2023-06-09 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202223002456.0U Active CN219164552U (en) | 2022-11-08 | 2022-11-08 | Phase-locked loop circuit |
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| CN (1) | CN219164552U (en) |
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- 2022-11-08 CN CN202223002456.0U patent/CN219164552U/en active Active
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